2024 Program at a Glance - FMS: the Future of Memory and Storage

2024 Program at a Glance

01:00 PM to 02:45 PM

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PRO PDSA1: Quantum Memory: Superconducting Qubits & Quantum Computer HW Design - Pt 1

Room 209, Floor 2

Track: Professional Development Series (Pre-Conference)

Organizer + Presenter:

WeiTi Liu, General Partner, Quantum Technology

Wei-Ti Liu is a General Partner of Quantum Technology, LLC. He was previously Co-Founder/GM/VP Engineering at PLX Technology, a maker of PCI-based chipsets. At PLX, he oversaw operations, directly managed the engineering group, and managed the foundry interface. He was President/CEO of NetChip Technology (now Broadcom Inc), a USB controller maker, and a security device manufacturer. Wei-Ti has extensive experience in ASIC VLSI chip designs, and has also been a design engineer for IBM, AMD, and Intel. He earned an MSEE from the City College of New York and a BSEE from the National Taiwan University. He has presented at several Flash Memory Summits and holds twelve US patents in that area. Areas of Interest includes: Investing Quantum Technology, and Advising on Semiconductor related technology projects, MRAM design, 3D Die stacking, and Heterogeneous Integration Architecture Design. Quantum Computing Workshop Presenter, “The Fundamental of Quantum Computation and Quantum Information for Engineer— A Practical Approach”. Grove School of Engineering, The City College of The City University of New York. Tutorial Course Agenda: 1. Introduction to Quantum Computing and Application 2. Review of Linear Algebra—Basic 3. Qubits, Operators and Measurement 4. Quantum Gates 5. Complexity Theory—Introduction 6. Quantum Communication 7. Quantum Computing with IBM Quantum Experience (Hands-on experience) 8. Quantum Algorithms 9. Quantum Error Correction.

Pre-Con Seminar Description:

Unlike classical memory, quantum computing's "no-clone theorem" limited Quantum memory using classical memory's read/write operations; when we access or measure qubits, their information is inevitably destroyed. Therefore, we must rely on quantum operations, precisely entanglement, to access qubits. As quantum computers advance, they demand many digital and analog circuits to execute control and measurement functions. The proliferation of qubits in an array has led to a significant increase in control and measurement signals. This signal surge has created a scalability issue for quantum computers, posing a challenge in their design and operation. The number of digital and analog cryogenic CMOS circuits has also escalated, leading to power and scalability issues, necessitating innovative solutions for quantum memory hardware design. Quantum memory is essential to quantum computing applications like finance, quantum chemistry, cryptography, and scientific research. Quantum networks enable secure, faster, and longer-distance transfer of quantum information. Moreover, they require quantum repeaters and quantum memory. This Professional Development Session aims to motivate experienced hardware and software engineers to explore the quantum field. We are exploring the advantages of quantum computing in finance, cryptography, chemistry, and optimization. Furthermore, quantum networks enable faster, longer-distance quantum information transfer with a secure network. Quantum memory is a significant element of quantum computing, and we are gaining knowledge of quantum hardware design using superconducting qubits. Part 1: • Gain knowledge of quantum computing hardware elements and understand the technical knowledge needed to design quantum computers with quantum process units (QPU) interfaces with quantum control and measurements. • Gain the engineering knowledge for implementing quantum vs classical algorithms. • Gain knowledge of engineering requirements for quantum computing and understand the quantum advantage over classical computers. • We summarized the quantum computing hardware's requirements for quantum memory.

PRO PDSB1: CXL for Disaggregated Memory & Accelerators in Data Ctrs - Pt 1

Room 203, Floor 2

Track: Professional Development Series (Pre-Conference)

Organizer + Moderator:

Pankaj Mehra, Founder, Elephance

Pankaj Mehra is President and CEO of Elephance Memory. A contributor to InfiniBand 1.0 spec and an inventor of the first RDMA persistent memory devices and filesystems, Pankaj is a systems and software practitioner who conducts his research at the intersection of infrastructure and intelligence. He is a co-author/co-editor/co-inventor on 3 books, and over 100 papers and patents, and a builder of systems that have won recognition from NASA, Sandia National Labs, and Samsung Electronics, among others. He was a VP of Storage Pathfinding at Samsung, Senior Fellow and VP at SanDisk and Western Digital, WW CTO of Fusion-io, and Distinguished Technologist at HP Labs. Pankaj has held faculty positions at IIT Delhi and UC Santa Cruz.

Speakers:

Siamak Tavallaei, Sr. Principal Engineer, Samsung

Siamak Tavallaei is Sr. Principal Engineer at Samsung. He joined the CXL effort as a founding member of the CXL Consortium and co-chair of the Technical Task Force (TTF) in 2019 to develop the CXL 2.0 specification. He has served on the CXL Board of Directors and as the CXL President. In 2016, he joined Open Compute Project (OCP) as a co-lead of Server Project. He later served as the Incubation Committee Representative for the Server Project and Steering Committee where he drives open-sourced modular design concepts for integrated hardware/software solutions. Previously, he has served as Distinguished Technologist at HP, Senior Principal Architect at Microsoft Azure, and Chief Systems Architect at Google.

Samir Rajadnya, Principal Architect, Microsoft

Samir Rajadnya is a Principal Architect in Microsoft Azure Hardware Architecture team where he works on future memory systems. Prior to Microsoft, Samir spent many years innovating in memory, storage, and networking. Samir was key architect to productize 3DXP technology at Micron, architect, and designer at disruptive storage startup DSSD. He was an SOC architect and designer at Juniper Networks, Netronome and Intel. Samir has served as part of multiple industry standards bodies throughout his career, including CXL and CCIX. Samir received his master’s in electrical engineering from Indian Institute of Technology Bombay.

Manoj Wadekar, Hardware System Technologist, Meta

Manoj is the HW technologist and Mr. "Storage Guy" working at Meta. He is transforming hyper-scale infrastructure to drive performance and efficiency (proven for "ebay servers". He loves Technology Research and Innovation, Product and Technology Strategy, and defining Product Roadmaps/Business cases. He constantly drives Cross-industry initiatives and collaborations.

Pre-Con Seminar Description:

The motivation for disaggregating memory is rooted in a desire to support and promote vast in-memory computing systems but without the issues of stranding and up-front provisioning. The speakers in this session will systematically comprehensively cover the topic of memory disaggregation leveraging the CXL standard from a software and hardware perspective, highlighting both challenges and opportunities. We will pay close attention to characteristics and use of memory at a distance. We conclude with our projections about the future of memory attachment in data centers. Topics: - CXL 3 and an update on standards covering P2P - Composable Memory Systems and OpenCompute Project - AI roadmap through 2030, the AI flywheel and data, and specific projections regarding memory and storage needs of AI - An updated analysis of memory expansion for AI, Database, and Virtual Machine workloads - Computational Memory and Storage Programming - Updated findings from architecture and operating systems for disaggregated memory

PRO PDSC1: DRAM in an Increasingly Diverse Platform

Room 212, Floor 2

Track: Professional Development Series (Pre-Conference)

Organizer + Presenter:

Bill Gervasi, Principal Systems Architect, Wolley Inc

Mr. Gervasi has over 45 years of experience in high speed memory subsystem definition, design, and product development. Career highlights include 19 years at Intel where he was systems hardware designer, software designer, and strategic accounts manager. Mr. Gervasi became a memory specialist for companies including S3, Transmeta, Netlist, SimpleTech, and Nantero, and is now Principal Systems Architect for Wolley, developing CXL based memory solutions. Mr. Gervasi been involved in the definition of Double Data Rate SDRAM since its earliest inception. He has served on the JEDEC Board of Directors and chaired committees for DRAM parametrics and memory modules during the development of DDR1 through DDR6. He is currently the chairman of the JEDEC Alternative Memory committee. He received the JEDEC Technical Excellence award, their highest honor, in 2020.

Pre-Con Seminar Description:

Long gone are the days where DRAM and storage were the only two options for computer architectures. Chiplets, fabrics, and switching tiers have all entered the equation, and hybrids of memory and storage contribute to a top to bottom rethinking of data flow. Artificial intelligence as a dominant emerging technology is also affecting the equation where memory capacity requirements force a blending of multiple memory approaches to feed the beast. These new requirements are also driving an energy crisis, so total cost of ownership analyses are required to make good tradeoffs. Takeaways from this session: • Understand the new memory tiers including HBM and CXL • Analyze the new hybrid memory concepts such as memory semantic storage • Impact of artificial intelligence and new automotive architectures • What trends are on the mobile client and edge fronts • Why data centers waste so much energy and what can be done about it

PRO PDSD1: Advanced HDD Technology for the Data Center

Room 204, Floor 2

Track: Professional Development Series (Pre-Conference)

Organizer + Presenter:

Mohamad El-Batal, Sr. Director of Architecture, Seagate

Mohamad is on the Board of Directors of the Non-Volatile Memory Express (NVMe), Flash Memory Summit (FMS), and Open Compute Project (OCP). Mohamad is currently the chair of the NVMe-HDD working group and driving its requirements specification. He is also the chair of the OCP PCIe External Connectivity Workstream enabling PCIe to evolve with NVMe and Computer Express Link (CXL) into the Ultra-Low-Latency of optical fabric of choice. He was the author and chair of the Storage Bridge Bay (SBB) specification and was on the SBB board of directors for multiple years. Mohamad participated technically and influenced various industry groups including the FC, SAS, NVMe, CXL and GenZ consortiums. In his career, Mohamad worked at leading enterprise storage technology and cloud provider companies, including Tandem, EMC, Mylex, IBM, LSI, Engenio, NetApp and now Seagate. Mohamad has 30+ year history of enterprise and cloud storage architecture knowledge, experience, and innovation. Mohamad holds 50+ issued and 20+ pending patents, covering: High-Availability/Resiliency Storage and Memory solutions, SSD controller and Systems architecture focus areas.

Speakers:

Praveen Viraraghavan, Technologist, Seagate

Praveen Viraraghavan is the Technologist of the Product Line Management organization. In his role at Seagate, Praveen is given the opportunity to collaborate with other leaders to shape the portfolio across all parts of the Seagate product and research ecosystem. Praveen works closely with all customers to help align their storage strategy to Seagate’s product and technology roadmap. Praveen has a proven record owning hardware and software architecture strategy working with multiple levels of technical and corporate leadership. Praveen has a knowledge of the ecosystem related to data management, which allows advocacy for the customer’s requirements while still prioritizing the company’s business and technical options. Praveen holds a BS degree in Electrical Engineering and did some graduate work on VLSI design in 1997 from Purdue University at West Lafayette. During his storage career Praveen has worked from the lowest embedded layers, silicon development, product architecture and development up through to the software layer. Praveen led the architecture of many new first-pass success silicon developments and new HDD and SSD product lines at leading storage companies serving cloud and OEM customers. Praveen transitioned to a startup where is helped redefine the storage stack used in the cutting edge S3 on premise object storage software solution, the company was later acquired. Praveen has been a contributor to many industry standard bodies. In his career, Praveen worked at leading storage technology and cloud companies, including Western Digital, LSI Logic, Cleversafe (acquired by IBM) and now Seagate. Praveen has 25+ year history of enterprise and cloud storage architecture knowledge, experience, and innovation. Praveen holds 50+ issued and 25+ pending patents, covering: Silicon Control and Datapath, Command Handling, Distributed Object Storage, Filesystems, and Memory solutions. Praveen has won innovation awards from LSI and IBM and was an IBM Master Inventor. Praveen currently serves on 4 Seagate patent review boards in support of their continued innovation.

Pre-Con Seminar Description:

Greater than 88% of today's cloud storage is stored on Hard Disk Drive (HDD) media, and this majority percentage is expected to remain true for the near future. These storage track sessions will discuss why this is the case and will go deep into the incredibly complex but commoditized and simplified technologies that enabled this fact. We will present on the substantial technical breakthroughs that have enabled HDDs to continue their capacity growth rate, and then explain the difference between the major formatting technologies, CMR vs. SMR, then discuss in detail the PMR technical capabilities and limitations and then dive into HAMR media and recording technologies. We plan to discuss some of the myths surrounding HDD Near-Line storage capabilities and limitations and explain the justifications behind some of the current and future engineering innovations that enable HDDs to maintain their Total Cost of Ownership (TCO) supremacy over other leading storage solutions. Our intent is to inform and empower the audience of these sessions with key information and strategies that would help them understand the difference between the various available HDD technologies and enable them to best pick the right storage for the right usage model to optimize their storage TCO.

03:15 PM to 05:00 PM

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PRO PDSA2: Quantum Memory: Superconducting Qubits & Quantum Computer HW Design - Pt 2

Room 209, Floor 2

Track: Professional Development Series (Pre-Conference)

Organizer + Presenter:

Wei Lu, General Partner, Quantum Technology

Bio Not Available

Pre-Con Seminar Description:

Unlike classical memory, quantum computing's "no-clone theorem" limited Quantum memory using classical memory's read/write operations; when we access or measure qubits, their information is inevitably destroyed. Therefore, we must rely on quantum operations, precisely entanglement, to access qubits. As quantum computers advance, they demand many digital and analog circuits to execute control and measurement functions. The proliferation of qubits in an array has led to a significant increase in control and measurement signals. This signal surge has created a scalability issue for quantum computers, posing a challenge in their design and operation. The number of digital and analog cryogenic CMOS circuits has also escalated, leading to power and scalability issues, necessitating innovative solutions for quantum memory hardware design. Quantum memory is essential to quantum computing applications like finance, quantum chemistry, cryptography, and scientific research. Quantum networks enable secure, faster, and longer-distance transfer of quantum information. Moreover, they require quantum repeaters and quantum memory. This Professional Development Session aims to motivate experienced hardware and software engineers to explore the quantum field. We are exploring the advantages of quantum computing in finance, cryptography, chemistry, and optimization. Furthermore, quantum networks enable faster, longer-distance quantum information transfer with a secure network. Quantum memory is a significant element of quantum computing, and we are gaining knowledge of quantum hardware design using superconducting qubits. Part 2: • Understanding the quantum memory hardware design's challenges and qubit requirements • Understanding the critical difference between quantum memory vs classical memory array, Gaining knowledge of engineering requirements for quantum memory design • The hardware of a quantum computer-- system partition based on heat load • We summarize the technology requirements for quantum memory and quantum computers to scale up for sizeable quantum computing systems.

PRO PDSB2: CXL for Disaggregated Memory & Accelerators in Data Ctrs - Pt 2

Room 203, Floor 2

Track: Professional Development Series (Pre-Conference)

Organizer + Chairperson:

Pankaj Mehra, Founder, Elephance

Speakers:

Siamak Tavallaei, Sr. Principal Engineer, Samsung

Samir Rajadnya, Principal Architect, Microsoft

Samir Rajadnya is Cloud Infrastructure, and Systems architect at Microsoft bridging the gap between computing and memory/storage. He is passionate about innovating in cloud infrastructure optimizations. Vertical integration between applications, software, systems, and silicon can bring tremendous benefits in large-scale cloud environments. He has led/worked on systems and chips (FPGAs and ASICs) from concept to silicon with several first pass silicon successes.

Manoj Wadekar, Hardware System Technologist, Meta

Manoj Wadekar is a Hardware Systems Technologist driving storage and memory technology and roadmaps at Meta. Manoj has been designing and building servers, storage, and network solutions for over 30 years. He is leading the Composable Memory Systems group in OCP. Manoj has evangelized Memory and Storage Disaggregation, NVMe over Fabric, Lossless Ethernet (DCB/CEE) in industry conferences. Before joining Meta, he held engineering positions at eBay, QLogic and Intel.

Pre-Con Seminar Description:

PRO PDSC2: Introduction to High Bandwidth Memory (HBM)

Room 212, Floor 2

Track: Professional Development Series (Pre-Conference)

Organizer + Presenter:

Marc Greenberg, Principal Consultant and CEO, Marc Greenberg Consulting, LLC

Marc Greenberg is an independent consultant in memory, semiconductor and IP. Marc currently serves as VP of Product for Cassia.ai, an AI IP company, as vice-chair of an undisclosed task group at JEDEC, and as advisor to several other companies. Marc was responsible for product management of HBM and other memory and storage IP products at Denali, Cadence and Synopsys for 20 years out of a 30-year career in semiconductor and IP. Marc has a master's degree in Electronics from the University of Edinburgh in Scotland.

Pre-Con Seminar Description:

In this Professional Development Series session, you'll learn about key aspects of High Bandwidth Memory (HBM): What is HBM, a short history of HBM, why is HBM important right now, how Large Language Models (LLMs) and Generative AI are driving demand for HBM technology, comparison of HBM with other popular memory types (DDR, LPDDR and GDDR), a high level view of HBM architecture, PCB and package requirements to implement chips deploying HBM, a view of the market for HBM and the chips that use it, and a review of public information on the future development of high bandwidth memories.

PRO PDSD2: Optimizing HDD Performance in the Generative AI Data Center

Room 204, Floor 2

Track: Professional Development Series (Pre-Conference)

Organizer + Presenter:

Mohamad El-Batal, Sr. Director of Architecture, Seagate

Speakers:

Praveen Viraraghavan, Technologist, Seagate

Pre-Con Seminar Description:

Citigroup inc. analysts quote "Enterprise data is expected to continue to grow at over 40% CAGR as AI becomes an incremental driver for data creation, storage, and data management" Today's AI ecosystem require fundamental shifts in the requirements of every datacenter infrastructure component. The predominant AI infrastructure strategy tends to currently focus on the most drastically impactful infrastructure components, as in GPUs, CPUs and Memory. Unfortunately, this leaves a major gap in the detailed understanding of the various AI Storage Infrastructure usage models with regards to the various TCO optimized storage tiers and their requirements from a Capacity, Workloads and Performance.

08:30 AM to 09:35 AM

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Open AIML-101-1: Storage for AI: Technology

Ballroom B, Floor 1

Track: AI and ML Applications

Organizer + Moderator:

David McIntyre, Director Product Planning, Samsung Electronics

David McIntyre focuses on computational storage acceleration solutions development and strategic business enablement for cloud to edge applications including AI inference/video analytics, database processing and blockchain networks. He has held senior management positions with IBM, Samsung, Xilinx, Intel (formerly Altera) and at Silicon Valley startups. He has consulted for institutional investors including Fidelity, Goldman Sachs and UBS. David is a frequent presenter and chairperson at the Flash Memory Summit and other technical conferences including SNIA.

Paper Presenters:

Tejas Chopra, Sr. Engineer, Netflix, Inc.

Paper Title:

Memory Optimizations in Machine Learning

Paper Abstract:

As Machine Learning continues to forge its way into diverse industries and applications, optimizing computational resources, particularly memory, has become a critical aspect of effective model deployment. This session, "Memory Optimizations for Machine Learning," aims to offer an exhaustive look into the specific memory requirements in Machine Learning tasks and the cutting-edge strategies to minimize memory consumption efficiently. We'll begin by demystifying the memory footprint of typical Machine Learning data structures and algorithms, elucidating the nuances of memory allocation and deallocation during model training phases. The talk will then focus on memory-saving techniques such as data quantization, model pruning, and efficient mini-batch selection. These techniques offer the advantage of conserving memory resources without significant degradation in model performance. Additional insights into how memory usage can be optimized across various hardware setups, from CPUs and GPUs to custom ML accelerators, will also be presented.

Author Bio:

Tejas Chopra is a Sr. Engineer at Netflix working on the Machine Learning Platform. Previously, he was a part of the Content Engineering organization working on building Storage Infrastructure for Netflix content. Tejas is also the Co-Founder of GoEB1 - a thought leadership platform for immigrants. Tejas is a Sr. IEEE Member, a BCS Fellow, a 2x TEDx speaker, and has spoken at several conferences on Cloud Computing, Blockchain, and Storage Infrastructure. His has worked at companies like Box, Datrium, Samsung, Cadence, and Apple in the past and holds a Master's degree in Electrical and Computer Engineering from Carnegie Mellon University, Pittsburgh.

Chanson Lin, Founder/CEO, Embestor Technology

Paper Title:

Multi-layered Data Storage Architecture for AI/ML Systems.

Paper Abstract:

The AI/ML systems need high bandwidth memory / storage as at ML learning and AI inferencing computational iterations process. On the other respect, the collected Big data which is waiting for analyzing, or the computed / categorized valuable data, those need relatively big capacity and well-organized data storage. As a result, a single-layered data storage device cannot satisfy the overall system performance requirements for AI/ML systems. By presenting a novel multi-layered data storage architecture with SRAM, DRAM, NAND Flash memory, to provide the functions of I/O accessing, Memory accessing, High speed accessing to the multi-layered data storing pools, to increase the performance and efficiency of AI/ML Computing systems. The connection between the multi-layered data storage and the AI/ML Computing engine can be on CXL or organized multiple bus channels.

Author Bio:

Dr. Chanson Lin is the Founder / Chairman & CEO of EmBestor Technology, a company specializing in industrial, niche application, and embedded storage applications. The company focuses on memory storage controller design and flash memory-based storage architectures. He has over 20 years’ experience designing NAND flash memory controllers and invented over 100 patents in the area. Before founding EmBestor, he was General Manager of the NAND flash memory controller business unit of ITE Technology, General Manager of USBest, and President / co-founder of RiCHIP. He has published several articles on embedded systems, industrial applications and has given many conference presentations, including several at previous Flash Memory Summits. He earned a PhD in electrical engineering from the National Chiao Tung University (Taiwan) and an MSEE from the National Taiwan University.

Molly Presley, SVP Marketing, Hammerspace

Paper Title:

Driving Business Outcomes: The Dual Impact of AI in High-Tech Organizations

Paper Abstract:

The integration of Artificial Intelligence (AI) is becoming a critical factor in determining business success and competitiveness. This presentation will explore the dual impact of AI on this sector, highlighting both the immediate benefits and the long-term business results. We will discuss how AI technologies optimize operational efficiencies, enhance product innovation, and enable more effective risk management. The positive implications such as increased productivity, cost efficiency, and market responsiveness will be analyzed. Concurrently, we will discuss potential challenges and considerations, including investment costs, integration complexities, and the need for skilled workforce adaptation. Attendees will gain a comprehensive understanding of how AI can not only transform but also scale businesses, preparing them for future challenges and opportunities.

Author Bio:

Molly brings over 15 years of product and growth marketing leadership experience to the Hammerspace team. She is also the host of the Data Unchained podcast and part of the Superwomen in Flash leadership team. Molly has led the marketing organization and strategy at fast growth, innovators such as Pantheon Platform, Qumulo, Quantum Corporation, DataDirect Networks (DDN), and SpectraLogic. In these companies she was responsible for the go-to-market strategy for SaaS, hybrid cloud, and data center solutions across a range of data intensive verticals and use cases. At Hammerspace, Molly will lead the marketing organization and be responsible for inspiring data creators and data users to take full advantage of a truly global data environment.

Paper Session Description:

As the demand for high-performance AI/ML systems continues to grow, the need for multi-layered data storage architecture has become crucial. Traditional single-layered devices are unable to meet the high bandwidth memory and storage requirements of AI inferencing and ML learning processes. A novel approach incorporating SRAM, DRAM, and NAND Flash memory pools has been developed to enhance I/O and memory access speeds, improving overall system performance. This advanced architecture, utilizing CXL or multiple bus channels, aims to boost the efficiency of AI/ML computing systems by providing high-speed access to data storage layers. Attendees will gain insights into how this innovative design can drive business outcomes by optimizing operational efficiencies, fostering innovation, and preparing organizations for future challenges.

Open BMKT-101-1: Market Analyst Panel

GAMR 1 (Great America Meeting Room 1), Floor 2

Track: Business Strategies and Memory Markets

Organizer + Moderator:

Jean Bozman, President, Cloud Architects Advisors

Jean S. Bozman is President of Cloud Architects Advisors, a market research and consulting firm focused on hardware and software for enterprise and hybrid multi-cloud computing. She analyzes the markets for servers, storage, and software related to datacenters and cloud infrastructure. A highly-respected IT professional, she has spent many years covering the worldwide markets for operating environments, servers, and server workloads. She was a Research VP at IDC, where she focused on the worldwide markets for servers and server operating systems. She is a frequent conference participant as a speaker, chairperson, and organizer at such events as Flash Memory Summit, OpenStack, and Container World. She is often quoted in a variety of publications including BusinessWeek, Investor’s Business Daily, the Los Angeles Times, CNET, Bloomberg, and Reuters. Ms. Bozman has also been VP/Principal Analyst at Hurwitz and Associates and Sr Product Marketing Manager at Sandisk. She earned a master’s degree from Stanford.

Panel Members:

Camberley Bates, VP and Practice Lead, Futurum Group

Camberley serves as the VP and Practice Lead at The Futurum Group bringing over 25 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm. She joined The Futurum Group through their acquisition of Evaluator Group in 2023. As the Managing Director at Evaluator Group from 2009 until 2023 she built a highly respected team, known for its deep technical expertise delivering competitive and market knowledge backed by data based economic and hands-on experience with the technology and IT consulting services. Camberley began her career at IBM in sales and management. She holds a BS degree in International Business from California State University - Long Beach and executive certificates from Wellesley and Wharton School of Business.

Simone Bertolazzi, Technology and Market Analyst, Yole Intelligence

Simone Bertolazzi, PhD, is Principal Analyst (Memory) at Yole Group. As member of the Yole Group’s Memory team, he contributes on a day-to-day basis to the analysis of markets and technologies, their related materials, device architectures and fabrication processes. Previously, Simone carried out experimental research in the field of nanoscience and nanotechnology, focusing on emerging semiconducting materials and their opto-electronic device applications. He (co-) authored more than 20 papers in high-impact scientific journals and was awarded the prestigious Marie Curie Intra-European Fellowship. Simone obtained a PhD in physics in 2015 from École Polytechnique Fédérale de Lausanne (Switzerland), where he developed novel flash memory cells based on heterostructures of two-dimensional materials and high-κ dielectrics. Simone earned a double M. A. Sc. degree from Polytechnique de Montréal (Canada) and Politecnico di Milano (Italy), graduating cum laude.”

Avril Wu, Senior Research Vice President, TrendForce Corp.

TrendForce Research Vice President Avril Wu has well over a decade of professional experience specializing in various aspects of memory product research. Prior to her 10-year tenure with TrendForce, Avril had worked with an established memory company for more than two years, also covering the same sector. Despite focusing on the DRAM market initially, Avril extended her expertise in 2019 to include NAND Flash as well, meaning she is currently more than qualified to cover the entire memory sector.

Jeff Janukowicz, Vice President, IDC

Jeff Janukowicz is a Research Vice President at IDC where he provides insight and analysis on the SSD market for the Client PC, Enterprise Data Center, and Cloud market segments. In this role, Jeff provides expert opinion, in-depth market research, and strategic analysis on the dynamics, trends, and opportunities facing the industry. His research includes market forecasts, market share reports, and technology trends of clients, investor, suppliers, and manufacturers. Mr. Janukowicz has an extensive background in storage, semiconductors, and solid state technologies. He brings more than 20 years of experience within the technology industry to IDC, including more than 15 years in storage and the semiconductor industry. Jeff has held various leadership positions in marketing and engineering during his career and before joining IDC he was responsible for strategic marketing and business planning activities for Agere Systems, which was acquired by LSI (now Avago).

Panel Session Description:

In a shifting landscape of the DRAM market, the emergence of AI applications brings both challenges and opportunities for stakeholders. DDR5 technology is set to lead the charge in driving innovation and market growth. Our in-depth analysis explores the intricate dynamics of supply and demand, forecasting how DRAM prices will react to market forces. As DDR5 advances towards 1anm and 1bnm processes, alongside the increasing focus on HBM, the intersection with AI becomes paramount. This strategic roadmap provides valuable insights into supply/demand dynamics, capacity adjustments, growth projections, and major supplier strategies in the evolving DRAM market of 2025 and beyond.

Open DRAM-101-1: DRAM Technology-Scaling Challenges & Future Directions

Ballroom C, Floor 1

Track: DRAM

Paper Presenters:

Ataberk Olgun, PhD Student, SAFARI Research Group at ETH Zurich

Paper Title:

Scalable and Low Overhead Read Disturbance Mitigation

Paper Abstract:

DRAM chips are increasingly more vulnerable to read disturbance phenomena (e.g., RowHammer and RowPress), where repeatedly accessing DRAM rows causes bitflips in nearby rows due to DRAM density scaling. Even though many prior works develop various RowHammer solutions, these solutions incur non-negligible and increasingly higher system performance, energy, and hardware area overheads as RowHammer vulnerability worsens. We present an overview of the state-of-the-art RowHammer solutions. We introduce two new RowHammer solutions, ABACuS and CoMeT, that can securely prevent RowHammer bitflips at low chip area, performance, and energy cost. We demonstrate how well the two solutions scale with worsening RowHammer vulnerability, typically quantified with the number of DRAM row activations needed to induce the first RowHammer bitflip (RowHammer threshold) in a DRAM chip. We describe the key insights that make ABACuS and CoMeT low-cost even at a very low, future RowHammer threshold of 125. At this RowHammer threshold, ABACuS and CoMeT incur small performance overheads of 1.45% and 4.01%, on average across 61 workloads from five widely used benchmark suites, respectively.

Author Bio:

Ataberk Olgun is a Computer Architecture researcher and a Ph.D. student in SAFARI Research Group at ETH Zurich, Switzerland, led by Prof. Onur Mutlu. His research interests lie in the intersection between computer architecture and memory system reliability and performance.

Abdullah Yaglikci, Ph.D. Student, SAFARI Research Group at ETH Zurich

Paper Title:

Scalably Mitigating DRAM Read Disturbance via Experimental Insights into Chips

Paper Abstract:

DRAM is the prevalent main memory technology due to its high density and low latency characteristics. The increasing need for faster access rates and larger DRAM capacity motivates improving the DRAM chip density. Manufacturing technology node size shrinks over DRAM chip generations to provide higher DRAM chip density. This technology scaling causes DRAM cell size and cell-to-cell distance to reduce significantly. As a result, DRAM cells become more vulnerable to read disturbance, i.e., accessing a DRAM cell disturbs data stored in another physically nearby cell. To provide a deeper understanding of and solutions to DRAM read disturbance, we 1) conduct experimental studies on real DRAM chips where we investigate the effects of temperature, access patterns, intra-chip variations, and wordline voltage; and 2) propose architecture-level solutions to mitigate DRAM read disturbance while it is exacerbated by technology node scaling and existing mitigations face practicality challenges due to a fundamental need for exposing proprietary information. This talk will provide a summary of these works.

Author Bio:

Giray is a Ph.D. candidate in the Safari Research Group at ETH Zürich, working with Prof. Onur Mutlu. His current broader research interests are in computer architecture, systems, and hardware security with a special focus on DRAM robustness and performance. In particular, his PhD research focuses on understanding and solving DRAM read disturbance vulnerability. Giray has published several works on this topic in major venues such as HPCA, MICRO, ISCA, DSN, and SIGMETRICS. One of these works, BlockHammer, was named as a finalist by Intel in 2021 for the Intel Hardware Security Academic Award. Giray's research is in part supported by Google and the Microsoft Swiss Joint Research Center.

ByeongSoo Kang, ETCH ENGINEER, SK hynix

Paper Title:

Plasma Etching Behavior of Y2O3 coatings by SF6 Plasma Pre-Treatment

Paper Abstract:

As DRAM cell scaling reaches its limit, SK Hynix is conducting various studies to continue the advancement of DRAM technology. Engineers face several challenges in overcoming the limitations of technology. One of the most significant issues faced by the industry is the coating material of the inner chamber wall. because fluorine-based gas is more required as we are entering into a smaller DRAM technology node. In order to meet the requirements for future coating material of the inner chamber wall, it is therefore imperative to develop a coating material with higher erosion resistance, better chemical stability, and fewer contamination particles. The coating material of the inner chamber has been upgraded from SiO2 to Al2O3 to Y2O3. But, recently many engineers have focused on yttrium oxide coating parts to solve the issue of reducing the initial etching rate in semiconductor process chambers. In this study, it was studied how SF6 plasma pre-treatment affects the initial etching rate shift. After pre-treatment with SF6 plasma, the surface of the Y2O3 coating was fluorinated to form a chemically stable YOxFy film. Then, as a result of the SNC partition process, the variable etch time shift was reduced by 66.7% (3.69"â1.23"). The initial CD degradation was improved by 83% (4.41â0.48). These results indicate that the surface of the Y2O3 coating, which was pre-treated with SF6 plasma, is more erosion-resistant than the non-treated Y2O3 film. Therefore, YOxFy film minimizes the shift of the initial etching rate in SNC partition etch process.

Author Bio:

ByeongSoo.Kang is currently serving as the Storage Node Contact(SNC) Engineer at SK Hynix. He is responsible for leading SNC Process dedicated to the yield improvement and increased productivity.

Ju An, STSM, IBM

Paper Title:

Enhancing Generative AI with 3D DRAM and Advanced Memory Architectures

Paper Abstract:

This paper explores the evolving landscape of memory architectures to meet the growing demands of Generative AI applications. With the increasing complexity of AI models and the need for high-capacity memory solutions, there is a pressing demand to efficiently load model parameters from memory to local caches or registers. To address this challenge, the adoption of a 3D stackable DRAM approach is deemed inevitable. The paper focuses on various technical approaches driving the memory industry towards enhanced memory capacity. These include innovative technologies such as High Bandwidth Memory (HBM) with Through-Silicon Via (TSV), Cell Over Peripheral (COP) DRAM architecture, and the pioneering 4F2 architecture. By discussing these advancements, the paper sheds light on the promising future of memory architectures in accelerating Generative AI applications.

Author Bio:

Ju Jin serves as a Senior Technical Staff Member at IBM's Infrastructure Supply Chain Organization, drawing upon more than twenty years of experience in the semiconductor industry. Her expertise lies in silicon fabrication processes and process integration, areas critical to her leadership in advancing the main memory system for IBM's Power and z Systems. She holds an MS/Ph.D. in Chemical Engineering from MIT, solidifying her academic foundation and enhancing her contributions to the field.

Paper Session Description:

In this session, we delve into the realm of enhancing Generative AI with cutting-edge memory architectures. Faced with the ever-increasing demands of AI applications, the shift towards 3D DRAM technology is deemed essential. We will discuss technical innovations such as HBM with TSV, COP DRAM architecture, and the groundbreaking 4F2 architecture, and the future for memory architectures in bolstering Generative AI applications. We will also examine challenges in DRAM technology and solutions to combat vulnerabilities in DRAM chips, ensuring optimal performance without incurring unnecessary overhead.

Open FARP-101-1: FDP and ZNS

Ballroom D, Floor 1

Track: Flash Architectures and Provisioning

Organizer + Moderator:

Brian Berg, President, Berg Software Design

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley Section, Director and past Chair of the Consultants Network of Silicon Valley, Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for Outstanding Service to the Consulting and Electrical Engineering profession, and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Paper Presenters:

Mariusz Barczak, Principal Engineer - Storage Software Architect, Solidigm

Paper Title:

Cloud Storage Acceleration Layer: Leveraging Gen5 FDP NVMe Technologies

Paper Abstract:

Cloud Storage Acceleration Layer (CSAL) is a sophisticated software solution designed to provide a high-density and high-performance local disks for cloud storage, thereby reducing user costs associated with storage infrastructure. The forthcoming generation of CSAL is positioned to leverage emerging NVMe technologies, including NVMe Gen5 devices and Flexible Data Placement (FDP), to further drive down expenses. In the upcoming iteration of CSAL, TLC Gen5 NVMe devices are proposed as cache devices, offering a cost-effective alternative to traditional Storage Class Memory (SCM). Additionally, the integration of FDP technology enables CSAL to optimize both cache and backend capacity storage, effectively segregating user data streams between these components. This strategic segregation minimizes the system's WAF, resulting in enhanced overall efficiency. In summary, CSAL represents a pioneering approach to leveraging forthcoming NVMe technologies for the development of a high-performance, cost-effective storage solution. This talk will explore the integration of these technologies within CSAL, highlighting their potential to revolutionize cloud storage infrastructure.

Author Bio:

Mariusz is a Principal Engineer in Solidigm. His storage software and storage solutions experience is over 12 years. His work area is finding innovations for storage software. In particular caching solutions, software defined storage, virtualization, and storage analytics. This is confirmed by numerous patents and open source activity. His recent work is focused on leading the team of Cloud Storage Acceleration Layer (CSAL) which delivers mixed media solutions combining Solidigm SLC with other storage components like Soldigim QLC SSD drives, to deliver efficient and durable storage.

Jonmichael Hands, Sr Director Strategic Planning, Fadu

Paper Title:

FDP Performance in VMs with Multiple NVMe Namespaces: Case Studies

Paper Abstract:

Hyperscalers are looking to improve flash efficiency, workload performance, and TCO. Cloud-native workloads are dominant, and larger SSDs now host many different applications, virtual machines, and containers. Flexible Data Placement (FDP) allows multiple applications to run on the same SSD while optimizing performance and endurance by intelligently placing like-data together to improve garbage collection efficiency. FDP drives are fully backwards compatible, so end-users can mix legacy software applications and new FDP enabled applications on the same drives across a cluster or fleet of drives. We will explore which applications can benefit from FDP with proof points and case studies from hyperscale database, caching, multiple namespaces and VMs. We will look at what application benefits can be achieved without any custom FDP-aware development.

Author Bio:

Jonmichael (JM) is a storage market expert, blockchain supporter, and sustainability leader. Jonmichael spent ten years at Intel in the Non-Volatile Memory Solutions group working on product line management, strategic planning, and technical marketing for the Intel data center SSDs. In addition, he served as the chair for NVM Express (NVMe) marketing, co-chair of the SNIA (Storage Networking Industry Association) SSD special interest group, and is active in Open Compute Project storage and sustainability projects. He was VP of Storage at Chia Network and remains an advisor. Jonmichael is the treasurer and secretary of the Circular Drive Initiative, 501(c)(6) non-profit, promoting the secure reuse of drives and circular business models for the storage industry. Jonmichael started his storage career at Sun Microsystems designing storage arrays (JBODs) and holds an electrical engineering degree from the Colorado School of Mines.

William Cheng, Director, Enterprise Marketing, Silicon Motion

Paper Title:

Flexible Data Placement (FDP) Benefits in QLC Applications: A Case Study

Paper Abstract:

1. Demand for QLC adoption in the Enterprise storage market 2. Challenge of using QLC NAND 3. Introduction of Flexible Data Placement (FDP) Technology 4. An example of how FDP is used in a high-capacity QLC NAND application 5. Analysis to show the benefits of using FDP in QLC application

Author Bio:

William Cheng is Director of Marketing at Silicon Motion. He leads a focused team in defining and promoting Enterprise controllers and development platforms that accelerate High Performance, Data Center SSD development. William has over 25 years in developing and marketing innovative storage products and solutions for the enterprise market. He has held various engineering and marketing positions at Western Digital, Microchip, Toshiba, and Intel. He earned a BSEE and MSEE at Purdue University.

Matias Bjorling, Distinguished Engineer and Country Manager, R&D Engineering, Western Digital

Paper Title:

Zoned Storage: Past, Present, and Future

Paper Abstract:

Zoned storage is now widely available across various types of storage devices, such as host-managed SMR HDDs (ATA/SCSI), SSDs with Zoned Namespace support (NVMe), and embedded devices (Zoned UFS). It is being deployed from hyperscaler data centers to mobile phones, and is proving to be an effective way to reduce TCO and environmental impact on CO2 while improving overall system performance. Over the past decade, a standard software stack has been developed to support these devices, providing a robust and scalable implementation to support the broad ecosystem. This software stack now has general support across multiple file systems, such as f2fs, btrfs, and Ceph, and it allows zoned storage device benefits to be used without any software changes. This presentation will discuss zoned storage's past, present, and future. We will explore the forthcoming scalability benefits that support zoned storage, as well as recent advancements in XFS that aim to clear the remaining storage stack obstacles.

Author Bio:

Matias Bjorling is currently serving as a Distinguished Engineer at Western Digital, where he leads the Emerging System Architectures R&D group. His areas of expertise include hardware/software co-design, emerging memory and storage architectures, and industry-wide ecosystem enablement through standardization and software development. Matias has played a key role in co-chairing the NVMe Zoned Namespace Command Set specification and is leading Western Digital's efforts towards ecosystem enablement. Hans Holmberg is a senior research scientist at Western Digital. He is the author of ZenFS and a driving force behind zoned storage, and an active contributor to the Linux storage ecosystem.

Rory Bolt, Principal Architect, KIOXIA

Paper Title:

Flexible Data Placement (FDP): What Every Storage Architect Should Know!

Paper Abstract:

FDP is a powerful new standard that provides unprecedented control to application writers and storage system architects on how their data will be organized within a Solid State Disk (SSD). The primary benefit of the new functionality provided by FDP is the ability to reduce Write Amplification (WA), which affects device lifespan and performance. However, many factors about how SSDs work, how data is written, and how operating systems support FDP can affect the level of WA improvement that can be achieved. This presentation will provide (1) a brief overview of FDP functionality, (2) how required functionality within an SSD is affected by FDP, (3) what applications can do to maximize the benefits of FDP, (4) how FDP configurations can affect the solutions costs of FDP, (5) how the Linux operating system interacts with FDP, (6) the implications for applications and storage systems, and (7) aspects of utilizing FDP that can affect the results that your applications and storage systems will achieve.

Author Bio:

Rory joined KIOXIA America in 2017. He has founded, built teams, and delivered product at four storage startups which were acquired. Rory has more than twenty-five years of experience in data storage systems, data protection systems, and high performance computing with tenures as VP software Engineering at Samsung, Technical Director/CTO counsel at NetApp, CTO counsel at EMC, Vice President, Chief Storage Architect, and Distinguished Fellow at Quantum. Rory has been granted over 12 storage related patents and has several pending.

Paper Session Description:

The demand for QLC adoption in the Enterprise storage market continues to grow, but the challenge of using QLC NAND has been a hindrance. However, the introduction of Flexible Data Placement (FDP) Technology is changing the game. FDP is being utilized in high-capacity QLC NAND applications to optimize data placement, improving performance and reducing costs. The benefits of using FDP in QLC applications are evident, as seen in increased efficiency and lifespan of devices. In a similar manner, Cloud Storage Acceleration Layer (CSAL) is leveraging Gen5 FDP NVMe Technologies to provide a high-density and high-performance local disks for cloud storage, reducing user costs and driving down expenses. Furthermore, FDP is a powerful new standard that every storage architect should be aware of, allowing for unprecedented control over data organization within SSDs. By reducing Write Amplification, FDP enhances device performance and lifespan. Finally, FDP performance in VMs with multiple NVMe namespaces has been proven through case studies, showcasing the benefits for hyperscalers and cloud-native workloads. Zoned storage, on the other hand, has become widely available across various storage devices, proving to be an effective way to reduce TCO and improve system performance. The past, present, and future of zoned storage will be discussed, highlighting the scalability benefits and advancements in software support.

Open INVT-101-1: Invited Talk with Andrew Tomlin

Ballroom E, Floor 1

Track: Invited Talks

Organizer + Chairperson:

Leah Schoeb, Sr. Developer Relations Manager, AMD

Leah Schoeb is a Sr Developer Relations Manager in AMD's platform architecture team, where she engages with solid state storage vendors on storage technology futures. She has over 25 years of experience in the computer industry, and was previously Acting Director of Reference Architecture at Intel where she led a team of segment managers and architects managing cross functional teams for flash- and NVMe-based data solutions. Leah has held management and engineering positions at VMware, Dell, and Sun Microsystems, and was also a Senior Partner at the analyst firm Evaluator Group, where she focused on storage, virtualization, and cloud infrastructure. Leah has ten technical publications, and has presented at many technical conferences. Her MBA us from the Univ. of Phoenix, and heer BSEE is from the Univ. of Maryland, College Park.

Paper Presenters:

Andrew Tomlin, CEO, QiStor

Paper Title:

Hardware-Accelerated Key-Value Databases as a Service

Paper Abstract:

The advancements in storage acceleration technology have not kept pace with other technological domains, such as AI. Key-Value databases have emerged as the fastest-growing database technology, crucial for powering webscale applications and services. In this presentation, we delve into an NVMe Key-Value solution employing FPGAs within the data center, and its potential benefits for customers. It will offer insights into the workings of Key-Value databases with traditional flash devices, and will highlight how the device-level Key-Value interface revolutionizes the landscape by impacting both cost and performance. It will also explore the hurdles encountered in developing this technology, and will propose solutions that can be extrapolated to other hardware projects.

Author Bio:

Andy Tomlin is Founder, CEO and Principal Architect at QiStor, a startup developing a hardware-accelerated, flash-based, Key-Value-as-a-Service solution for data centers. He is a 30-year industry veteran with extensive experience in flash management and controller architecture, and has delivered many flash-based products to both the client and enterprise spaces. Andy has led multiple leading-edge controller and firmware development projects while holding executive and VP Engineering positions at multiple flash and controller vendors including SanDisk, SandForce, WD, Samsung, and KIOXIA. He has presented on these topics numerous times over the years at Flash Memory Summit, and he holds over 60 patents in these areas.

Paper Session Description:

In this Invited Talk, Andrew Tomlin, founder of QiStor, will discuss how advancements in storage acceleration technology have not kept pace with other technological domains, such as AI. Key-Value databases have emerged as the fastest-growing database technology, crucial for powering webscale applications and services. He will examine an NVMe Key-Value solution employing FPGAs within the data center, and its potential benefits for customers, and will offer insights into the workings of Key-Value databases with traditional flash devices, and how the device-level Key-Value interface revolutionizes the landscape by impacting both cost and performance. He will also explore the hurdles encountered in developing this technology, and will propose solutions that can be extrapolated to other hardware projects.

Open SPOS-101-1: Boost Memory Capacity & Performance For Modern Workloads with CXL

Ballroom A, Floor 1

Track: Sponsored Sessions

Sponsor:

CXL Consortium

Organizer + Moderator:

Kurtis Bowman, Director, Server System Performance, AMD

Kurtis Bowman is the Director of Strategy and Architecture at AMD. His focus is to bring innovations to life to maximize the performance of cloud and enterprise workloads. He has been a member of the CXL Consortium since its initial formation and previously served as a Board member of the Consortium. He is the Marketing Working Group Co-Chair and is an active member of the CXL Events Task Force and CXL 3.0 NDA Keynote Presentation creation team. Kurtis represented multiple consortia at industry events by supporting and moderating panels, briefings, and more.

Panel Members:

Su Lim, Fellow and System Architect at Micron, Micron

Su Wei is currently a Fellow and System Architect at Micron. He leads the CXL System Architecture team and drives the end-to-end product definition and technology pathfinding. Su Wei has 40+ patent so far.

Hoshik Kim, Vice President and Fellow of Memory Systems Research, SK hynix

Hoshik Kim is Vice President and Fellow of Memory Systems Research at SK hynix, where he leads various research and pathfinding activities in the area of memory systems and solution architecture. His current research interests focus on next-generation memory systems architecture and software solution in various systems and application domains, which include Custom HBM, CXL memory expansion, memory disaggregation, computational memory and storage solutions for data centers at scale. Prior to joining SK hynix, he worked for Intel Corporation and LG Electronics, where he gained broad experiences in architecture, design, verification and electronic design automation (EDA) for microprocessors, system-on-chips (SoC) and intellectual properties (IP).

Chris Petersen, Fellow, Technology and Ecosystems, Astera Labs

Chris Petersen is a Fellow of Platforms and Ecosystems at Astera Labs focused on driving the company’s technology and product roadmap, and its continued close collaboration with top hyperscaler customers and ecosystem partners. His background includes over 20 years as a data center and server design architect with broad experience in developing and integrating CPUs, memory, AI and video accelerators, networking, and storage. Previously, he spearheaded hardware technology and roadmaps as a Hardware Systems Technologist at Meta for over a decade, and represented the company as a board member for the CXL Consortium, JEDEC, and NVM Express, Inc.

Kapil Sethi, Director, New Business Planning Team, Samsung Seminconductor Inc

Kapil is currently Director in the New Business Planning team at Samsung Semiconductor where he leads technical product planning for Samsung’s CXL® technology based products. He has been at Samsung Semiconductor for more than 3 years. Previously, Kapil has worked as Product Manager leading multi-million dollar product lines.

Panel Session Description:

Compute Express Link (CXL) is a cache-coherent interface that enables memory expansion and heterogeneous memory for disaggregated systems. CXL technology helps reduce storage latency, boost system performance and efficiency, and break through the limitations of current memory interface technology. This panel will share data points from CXL technology implementations to show how CXL meets the memory capacity and bandwidth needs for AI, HPC, and in-memory database applications. Attendees will gain insights into the solutions that are readily available within the market.

Open SSDT-101-1: Flash & Memory Controller Technologies for AI

Ballroom F, Floor 1

Track: SSD Technology

Organizer + Chairperson:

Erich Haratsch, Senior Director Architecture, Marvell

Erich Haratsch is Senior Director Architecture at Marvell, where he leads the architecture definition for Bravera SSD controllers and other memory-based products. Prior to joining Marvell, he worked at Seagate and LSI, where he worked on Nytro and SandForce branded SSD controllers. Earlier in his career, he developed signal processing and error correction technologies for multiple generations of HDD controllers at LSI and Agere Systems. He started his career at AT&T and Lucent Bell Labs, where he worked on Gigabit Ethernet over copper, optical communications and the MPEG-4 video standard. He is the author of over 40 peer-reviewed journal and conference papers, and holds more than 200 U.S. patents. He also is a Senior Member of IEEE, and earned his MS and PhD degrees from the Technical University of Munich (Germany).

Paper Presenters:

Tao Lu, Research Manager, DapuStor

Paper Title:

CXL2P: Addressing DRAM Shortages in Large-Capacity SSDs and Reducing Cost

Paper Abstract:

The traditional best practice of utilizing 4KB page granularity for SSD address translation is being challenged due to shortages in onboard DRAM, especially as enterprise-level SSDs approach 100TB and PB-level SSDs emerge. The limited DRAM cannot accommodate the entire page mapping table. Existing solutions propose larger mapping granularity (e.g., 16KB) and learned indexes to reduce memory footprint, but these approaches suffer from suboptimal random write performance and limited applicability. The advent of the CXL protocol presents new opportunities for large capacity SSDs to retain optimal 4KB page mapping granularity. We have investigated the feasibility and advantages of leveraging CXL.cache to supplement SSD memory for page indexing and introduced an innovative CXL-based tiered memory and index architecture, cxL2P. This architecture is designed to fundamentally address the onboard DRAM shortage issue and support fine-grained page mapping for large-capacity SSDs without compromising performance.

Author Bio:

Dr. Tao Lu is a seasoned researcher in the storage domain. Dr. Lu currently serving as the R&D Manager at DapuStor, a leading enterprise specializing in SSD controller chip design and customized intelligent SSD solutions. With expertise in SSDs and data compression, Dr. Lu has been instrumental in driving storage innovation at DapuStor. As the technical lead, he spearheaded the development and mass production of the company's first-generation computational storage drives.

Licheng Xue, ASIC digital design manager, Starblaze

Paper Title:

Dynamic data loading from Flash to DRAM for LLM inference

Paper Abstract:

Large language models (LLMs) cost too much DRAM to store all the model parameters for inference. To perform inference using the Llama2-13B model, you’ll need to store approximately 26GB model parameters in DRAM, which is challenging to provide, especially for edge LLM inference platforms, such as AI PCs and AI phones. While DRAM cannot provide sufficient capacity to store parameters, Flash can offer it but cannot provide the required read latency and throughput. We propose to keep part of model parameters in DRAM and all model parameters in Flash devices, dynamically exchange the new parameters with the old useless ones during LLM inference. Two key issues are addressed: “which parameters should be loaded?” and “How to improve the loading latency and throughput?”. Our methods enable efficient inference for devices with insufficient DRAM.

Author Bio:

Obtained doctoral degree from Beijing Institute of Technology. Occupied in Starblaze, specializing in the architecture design of SSD controllers and AI chips. Participated in the tape-out process of four SSD controller controllers. Presenter of FMS19.

Vasanthi Jagatha, Senior Manager, Product Marketing, Marvell

Paper Title:

Flash Controllers for the AI Era

Paper Abstract:

Gen AI has a wide range of applications. Depending on the application, data management, workload for the memory / storage varies significantly. Every stage (Data Ingestion, Training, Inference, RAG, etc.) has nuanced flash SSD storage requirements needing the right mix of SSD controller features like high random performance and host management capability. In addition to solving storage challenges, the right SSD controller can innovatively alleviate the significant memory constraints placed by the ever-increasing volume of raw and ephemeral data that is generated by Gen AI applications. In this presentation, we will walk through the storage and memory needs of the Gen AI data pipeline and craft the optimal storage controller for Gen AI workloads.

Author Bio:

Vasanthi Jagatha is Senior Manager of Product Marketing, Flash SSD team in the Custom, Compute & Storage Group at Marvell. In this role, Vasanthi is responsible for custom flash controller initiatives. Vasanthi has also managed cloud and enterprise flash controller product lines. Vasanthi joined Marvell from Intel where she held product management, business development and research engineering roles for Storage and FPGA products. Vasanthi earned a master’s degree in Electrical Engineering and a bachelor’s degree in Computer Systems Engineering from Arizona State University.

Yuyang Sun, Product Marketing Engineer, Solidigm

Paper Title:

Flash Storage in the AI Era

Paper Abstract:

In recent years, the advent of artificial intelligence (AI) has ushered in a transformative era in computing, where data processing speed and efficiency have become paramount. The existing datacenter infrastructure and edge devices have encountered challenges in keeping up with the escalating demands imposed by AI applications. Rapid demand growth in the fields such as compute, memory, and networking has revealed the growth potentials and underscored the urgency of addressing the limitations to better accommodate the new requirements of the new AI era. As AI technology continues to advance, it is important to understand how flash storage is likely to evolve as part of the AI hardware infrastructure. This presentation aims to comprehensively examine the hardware infrastructure requirements for AI with a focus on storage. We will evaluate the existing technologies and identify those essential to fortify support for the ongoing AI revolution. Furthermore, our discussion will delve into the pivotal role that flash storage can play in shaping a more efficient and potent future for AI by optimizing data-intensive tasks and enhancing overall system performance and power efficiency.

Author Bio:

Yuyang Sun, Senior Manager of Product Marketing at Solidigm, has over a decade of experience in SSD storage design, business planning, marketing, and strategy. Her day-to-day interactions with major industry players have allowed her to gain invaluable insights into the world of data center storage solutions, and she has been actively involved in managing data center QLC SSD products since their inception. Yuyang holds a Bachelor's and Master's degree in Electrical Engineering from University of British Columbia and an MBA from the Wharton School of Business. In her leisure time, she enjoys playing badminton and even co-founded a local badminton club with hundreds of active members.

Paper Session Description:

In the ever-evolving landscape of artificial intelligence (AI), the demand for faster and more efficient data processing is at an all-time high. Flash storage technology has emerged as a pivotal player in the AI hardware infrastructure, offering the potential to optimize data-intensive tasks and enhance system performance. However, challenges such as dynamic data loading from Flash to DRAM for LLM inference and finding the right flash controllers for Gen AI applications have arisen. Additionally, the innovative CXL2P protocol has been introduced to address DRAM shortages in large-capacity SSDs and reduce costs, ensuring optimal performance without compromising efficiency. Join us as we explore the exciting possibilities of flash storage in the AI era.

Open UCIC-101-1: UCIe Solution Technology Innovations NEW

Ballroom G, Floor 1

Track: UCIe and Chiplets

Organizer:

Brian Rea, Technology Initiative and Ecosystem Enablement Manager, Intel

Brian Rea has served as a marketing work group co-chair of UCIe since 2022 and is a Technology Initiative and Ecosystem Enablement Manager at Intel. Rea holds a MBA from the University of Washington and a B.S. in Electrical Engineering from the University of Texas at Austin.

Paper Presenters:

David Kulansky, Director of Product Marketing, Alphawave Semi

Paper Title:

High Performance Disaggregated Systems through UCIe Interconnects and Chiplets

Paper Abstract:

The rapid advancement of semiconductor fabrication processes and the increasing demand for high-performance computing have necessitated the development of disaggregated systems, which offer enhanced flexibility, scalability, and resource utilization. By leveraging UCIe Die-to-Die interconnects, these systems enable efficient communication between different components leading to improved performance and reduced power consumption. In this session, we will delve into the core principles of UCIe, including their low latency, low power consumption, and interoperability. We will discuss how UCIe enables a unified interconnect ecosystem for IO, memory, and accelerator based chiplets which can revolutionize diverse domains such as data centers, edge computing, artificial intelligence, autonomous systems, and high-performance computing. We will also touch on how chiplets enable both common and new connectivity use cases like IO/memory disaggregation and 2.5D co-packaged optics.

Author Bio:

Dave Kulansky is Director of Product Marketing at Alphawave Semi focused on High-Speed IO. Dave has 20+ years of semiconductor experience, focused on mastering best fit solutions to streamline new product development. Before joining Alphawave, Dave held positions in AMS, RF & SerDes design, but he most recently focused on PCIe & Ethernet solutions.

Randy White, Memory Solutions Program Manager, Keysight

Paper Title:

UCIe and how to enable an open chiplet ecosystem

Paper Abstract:

The demand for high performance, power efficient computing solutions to address next-generation workloads has caused the industry to shift from monolithic designs to Systems in Package (SiP). While modular architectures allow design teams to re-use individual components and replace only those that have the largest impact to the end product, the standardization of die-to-die interfaces is crucial to achieve it at scale. Universal Chiplet Interconnect Expressâ¢, an emerging die to die interconnect standard, will revolutionize the industry due to its compliance and intercompatibility program which enable a truly open chiplet ecosystem. In order to realize that vision, the right set of test and validation tools pre- and post-packaging must be available, such that designers are ensured the interconnected chiplets will function as desired. This presentation will explore the test and validation challenges involved with die-to-die interconnects, and discuss some proposals to overcome these challenges.

Author Bio:

Randy White is the Memory Solutions Program Manager for Keysight Technologies. He is focused on test methodologies for emerging memory technologies in server, mobile and embedded applications. Randy has spent the last 20 years investigating signal integrity measurement techniques including de-embedding algorithms, measurement/model correlation and high speed measurements for real-time & sampling oscilloscopes as well as BERTs & AWGs. He has participated on many standards committees including UCIe, PCI-SIG, USB-IF, SATA-IO, and JEDEC to help define new test methodologies and is currently the chair of the JEDEC JC40.5 Logic Validation subcommittee. He graduated with a BSEE from Oregon State University.

Prashant Dixit, Senior Engineering Manager, Siemens EDA

Paper Title:

Verification Challenges and Solutions for Multi-Die Systems

Paper Abstract:

Multi-die systems accelerate the scaling of system functionality and facilitate the creation of new product variants but with new challenges in functional verification. Verifying a UCIe design includes sideband training, arbitration, lane repair and reversal, validate various requests and responses, scoreboarding across power cycles and reset types and all components in the dies from a system-level perspective. We will discuss the verification solutions for chiplet designs - full stack, d2d adapter, logphy, from planning to closure. Access to various flit types, sideband packet types, LTSM states, and other data structures will be done using UVM features like callbacks and analysis components, common APIs for PCIe, CXL, and streaming modes make the solution highly adaptable for high-level stimulus. We will see strategies to make the die-level testbench reusable and synchronized to ensure that data arrives with the expected throughput and latency with a case study that demonstrates how these techniques, along with a flexible and open architecture, exhaustive compliance test suite and efficient debug mechanism, help UCIe customers verify designs and achieve less time to market.

Author Bio:

Prashant Dixit is currently working on the development of verification solutions for UCIe-based designs at Siemens EDA. With a strong background in the storage domain, he also manages the Storage Verification IPs team, focusing on the development and testing of NVMe and NVMe over Fabrics testing solutions. Prior to his role at Siemens EDA, Prashant gained valuable experience at Samsung, where he contributed in the design and verification of IPs and SoC of networking and storage domains. Prashant holds a Master of Engineering degree in Microelectronics from BITS Pilani, which he completed in 2006. He also earned a Bachelor of Technology in Electronics and Communication from Uttar Pradesh Technical University in 2004.

Nilesh Shah, VP, Business Development, ZeroPoint Technologies

Paper Title:

Chiplet-Based Compressed LLC Cache & Memory Expansion

Paper Abstract:

HBM, Non-volatile, DDR memory chiplets, and LLC cache chiplets play a pivotal role in overcoming memory and SRAM scaling challenges in data centers and smart devices. However, the Total Cost of Ownership (TCO) associated with chiplet-based memory and cache presents a hurdle for hyperscale deployment. Introducing a cutting-edge hardware-accelerated chiplet IP that achieves real-time memory compression (2-4X) at CACHE LINE granularity, with sub 10ns latency. This IP seamlessly integrates with SRAM (xRAM) LLC, Nonvolatile, and UCIe/CXL-connected memory chiplets, enhancing TCO cost-effectiveness ($$/GB) while preserving performance. When paired with a high-speed coherent mesh network and protocol within an SoC, substantial return-on-investment is realized. This configuration offers unmatched flexibility and efficiency in resource management. The presentation elucidates the architectural components that seamlessly integrate with existing chiplet ecosystem elements. The overarching goal is to present viable options for mitigating adoption barriers associated with memory and LLC cache chiplets, particularly in large memory applications across Cloud, Hyperscale, and Automotive segments.

Author Bio:

Nilesh currently leads Business Development at ZeroPoint Technologies where he is responsible for engaging Hyperscalers, Memory Module , controller and processor/accelerator manufacturers to develop Data Center and Smart Device solutions . He's an active member of the CXL Consortium, JEDEC, SNIA, represents the company at OCP. Previously, Nilesh developed Data Center SSD products and Computational Storage initiatives at Intel and holds several patents in this area. Nilesh runs several Meet Up Communities with upwards of 5000 active members and serves as an Advisor to several other companies in the Emerging Memory Technology IP and SoC space.

Paper Session Description:

In this session, we will first examine how chiplet-based dompressed LLC cache and memory expansion utilizes cutting-edge hardware-accelerated chiplet IP to overcome memory and SRAM scaling challenges in data centers and smart devices. This IP achieves real-time memory compression with sub 10ns latency, seamlessly integrating with various memory chiplets while enhancing cost-effectiveness and preserving performance. We will then discuss how to address the challenges in functional verification for UCIe designs, offering strategies for die-level testbench reuse and synchronization. We will then explore how UCIe enables efficient communication between components for improved performance and reduced power consumption. UCIe and how to enable an open chiplet ecosystem discuss the standardization of die-to-die interfaces and the importance of test and validation tools for an interconnected chiplet ecosystem.

09:45 AM to 10:50 AM

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PRO AIML-102-1: Storage for AI: Applications

Ballroom B, Floor 1

Track: AI and ML Applications

Organizer + Chairperson:

David McIntyre, Director Product Planning, Samsung Electronics

Paper Presenters:

Swapna Yasarapu, Azure Storage Architecture, Microsoft

Paper Title:

Storage Media & Architecture for AI Workloads

Paper Abstract:

AI workloads bring uniqueness associated with how they generate and store data while leveraging existing storage infrastructure. Lifecycle of Storage in AI involves local caching and persistent storage, while the data is acquired, processed, modeled, trained, refined, and stored. AI workloads are generating some interesting storage patterns, that could influence the direction of future Storage Media and Architectures, to make them more AI workload specific, which will be the focus of this talk.

Author Bio:

Swapna Yasarapu has over 25yrs in the storage industry spanning responsibilities ranging from ASIC design, systems engineering, product management and P&L management. Swapna has been a key player in the flash industry - in the definition and productization of new flash form factors (SFF8639, EDSFF) as well as her multi-year tenure as NVMe board member contributing to bringing NVMe as the mainstream interface for the industry.

John Mazzie, Senior Solutions Engineer, Micron Technology

Paper Title:

Analyzing workloads using storage as memory replacement for large model training

Paper Abstract:

Dataset training sizes continue to grow, and larger models may not fit into system memory. In this situation, data loaders need to access models located on flash storage. One such method is a memory mapped file stored on SSDs, though this process can slow training down significantly. New methods that take advantage of the parallelism provided by modern NVMe devices, can make a huge difference in training these large models. We will dive into the analysis of workloads for large training models, showing how they take advantage of modern devices and what kinds of workloads that these devices are experiencing.

Author Bio:

John is a Member of Technical Staff, Systems Performance Engineer at Micron Technology, working on application tracing and data analysis for SSD development since 2016. Previously, he worked in the storage group at Dell Technologies and has a M.S. in Electrical Engineering from West Virginia University.

Ace Stryker, Product Marketing Lead, Solidigm

Paper Title:

AI Data Pipeline

Paper Abstract:

NVIDIA GPUDirect® Storage (GDS) enables a path for direct memory access (DMA) transfers between the GPU and storage device in a system, allowing data to be moved without any intermediate copies in the CPUs memory. This leads to increased system bandwidth while decreasing latency and CPU utilization. The proposed presentation will share the configuration that was used for the testing (this GDS configuration is also supported on the DGX A100 system, the world's first 5-petaFLOP AI system built with a new generation of GPUs). We will share results of our testing which shows a 2.2x increase in GPU operations, Throughput and Latency in this configuration compared to when CPU is involved in the data transfer from storage device. The data also will show that CPU utilization is lower with GDS configuration since a lot of the transfer overhead is handled by the GPU/SSD.

Author Bio:

I am currently an Eco-System engineering manger at Solidigm. In my position I am responsible for validating our Solid State Drives with eco-system partners that provide next generation enterprise systems (x86 and arm based CPU and GPU vendors) as well as system components (retimers, redrivers, RAID card and Switch vendors). I have spent >25 years at Intel working in various capacities including component design engineer, system validation manager and FW engineering manager. After transitioning to Solidigm I have started leading the eco-system validation team, we are responsible for all certification and eco-system compatibility validation activities at Solidigm

Paper Session Description:

This session examines a variety of approaches and applications used in storage for artificial intelligence, including direct memory access transfers between the GPU and storage device, eliminating the need for intermediate copies in CPU memory. We will also discuss RAG optimized SSD solutions for the Generative AI era, and explore how storage media and architecture are evolving to cater to AI workloads. Join us in analyzing workloads using storage as memory replacement for large model training.

Open BMKT-102-1: Memory Markets

GAMR 1 (Great America Meeting Room 1), Floor 2

Track: Business Strategies and Memory Markets

Organizer + Chairperson:

Jean Bozman, President, Cloud Architects Advisors

Paper Presenters:

James Pan, Senior Principal Engineer Project Manager, Northrop Grumman

Paper Title:

Techniques to Fabricate Ultra-Fast Sub-1nm Photonic SRAMs

Paper Abstract:

Traditionally, CMOS is not considered a light emitting device. Photonic CMOS – which includes a tunnel LED or threshold-less ultra-low resistance laser in the drain region, and photon sensors (avalanche photo diode) in the drain / well regions as one integral transistor – is a light emitting device, similar to laser and LED. CMOS can also be a microwave generating device. In this paper, we will look into ways of how to design a CMOS inverter, and ultra-highspeed SRAM (Static Random Access Memory), using the Photonic Millimeter Wave CMOS technology, for Optical Computing. Inverter and SRAM (in cache memories) are critical components in ULSI processors or RF ASICs. The Photonic CMOS Inverter and Photonic SRAM are 100% compatible to existing CMOS manufacturing and circuit designs. Nonlinear optical materials, as well as optical processes, such as optical filtering and polarization, can be used to further improve the Photonic SRAM speeds.

Author Bio:

James Pan is a Senior Principal Engineer and Project Manager in Northrop Grumman Corporation. He received his Ph.D. from Purdue University, MSEE from University of Texas at Austin, and BSEE from National Taiwan University. He worked for IBM (T. J. Watson Lab. and E. Fishkill), AMD, Micron Technology, Atmel Corporation, Fairchild Semiconductor, and Semicoa Corporation. Dr. Pan started American Enterprise and License Company in 2009.

Ronen Hyatt, Founder and CEO, Unifabrix

Paper Title:

Breaking the Memory Wall - here and now!

Paper Abstract:

Do you have a memory-bound cluster? Would you like to overcome the Memory Wall today? this presentation will show the technologies implemented in current and future Memory Pool technologies including real use cases, performance numbers, and TCO model. After this presentation, you will know the Pros and Cons of Memory Pooling.

Author Bio:

Ronen is an expert in system architectures with over 25 years of experience leading and delivering silicon designs running Compute acceleration cores, DSAs, CXL and Ethernet connectivity, RDMA networking and programmable switches. Ronen has served as CTO and lead architect in multiple leading silicon companies, including Intel, where he co-founded the IPU (Infrastructure Processing Unit) and initiated the programmable Ethernet connectivity development. Ronen is Founder and CEO at UnifabriX, a system and silicon startup targeting the Memory Wall with CXL-based Software-Defined Memory Pools and CXL Fabrics. Ronen holds more than 40 patents (some pending), an MSc and BSc in Computer Engineering from Technion Institute of Technology, and MA in Law from Bar-Ilan University.

John Lorenz, Senior Analyst, Yole Group

Paper Title:

Memory market recovery and focus on datacenter and CXL demand

Paper Abstract:

The DRAM and NAND markets are rebounding from their worse levels of profitability in over a decade. Where are the green shoots for the ongoing recovery? Which aspects of the forecast contain upside and downside risk? Can we expect to see another cyclical downturn in the coming years? As a general market overview, this presentation will discuss Yole's perspective on memory supply and demand, pricing and margins, and memory industry capex through 2029. As datacenter is the most important piece of DRAM demand, there will be an additional examination of how the implementation of CXL can simultaneously boost the overall DRAM demand while reducing the cost per accessible bit for datacenter architects.

Author Bio:

John Lorenz is a Sr Technology and Market Analyst at Yole Group, a leading analyst firm based in France. At Yole, John covers processors, accelerators, and DRAM, with keen attention to manufacturing topics and applications. He has spoken at many events, including EETimes' AI Everywhere forum and Chiplet Summit. He has also been quoted in many media outlets, including Le Figaro and the Ojo Yoshida Report. Before joining Yole Group, John was a senior manager in strategic finance for Micron Technology, where he analyzed technology investments and forecasted memory industry trends. He earned a BSME from the University of Illinois at Urbana-Champaign.

Jim Handy, General Director, Objective Analysis

Paper Title:

Annual Memory Update: Market Outlook in a Time of Great Change

Paper Abstract:

2024 opened with strong growth, largely fueled by enormous adoption of heavyweight AI systems. What changes does this bring to semiconductor consumption? Is the year’s early growth sustainable? What is the impact of the US/China trade war, high interest rates & inflation, and wars in Ukraine and Israel/Gaza? What changes will come from new technologies like CXL, HBM, and chiplets? In this session respected semiconductor industry analyst Jim Handy of Objective Analysis will show how all of these factors will combine to create a changing market, and will provide attendees with a deep understanding of the aspects that are predictable and those that must be dealt with cautiously.

Author Bio:

Jim Handy, Objective Analysis, is a leading semiconductor analyst. After positions at Intel, National Semi, and Infineon he is respected for his tech depth, accurate forecasts, and numerous reports. See http://Objective-Analysis.com, http://TheMemoryGuy.com, and http://TheSSDguy.com.

Nilesh Shah, VP, Business Development, ZeroPoint Technologies

Paper Title:

Unveiling the dynamics of IP Licensing Economics: Memory & Storage SoC/Chiplets

Paper Abstract:

This panel/presentation explores the complex economic landscape of Intellectual Property (IP) licensing within the semiconductor industry, with a specific focus on Storage and Memory System-on-Chip (SoC) and chiplet development for hyperscale computing. The discussion covers key aspects: 1. **Market Dynamics:** Analysis of evolving trends and demands in hyperscale computing, and their impact on decision-making for IP licensing models. 2. **Leveraging IP Ecosystems:** Exploration of the role of IP ecosystems in supporting SoC and chiplet development, assessing economic viability for collaborative innovation. 3. **Cost-Benefit Analysis:** In-depth examination of economic implications related to various IP licensing structures, including upfront fees, royalties, and revenue-sharing models, considering scale and volume effects. 4. **Risk Management:** Addressing inherent risks in IP licensing, including conflicts, legal considerations, and strategic implications at different development stages. 5. **Technological Advancements:** Assessment of the influence of advanced fabrication processes and AI integration on the economics of IP licensing in SoC and chiplet development.

Author Bio:

Paper Session Description:

This session provides insight into the market outlook amidst great changes in semiconductor consumption due to factors like AI system adoption, trade wars, and new technologies. We will discuss the foreseeable impacts and challenges in the evolving memory landscape. The dynamics of IP licensing economics in memory and storage SoC/chiplets development will be explored in-depth, covering market trends, leveraging IP ecosystems, cost-benefit analysis, risk management, and technological advancements. We will aim to shed light on the complex economic landscape of IP licensing within the semiconductor industry. We will also explore the use of nonlinear optical materials and processes, and the revolution in optical computing. Additionally, the memory market recovery and focus on datacenter and CXL demand will be analyzed, highlighting the rebound of DRAM and NAND markets and the factors contributing to their recovery.

PRO COMP-102-1: CS Solution/Technology Innovations NEW

Ballroom C, Floor 1

Track: Computational Storage

Organizer:

Scott Shadley, Strategic Planner, Solidigm

Scott Shadley has spent over 25 years in the semiconductor and storage space. He has time in Production, Engineering, R&D, Customer focused roles including Marketing and Strategy. His current focus is in efforts to drive adoption of new storage technology as a Director of Strategic Planning at Solidigm. He has been a key figure in promoting SNIA as a second term Board member and leading the computational storage efforts as a co-chair of the SNIA Technical Working Group. He participates in several industry efforts like Open Compute, NVM Express and is seen as a subject matter expert in SSD technology and semiconductor design. He has and still speaks on the subject at events like the Open Compute Summit, Flash Memory Summit, SDC, and many other events, press interviews, blogs, and webinars. While at NGD Systems, Scott developed and managed the Computational Storage products and ecosystem. Scott previously managed the Product Marketing team at Micron, was the Business Line Manager for the SATA SSD portfolio, and was the Principal Technologist for the SSD and emerging memory portfolio. He launched four successful innovative SSDs for Micron and two for STEC, all of which were billion dollar programs. Scott earned a BSEE in Device Physics from Boise State University and an MBA in marketing from University of Phoenix.

Paper Presenters:

Qing Zheng, Scientist, Los Alamos National Laboratory

Qing Zheng is a Scientist in Los Alamos National Lab’s High-Performance Computing Division and a member of the Lab’s Ultrascale System Research Center at New Mexico Consortium. Qing performs I/O and storage research that guides the Lab’s future computing platform and storage infrastructure designs. Qing received his PhD in Computer Science from Carnegie Mellon University in 2021. Qing is known for his expertise in distributed filesystem metadata and large-scale data analytics. Qing’s work has been exhibited at local science museums, reported by national media, and recognized with multiple R&D 100 and Supercomputing Best Paper Awards.

Onur Mutlu, Professor of Computer Science, SAFARI Research Group at ETH Zurich

Paper Title:

Storage-Centric Computing for Genomics and Metagenomics

Paper Abstract:

Genomics and metagenomics have enabled significant advancements in many critical areas. The exponential growth of genomic data poses unprecedented challenges in genomics and metagenomic applications. These applications suffer from significant data movement overheads from the storage system. To fundamentally address these overheads, we make a case for storage-centric computing. First, we propose MetaStore, the first in-storage processing system designed to significantly reduce the data movement overhead of end-to-end metagenomics. MetaStore is enabled by our lightweight and cooperative design that orchestrates processing inside and outside storage. MetaStore outperforms the performance- and accuracy-optimized software baselines by 2.7-37.2Ã and 6.9-100.2Ã, respectively, while matching the accuracy of the accuracy-optimized tool. MetaStore achieves 1.5-5.1Ã speedup compared to the hardware baseline, while achieving significantly higher accuracy. Second, we propose GenStore, the first in-storage processing system designed for genome sequence analysis. GenStore significantly improves the read mapping performance of the software (hardware) baselines by 1.5-33.6Ã (1.5-19.2Ã).

Author Bio:

Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is also a faculty member at Carnegie Mellon University, where he previously held the Strecker Early Career Professorship. His current broader research interests are in computer architecture, systems, hardware security, and bioinformatics. A variety of techniques he, along with his group and collaborators, has invented over the years have influenced industry and have been employed in commercial microprocessors and memory/storage systems. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held various product and research positions at Intel Corporation, Advanced Micro Devices, VMware, and Google. He received the IEEE Computer Society Edward J. McCluskey Technical Achievement Award, the ACM SIGARCH Maurice Wilkes Award, the inaugural IEEE Computer Society Young Computer Architect Award, the inaugural Intel Early Career Faculty Award, US National Science Foundation CAREER Award, Carnegie Mellon University Ladd Research Award, faculty partnership awards from various companies, and a healthy number of best paper or "Top Pick" paper recognitions at various computer systems, architecture, and hardware security venues. He is an ACM Fellow "for contributions to computer architecture research, especially in memory systems", IEEE Fellow for "contributions to computer architecture research and practice", and an elected member of the Academy of Europe (Academia Europaea). His computer architecture and digital logic design course lectures and materials are freely available on YouTube, and his research group makes a wide variety of software and hardware artifacts freely available online. For more information, please see his webpage at https://people.inf.ethz.ch/omutlu/.

Woosuk Chung, Storage Software Team Lead, SK hynix

Paper Title:

Toward Open Standardized Object-Based Computational Storage for Big Data Analyti

Paper Abstract:

Open standards facilitate interoperability, community support, and vendor neutrality. Just as NFS sets the protocol for NAS and ANSI T10 defines SCSI’s Object-based Storage Device (OSD) command set, this talk pushes for standardizing object-based computational storage amid rising object storage use, the increasing bottleneck caused by excessive data movement, a lack of standardized methods for integrating data reduction functions within storage, and a shift towards NVMe as a modern replacement for the old SCSI interface. As a collaborative effort among SK hynix, Los Alamos National Laboratory, Versity, Neuroblade, and Airmettle, we envision a standardized Object-based Computational Storage (OCS) stack as an open computational storage platform for data analytics. This stack comprises a high-level Object-based Computational Storage (OCS) interface for object management and query pushdown and a low-level Object-based Computational Storage Device (OCSD) command set for device-level object storage and query processing. A typical setup would consist of a pool of gateway servers implementing the high-level interface and a pool of NVMe devices or arrays implementing the low-level interface. This talk will focus on the rationale behind such an open storage stack design, its integration with existing storage services, and its current prototype implementation along with early analysis acceleration results using real-world dataset and workflows.

Author Bio:

Woosuk Chung is currently serving as the Storage Team Leader at SK Hynix. He is responsible for leading a team dedicated to the research and development of next-generation storage systems and future enterprise SSDs for enhancing the system performance

Prashant Dixit, Senior Engineering Manager, Siemens EDA

Paper Title:

Accelerating Verification of Computational Storage Designs

Paper Abstract:

Computational Storage and Subsystem Local Memory (SLM) command sets leverages low latency, high bandwidth, efficient command handling, and direct CPU access which makes it ideal for computational storage designs. However, these features add various challenges in their functional verification. To ensure thorough verification, validation of command operations from these command sets and data transfers to and from various regions, memory score boarding across power cycles should be included. These challenges require the solution to be agile and adaptable. We will discuss the important characteristics of verification solution from planning to closure. We will see how by using common APIs, different kinds of access to commands, data structures, SLM ranges using UVM features like callbacks and analysis components will make the solution highly adaptable for various types of device-defined or vendor specific programs keeping the high-level stimulus similar. We will see a case study on how the above techniques along with exhaustive compliance test suite, and efficient debug mechanism helped our NVMe customer verify computational storage design thoroughly and achieve lesser time to market.

Author Bio:

Ujjwal is currently working on the development of verification solutions for NVMe and NVMe over Fabrics testing solutions in storage domain focusing on the Computational Storage. Ujjwal holds a Bachelor of Technology in Electronics and Communication from Guru Govind Singh Indraprastha University in 2023.

Paper Session Description:

In this session, we dive into the world of object-based computational storage for data analytics, which is revolutionizing the way data analytics systems process and transfer data. Verification of computational storage designs, crucial for ensuring the functionality and reliability of computational storage systems, uses APIs, UVM features, and efficient testing techniques to reduce time to market. Lastly, storage-centric computing for genomics and metagenomics is reshaping the field by addressing data movement overheads and improving performance in genomic applications with innovative in-storage processing system. Let's continue pushing the boundaries of computational storage for a brighter future in data analytics and genomics.

PRO CXLT-102-1: CXL Fabric Management

Ballroom E, Floor 1

Track: CXL

Organizer + Chairperson:

Anil Godbole, Xeon CXL Strategy & Marketing Manager at Intel Corporation, Intel

Anil is Xeon CXL Strategy & Marketing Manager at Intel Corporation.

Paper Presenters:

Bhushan Chitlur, Sr Principal Engineer, Datacenter & AI Group, Intel

Paper Title:

Improving SW-HW processing pipeline for storage stack/service workflows w CXL

Paper Abstract:

Storage services & workflows are adopting disaggregated storage architecture enabled by newer ethernet standards: 400/800GE. This also necessitates need for HW accelerators for operations like compression, encryption, erasure coding, deduplication etc with some usages requiring operations at storage initiator. These operations require data context to be translated from memory into storage context right at the Storage initiator (typically, CPU) before transmission over 400/800GE to the destination media block/object/file storage. The storage stack thus is a blend of protocol processing & multiple translations enforcing data segmentation using SW-based execution or through accelerator usage (e.g., TLS encrypt / decrypt, NVMe data digest, etc.). Almost always, requires multiple data movement between cpu memory domain and lookaside accelerator memory domains with PCIe link becoming the bottleneck. This paper proposes a CXL based implementation to preserve memory context of data as long as possible, chaining storage and network functions to deliver higher performance for both local & disaggregated storage accesses: block, object, file across varied storage media: volatile, ephemeral, non-volatile. The solution will enumerate CXL concepts to enhance current IO paths and show how adopting CXL dataflow (Type1 / Type2 / Type3) allows for data plane in only one memory domain with control plane straddling between cpu and accelerator memory domains. This delivers higher throughput, more IOPs per node & also reduces deployment cost by enabling solution upgrades requiring slower hardware refresh cadence.

Author Bio:

Bhushan Chitlur is a Sr Principal Engineer, Datacenter & AI Group at Intel Corporation

Grant Mackey, CTO, Jackrabbit Labs

Paper Title:

You Don't Know 'Jack': CXL Fabric Orchestration and Management Best Practices

Paper Abstract:

The CXL consortium has published a fabric management API in their latest specification which codifies how switches and devices should pass information to each other in a standardized way for configuration and management. However this API is just a set of commands, not a framework for accomplishing tasks at a system or infrastructure configuration level. To date, the CXL community, both creators and consumers, have not discussed how fabric orchestration should function for CXL. Jackrabbit Labs has written a CXL FM API compliant set of open source tools which function as a fabric management and orchestration layer for CXL devices and switches. In this presentation we introduce 'Jack,' and talk about best practices for integrating CXL fabrics into familiar platform management tools. Further, we'll demonstrate how CXL fabrics and orchestration integrate into a Kubernetes deployment.

Author Bio:

Grant Mackey, Distinguished engineer focused on datacenter enablement. Inventor/researcher of storage and HPC systems for Western Digital and Los Alamos National Labs. A published author and patent holder with nearly two decades of experience in research and development of datacenter architectures, workloads, infrastructure, and emerging technologies.

Sudhir Balasubramanian, Sr Staff Solution Architect - Oracle, VMware by Broadcom

Paper Title:

VMware Memory Vision for Real World Applications

Paper Abstract:

VMware has been on an evolving journey on memory innovations mainly first with persistent memory, then with memory tiering, and is now extending that with CXL. CXL provides an opportunity for VMware (by Broadcom) to further improve on performance, and provide further customer benefits such as TCO reduction, server consolidation, and even disaggregation, with increased capacity and bandwidth to run workloads like Mission critical databases, AI/ML and analytics. Use of accelerators increases the number of use-cases that can be supported with a larger variety of workloads with minimum configuration changes. This session aims to provide real-world application examples using memory tiering.

Author Bio:

27 + years Oracle hands on experience - Principal Oracle DBA / Architect, Oracle RAC/Data Guard Expert, Experienced in EMC SAN Technologies Principal Oracle DBA/Oracle Architect [1995 – 2011] Senior Staff Solution Architect & Global Oracle Practice Lead [2012-] - VMware / VMware by Broadcom VMware VCA – Cloud ,VMware vBCA Specialist, VMware vExpert Member of the Office of the Chief Technical Ambassador VMware (Alumni) Oracle ACE Leading Author - “Virtualizing Oracle Business Critical Databases on VMware SDDC” Recognized Speaker@ VMware Explore, Oracle Cloud World, Oracle User Groups, Quest IOUG, Dell EMC World, SNIA and Webinars Industry recognized expert in Oracle Virtualization technologies Blogs http://vracdba.com/ https://blogs.vmware.com/apps/author/sudhirbalasubramanian/ Twitter : @vracdba LinkedIn : https://www.linkedin.com/in/sudhirbalasubramanian/

Navneet Rao, Engineer, Intel

Navneet Rao is a Solutions Architect at Intel Corporation

Yong Tian, Field CTO, MemVerge

Paper Title:

The Case for CXL Memory Expansion

Paper Abstract:

With support for CXL 1.1, servers now offer a new architectural model with the capability for memory expansion through CXL Memory Add-in Cards (AICs) and E3.S memory modules. This presentation addresses the critical considerations faced by sellers and buyers regarding the cost, capacity, and performance implications of integrating mixed DIMM and CXL memory in their server environments. Yong Tian will guide the audience through an insightful exploration of the innovative memory expansion architecture options presented by CXL and its 1.1 specifications. An in-depth analysis will be presented, unveiling strategies to slash memory costs by half while concurrently elevating a single server's capacity to an impressive 32TB. The focal point of the presentation will be test results illustrating how servers equipped with mixed memory can sustain optimal application performance. This will be achieved through the utilization of automated tiering software, driven by fine-grained latency and bandwidth policies. Attendees will gain valuable insights into the nuanced dynamics of mixed memory configurations, understanding when and how servers can seamlessly adapt to varying workloads.

Author Bio:

Yong Tian is VP of Products for MemVerge. He heads the product strategy for the company’s Memory Machine software. Previously Yong was Co-Founder and COO of UltraSee Corp, a pioneer in software-defined ultrasound imaging. He holds a Master of Management from Stanford Graduate School of Business, Masters of Electrical Engineering from the University of Illinois, and B.E. in Electrical Engineering from the Cooper Union.

Paper Session Description:

This session discusses how memory innovations are leveraging technologies like persistent memory, memory tiering, and the latest addition of CXL. Open source fabric management and orchestration layers for CXL devices and switches can offer best practices for seamless integration with familiar platform management tools. Additionally, with CXL 1.1, servers now supporting memory expansion through CXL Memory Add-in Cards and E3.S memory modules, sellers and buyers can now integrate cost-effective and high-capacity solutions. Attendees will gain valuable insights into the benefits and strategies of incorporating mixed memory configurations in server environments, ultimately optimizing application performance.

PRO DCTR-102-1 Hyperscale Applications Part 1

Ballroom D, Floor 1

Track: Data Center Applications

Organizer:

Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft

Jonathan Hinkle is Senior Director - Azure Memory and Storage Pathfinding at Microsoft. He previously was In Micron's Storage Business Unit, where he investigated new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.

Chairperson:

Steven Wells, Fellow - Storage Solutions Architecture, Micron Technology

Steven is a 37-year veteran with most of that time focused on flash memory component and SSD design. He currently is a Fellow of Storage Solutions Architecture at Micron Technology. He currently holds 60+ patents covering flash memory and security. Recipient of 2017 FMS Most Innovative Memory Technology - Data Center.

Paper Presenters:

Vineet Parekh, Hardware Systems Engineer, Meta

Paper Title:

SSDs in Meta Datacenters

Paper Abstract:

In this presentation we will cover how flash is used in the Meta datacenter fleet. What are the challenges we observe in designing and sustaining storage in fleet. At end we will talk about how the ecosystem is changing for storage and how is Meta contributing here.

Author Bio:

Vineet Parekh has been working in the hyperscale industry for more than a decade. He is a Hardware Engineer at Meta where he is responsible for design, testing and reliability of the Meta server fleet.

Lee Prewitt, Principal Hardware Program Manager, Microsoft

Lee Prewitt is a Principal Hardware Program Manager with 25 years of storage industry experience ranging from Magneto-Optical to spinning rust to Flash. His former work at Microsoft has included working in the Windows and Devices Group where he was responsible for many of the components in the storage stack including File Systems, Spaces, Storport and Microsoft’s inbox miniport drivers. His responsibilities included storage devices ranging from SD and UFS in mobile to NVMe in Enterprise and Data Centers. He currently works in the Azure CSI team where he is responsible for future Data Center storage initiatives, specifications and evangelization.

Ross Stenfort, Hardware Systems Engineer, Storage, Meta

Paper Title:

Storage Industry Update

Paper Abstract:

Ross Stenfort (Meta) and Lee Prewitt (MSFT) will provide an update on the storage from a hyperscale perspective.

Author Bio:

Ross Stenfort is a Hardware System Engineer at Meta delivering scalable storage solutions. He has been involved in the development of storage systems, SSDs, ROCs, HBAs and HDDs with many successful products and over 40 patents.

Bill Gervasi, Principal Systems Architect, Wolley Inc

Paper Title:

NVMe Over CXL: How CXL Lets Us Do Controller Memory Buffers the Right Way

Paper Abstract:

NVMe has supported controller memory buffers since version 1.2 of the specification, however CMB performance advantages were limited by the PCIe bus itself which does not support a lightweight memory protocol. CXL fixes this fundamental limitation of CMBs by allowing efficient memory accesses with the CXL.mem protocol over that same PCIe physical interface while the CXL.io protocol supports all the legacy functionality of NVMe without requiring applications to be rewritten. Race conditions in resource allocation are resolved by having storage and memory on the same device. Advantages of SSDs using NVMe Over CXL are detailed and compared to memory semantic SSDs. The merging of storage and memory has another side benefit: DRAM persistence ala NVDIMM-N.

Author Bio:

Paper Session Description:

This session will share the latest updates on storage from a hyperscale perspective in the storage industry. We will delve into the use of SSDs in Meta datacenters, exploring the challenges faced in designing and maintaining storage in the Meta fleet. We’ll also shed light on the changing landscape of the storage ecosystem and Meta's role in shaping it. Additionally, the discussion on Flexible Data Placement (FDP) in the real world will highlight the advantages of FDP at scale, offering insights into its practical applications and benefits.

Open SPOS-102-1: SNIA: Data and Storage Standards to Accelerate Implementations NEW

Ballroom A, Floor 1

Track: Sponsored Sessions

Sponsor:

SNIA

Organizer + Chairperson:

Bill Martin, Principal Engineer SSD I/O Standards, Samsung Electronics

Bill has been involved in the storage industry for over 30 years, starting in 1983 with the development of a proprietary optical storage interface for HP, architecting the HP Tachyon interface chip for Fibre Channel, serving on industry consortiums and standards bodies for storage including SNIA, INCITS T11, INCITS T10, INCITS T13, SATA-IO, and NVMe. He currently represents Samsung SSD technologies in the standards community as co-chair SNIA technical council, Vice Chair INCITS T10, Board member NVMe board, Secretary INCITS T13, Co-Chair SNIA Object Drive TWG, and active contributor to the technical work of these organizations.

Paper Presenters:

Anthony Constantine, SFF Co-Chair and SNIA Technical Council, SNIA

Paper Title:

SFF: Connecting Everything Together

Paper Abstract:

SNIA's SFF group is prolific, putting out hundreds of specifications. But what do they do, and who is involved? The SFF specifications for connectors, transceivers, and form factors are used pervasively throughout the computer industry, providing standardized interconnects for systems, devices, and fabrics. Learn about the broad-reaching scope of current and future work the SFF is undertaking.

Author Bio:

Anthony Constantine is the author for several EDSFF specifications and contributes to other SFF TA specifications within SNIA. He also serves as co-chair for the SFF TA. In addition, Anthony contributes to PCI-SIG, JEDEC, Open Compute Platform (OCP), and the Open NAND Flash Interface (ONFI). Anthony has over 23 years of experience in the technology industry with an expertise in memory, storage, physical interfaces, low power technologies, and form factors. He earned a BS in Electrical Engineering from UC Davis.

Richelle Ahlvers, Storage Technology Enablement Architect, Intel

Paper Title:

Manageability

Paper Abstract:

SNIA has been the source for storage management standards for over 20 years, and continues to lead with standards-based management interfaces for key use cases and configurations, from enterprise, to NVMe, to cloud, enabling infrastructure for applications from traditional to bleeding edge. Learn how SNIA works with partners to rapidly adapt manageability strategies for standards with technologies like SNIA Swordfish(tm).

Author Bio:

Richelle Ahlvers is a Storage Technology Enablement Architect at Intel, where she promotes and drives enablement of new technologies and standards strategies. Richelle has spent over 25 years in Enterprise Storage R&D teams in a variety of technical roles, enabling new technology ecosystems, leading the architecture, design and development of storage array software, storage management software user experience projects including mobility, developing new storage industry categories including SAN management, storage grid and cloud, and storage technology portfolio solutions. Richelle has been engaged with industry standards initiatives with SNIA and DMTF for many years. She serves on the SNIA Board of Directors, the Chair of the Storage Management Initiative, and has led the SSM Technical Work Group developing the Swordfish Scalable Storage Management API from the group’s inception; she is the alliance liaison between SNIA and DMTF, as well as the alliance liaison for OFA, OCP, and the SODA Foundation. She has also served as the SNIA Technical Council Chair and been engaged across a breadth of technologies ranging from storage management, to solid state storage, cloud, and green storage. Richelle has also initiated and led both site and corporate level women's diversity forums, and presents regularly at diversity conferences

Shyam Iyer, Distinguished Engineer, Dell

Paper Title:

Accelerators: SDXI, DPUs, and Storage

Paper Abstract:

Shyam Iyer, Chair of the SNIA Smart Data Accelerator Interface (SDXI) Technical Work Group, provides an update on this SNIA standard for a memory-to-memory data movement and acceleration interface

Author Bio:

Shyam Iyer is a Distinguished Engineer in Dell's Chief Technology and Innovation Office experienced in Researching, Designing, Developing, Debugging, Validating, Leading, and Driving System and Software solutions that have an industry-wide impact. With 50+ granted patents and several patent pending applications, Shyam has wide experience with Kernel, Device Drivers, Operating Systems, Virtualization, FPGA/Hardware device definitions, system architecture, performance tuning, Simulation, characterization, Storage Networking protocol stacks, OS/BIOS interfaces, Systems management, CPU micro-architecture, security architectures, etc. He works on a variety of forward-looking concepts and strategies in Dell’s technical leadership community. He regularly presents/reviews solutions internally and externally with C-level execs, customers, and developer-oriented audiences. Shyam writes code/reviews them for relief and enjoys a healthy smattering of technical and business-oriented discussions. Among his SNIA activities, Shyam is the Chair for SDXI (Smart Data Accelerator Interface), a SNIA Technical Working Group(TWG) that aims to develop, extend, and drive an extensible, virtualizable, forward-compatible, memory to memory data movement and acceleration interface standard. He is the co-chair for the SDXI + Computational Storage Subgroup that envisions SDXI devices in a Computational Storage architecture and works to propose Computational Storage features to the SDXI standard. Shyam was recognized with the “Excellence in Leadership” award by SNIA membership in 2022. Under his leadership, SDXI TWG won the “SNIA TWG of the Year” award in 2021 and the “Most Innovative Memory Technology” award at Flash Memory Summit(FMS) 2023 for SDXI specification v1.0.

Paul Coddington, Engineer, Amphenol

Paper Title:

SFF: Connecting Everything Together

Paper Abstract:

Author Bio:

Bio Not Available

Paper Session Description:

SNIA develops standards across a wide range of data and storage technologies today. This session will provide a brief overview of the organization’s scope, and dive into three of SNIA’s key standards that affect the future of memory and storage. SNIA has led the development of standards-based management standards and conformance programs for over 20 years. Get an update on the latest work from SNIA and its alliance partners to provide integrated manageability standards across technologies. SNIA’s SFF specifications provide the necessary connectors and form factors to deliver interoperable systems. Recent demand for offload-based data processing is driving increased demand for accelerators, and in turn, for standardization of accelerator usage

PRO SSDT-102-1: SSD Technologies for Compute Use Cases

Ballroom F, Floor 1

Track: SSD Technology

Chairperson:

Phil Colline, Senior Principal Architect, Marvell Technology Inc

Phil Colline is a Senior Principal Architect at Marvell with more than two decades of experience as a storage software architect and firmware developer. In his role, Phil is responsible for contributing to the architecture definition for NVMe-oF, NVMe, and other memory-based products. Phil joined Marvell from Seagate Technology, where he was a Principal Software Engineer. At Seagate Technology, he was a member of the Systems Group Advanced Development team and architected, designed and delivered a number of NVMe and NVMe-oF controller and interface solutions for Seagate’s external RAID controllers. Prior to this, Phil was Principal Software Engineer at Dot Hill Systems, where he was responsible for the RAID system solution I/O architecture and the lead architect for the company’s T10 PI feature. Phil holds a B.S in Information and Computer Science from UC Irvine and has been awarded 7 patents in the areas of data storage and IO interfaces.

Organizer:

Erich Haratsch, Senior Director Architecture, Marvell

Erich Haratsch is Senior Director Architecture at Marvell, where he leads the architecture definition for Bravera™ SSD controllers and other memory-based products. Prior to joining Marvell, he worked at Seagate and LSI, where he worked on Nytro® and SandForce® branded SSD controllers. Earlier in his career, he developed signal processing and error correction technologies for multiple generations of HDD controllers at LSI and Agere Systems. He started his career at AT&T and Lucent Bell Labs, where he worked on Gigabit Ethernet over copper, optical communications and the MPEG-4 video standard. He is the author of over 40 peer-reviewed journal and conference papers, and holds more than 200 U.S. patents. He also is a Senior Member of IEEE, and earned his MS and PhD degrees from the Technical University of Munich (Germany).

Paper Presenters:

Trent Johnson, SSD Hardware Architect, IBM

Paper Title:

FlashCore Module (FCM): Meet the Engine Behind IBM's Flash Systems

Paper Abstract:

The 4th generation IBM FlashCore Module delivers enterprise level storage to clients using inexpensive QLC flash memory technology. It offers many optimizations through its computational storage architecture. How do we do it? We will go through some of the hardware implementation details and features to demonstrate how FlashCore Modules can save money on capacity, and power as well as improve RAID performance and keep data safe from ransomware attacks.

Author Bio:

Trent Johnson is a Hardware Architect at IBM, with a focus on the IBM FlashCore Module. He joined IBM as part of the Cleversafe Acquisition where he was also the System Hardware Architect of exabyte-scale object storage. Prior to Cleversafe, he developed system-level manufacturing and test solutions for AMD CPUs and GPUs where he was awarded the AMD Corporate Technical Achievement Award. He has 24 years of industry experience, holds 7 US patents and has published at the Burn-in and Test Socket Workshop as well as the Conference for Consumer Electronics. He earned BSEE and MSEE degrees from The University of Texas at Austin in Electrical Engineering with a focus on Manufacturing System Engineering.

Nick Snow, Product Manager, Enterprise SSDs, KIOXIA America, Inc

Paper Title:

PCIe 6.0 SSDs: Powering the Future of Compute and Storage.

Paper Abstract:

In January 2022, the PCIe 6.0 specification was officially ratified. Among many new features, most notable is it’s doubling of performance compared to the PCIe 5.0 specification to an incredible 128GB/s for an x16 link. With this new massive speed comes new considerations for NVMe solid state drives. As performance and power requirements increase, we will discuss what form factors are best to take advantage of PCIe 6.0. We will also consider signal integrity, thermal constraints, and other aspects that need to be at the forefront of any new PCIe 6.0 NVMe SSD designs.

Author Bio:

Nick Snow has held device and system design engineer and product line manager positions within in the data storage industry for over 10 years.

Devesh Rai, Sr. Staff Strategic Marketing Manager, KIOXIA America, Inc

Paper Title:

Review of RAID Offload Concept and Its Adoptability in Different Applications.

Paper Abstract:

Data redundancy solutions by nature are compute intensive and pose challenges on system resources. NVMe SSDs equipped with RAID offload technology can be used in reducing RAID application usages of compute, DRAM usages and cache thrashing. KIOXIA proposes a scale out RAID offload technology can be adopted in following areas; attaining sustainability goals in data scrubbing; reducing network traffic in RAID volumes spread across multiple canisters; rebuilding data on drives within RAID setups; data center applications like VMWare’s VSAN 8.0; mixed drive setups like high performance computing nodes; and conventional hardware and software RAID applications.

Author Bio:

Devesh Rai has held senior software engineer positions over the past 20 years. Devesh’s extensive experience includes designing and developing host I/O stack, distributed file system, DRaaS, and firmware for NVMe SSDs.

Chandra Nelogal, Distinguished Member of Technical Staff, Trusted Computing Group

Paper Title:

Review of RAID Offload Concept and Its Adoptability in Different Applications.

Paper Abstract:

Author Bio:

Chandra Nelogal is an Engineering Technologist working in the area of data storage and security in the Dell’s Infrastructure Solutions Group. Chandra represents Dell in the Trusted Computing group, co-chairing the Storage Work group. Chandra also contributes to the DICE work group in TCG as well as to other work groups in other Industry standards organizations that focus on platform infrastructure (DMTF PMCI) and security (DMTF SPDM). Chandra is a prolific inventor with 70 granted patents from USPTO. Chandra has a B.S. in Computer Science from Bangalore University in India, and an M.S. in Engineering from the University of Texas at Austin in the US. Chandra has presented on security topics at conferences such as SNIA SDC, SNIA Security Summit and Flash Memory Summit.

Paper Session Description:

In this session, we look at SSD technologies for compute use cases. PCIe 6.0 SSDs are revolutionizing the future of compute and storage with their incredible speed and performance, doubling that of the previous generation. As NVMe solid state drives continue to evolve, new considerations such as signal integrity and thermal constraints must be taken into account to fully leverage the power of PCIe 6.0. RAID offload technology offers a promising solution to reduce compute and DRAM usage in data redundancy applications, making it adaptable in various areas such as data scrubbing, network traffic reduction, and data center applications. The FlashCore Module from IBM is the engine behind their Flash Systems, providing enterprise-level storage with cost-saving features and improved performance. Knowledge Aware SSDs are introducing a novel method to rebuild failed RAID drives, leveraging firmware to offload host system resources and optimize overall system performance.

PRO UCIC-102-1: UCIe Technology Opportunities & Benefits NEW

Ballroom G, Floor 1

Track: UCIe and Chiplets

Organizer:

Brian Rea, Technology Initiative and Ecosystem Enablement Manager, Intel

Paper Presenters:

Mayank Bhatnagar, Product Marketing Director, Cadence Design Systems

Paper Title:

How UCIe Reduces the Barrier to Entry in Chiplet Design

Paper Abstract:

The design of systems-in-package (SIP) or System-on-chip is a process with an excessive cost in terms of resources and time. However, there are designers with differentiated ideas big enough for chiplets, and users that want to buy these prefabricated chiplets to reduce their time and design costs. A widely adopted open standard such as UCIe enables that, without which all chiplets must be designed and consumed internally. We discuss the possibilities that UCIe technology opens by reducing the barrier to entry for boutique chiplet designers. We also present illustrative examples of how it helps chiplet users by fostering innovation and competition by enabling a chiplet marketplace.

Author Bio:

Mayank Bhatnagar is a product marketing director with Cadence Design Systems, where he focuses on die-to-die interface IP, including UCIe. His goal is to align Cadence's IP strategy to the overall market direction and enable IP solution tuned to customer needs. Prior to this, he has worked on fabrication technology, device design, foundational IP, SOC and block level digital implementation,and interface IPs such as DDR, LPDDR, HBM, AIB, HBI, and UCIe. He holds a master's degree in electrical engineering, and a master's degree in business administration.

Paper Session Description:

UCIe (Universal Chiplet Interconnect Express) is revolutionizing the field of SoC construction by providing an open industry standard that allows for more customizable package-level integration. Founded by key players in the semiconductor industry, UCIe 1.1 Specification was introduced at FMS 2023, bringing significant improvements to the chiplet ecosystem. This session will highlight the enhancements made in the UCIe 1.1 specification, as well as how it simplifies system setups and compliance testing for device interoperability. By reducing the barrier to entry for boutique chiplet designers and enabling a "chiplet marketplace," UCIe is paving the way for a more innovative and competitive future in chiplet design.

10:50 AM to 11:00 AM

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Open Chairman's Welcome

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Organizer + Moderator:

Charles Sobey, Chief Scientist, ChannelScience

Chuck Sobey is Conference Chair of FMS. Under his leadership, FMS has increased its size, scope, and influence worldwide, while navigating the unprecedented effects the pandemic has had on the global events industry. Chuck is a respected memory and storage technology strategist, researcher, and lecturer. As Chief Scientist of ChannelScience, he guides clients in evaluating emerging memory and storage technologies and in maximizing their reliability and performance. He uses probability analysis to match a technology's projected capabilities to an application's requirements. His team has won SBIR awards from the US Department of Energy to advance the field of magnetic tape recording, on which practically all of the hyperscale and cloud services rely. Chuck's clarity of explanation and extensive experience and industry network make him a sought-after technical and business development consultant. He has taught storage/memory technology seminars around the world. Chuck is also General Chair of SmartNICs Summit, which he is co-developing to support the hyperscale and cloud data center ecosystem. He earned an MS ECE from the University of California, Santa Barbara and a BS ECE from Carnegie Mellon University. He holds 7 US patents.

Special Presentation Description:

FMS Conference Chair Chuck Sobey welcomes all to FMS24 - the Future of Memory and Storage, and provides an overview of the three day event.

11:00 AM to 11:30 AM

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Open Keynote 1: KIOXIA: Advancements in flash memory technologies to unleash the power of AI

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Keynote Speakers:

Atsushi Inoue, VP and Technology Executive, KIOXIA

Mr. Atsushi Inoue is seasoned Vice President and Technology Executive in the Memory Division at KIOXIA Corporation. With over 30 years of experience in the flash memory industry, he plays a crucial role in product planning, technical marketing, and customer support for the latest 3D flash memory BiCS FLASH™. His responsibilities also include application engineering and development support for NAND components and applications. In his recent activities, one remarkable accomplishment is the launch of BiCS FLASH™ generation 8, which utilizes a groundbreaking technology of bonding the CMOS wafer and Cell Array wafer together, aiming for further capacity and density enhancement of flash memory. Mr. Inoue graduated from the Department of Materials Science and Engineering, Faculty of Science and Engineering, Waseda University in 1993. In the same year, he joined Toshiba, contributing to the evaluation of early-stage 4Mbit and 32Mbit NAND flash memory in the Memory Evaluation Engineering Department. In 1999, he moved to Toshiba America Electronic Components, where he supported the initial expansion of NAND technology. Upon returning to Japan in 2003, he worked in the Memory Evaluation Engineering Department, focusing on new technologies such as 70nm QLC and 56nm TLC. From 2009, he worked in the Memory Application Engineering Department, where he was involved in planning NAND products for the enterprise and data center markets. Subsequently, he served as Senior Director in the Memory Technical Marketing Managing Department before assuming his current position. Mr. Inoue is currently based at the KIOXIA Corporation headquarters in Tamachi, Tokyo, Japan.

Neville Ichhaporia, Sr. VP & General Manager, KIOXIA America, Inc

Mr. Ichhaporia holds the position of Senior Vice President and General Manager of the SSD Business Unit at KIOXIA America, Inc. In this role, he is responsible for the company’s marketing, business management, product planning, and engineering teams, overseeing the SSD product portfolio aimed at cloud, data-center, enterprise, and client computing market segments. Neville has over 20 years of extensive industry experience across a variety of responsibilities and disciplines, including product management, strategic marketing, new product development, hardware engineering, and R&D. Prior to joining KIOXIA in 2016, Neville held diverse roles in business, product management, and engineering development at Toshiba Memory America, SanDisk, Western Digital Corporation, and Microchip. Mr. Ichhaporia holds an MBA from the Santa Clara University Leavey School of Business, an MS in Electrical Engineering and VLSI Design from the University of Ohio, Toledo, and a BS in Instrumentation and Control Systems from the University of Mumbai. He is based at KIOXIA America’s headquarters in San Jose, CA.

Keynote Description:

With continued pursuit of innovation for more than 35 years, NAND flash memory has become an indispensable technology to capture data – the “new currency” of our digital world – fueling emerging paradigms in the world of AI, Cloud, and Edge Computing. Looking toward the future, KIOXIA’s BiCS FLASH™ 3D generations will continue to scale, enabling higher density and performance along with cost and power improvements. KIOXIA will lead the way and present cutting edge memory and SSD technologies, as well as highlight advanced developments to address the memory and storage needs for next-generation applications with innovations and optimizations rooted in flash-memory based technologies and approaches. No matter what your application, get there with KIOXIA.

11:30 AM to 11:40 AM

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Open 2024 Lifetime Achievement Award

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Organizer + Moderator:

Brian Berg, President, Berg Software Design

Organizer + Moderator:

Jim Handy, General Director, Objective Analysis

Jim Handy is President of Objective Analysis, a strategic marketing and market research firm for the semiconductor industry. He has over 30 years of electronic industry experience, including 14 years as an industry analyst with Dataquest and Semico Research. A frequent presenter at trade shows, Mr. Handy has also written hundreds of articles and is frequently interviewed and quoted in the electronics trade press and other media. Mr. Handy writes the Chip Talk blog for Forbes online and contributes to two Objective Analysis blogs: The SSD Guy and The Memory Guy. He is the author of “The Cache Memory Book” and a patent holder in cache memory design. He holds a BSEE from Georgia Tech and an MBA from the University of Phoenix.

Special Presentation Description:

The FMS Lifetime Achievement Award recognizes individuals who have shown outstanding leadership in promoting the development and use of memory, storage, and/or associated or related technologies, including one or more of the following: - Creating or promoting an important memory or storage technology, or a related technology, - Leadership of a major memory or storage company, business effort, or academic program, - Bringing memory or storage technology to a new and important application Lifetime Achievement Award winners may be for a single person, or for a small team or group of individuals with an important connection. By bestowing this award, FMS hopes to help foster further advances in the memory and storage industries.

11:40 AM to 11:45 AM

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Open 2024 Special Award

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Special Presentation Description:

Description Not Available

11:45 AM to 12:15 PM

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Open Keynote 2: NEO Semiconductor: New 3D AI Chip Technology Accelerates Generative AI

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Keynote Speakers:

Andy Hsu, Founder & CEO, NEO Semiconductor

Andy Hsu is the Founder and CEO of NEO Semiconductor, a company focused on the development of innovative architectures for NAND flash and DRAM memory. Andy is responsible for the overall company strategy, execution, and technology innovation that fuels the company's growth. He has more than 25 years of experience in the semiconductor industry including positions as VP of Engineering and leader of R&D and Engineering Teams. This resulted in the development of more than 60 products in various non-volatile memories. Andy is an accomplished technology visionary and inventor of more than 120 granted U.S. patents. He performed research in the fields of Neural Networks and Artificial Intelligence (AI) while earning a master's degree in Electrical, Computer, and System Engineering (ECSE) from Rensselaer Polytechnic Institute (RPI) in New York. He earned a bachelor's degree from the National Cheng-Kung University in Taiwan.

Keynote Description:

The demand to accelerate artificial intelligence applications (AI apps) continues growing, especially for emerging workloads involving artificial neural networks like generative AI. Current AI Chips simulate neural networks for AI apps using a processor (GPU), memory (HBM), and software, but architectural inefficiencies waste significant amounts of performance and power. Next-generation AI Chips will use totally new AI Chip technology to perform neural network operations inside 3D DRAM, enabling 100x higher performance and 99% lower power consumption. New 3D architectures have the potential to enable the next wave of AI applications with more innovative memory and storage solutions.

01:00 PM to 01:30 PM

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Open Keynote 3: SK hynix: AI Memory & Storage Solution Leadership and Vision for AI Era

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Keynote Speakers:

Unoh Kwon, VP, Head of HBM PI, SK hynix

Unoh Kwon is vice president of the HBM process integration group at SK hynix, leading the development and enablement of next generation HBM process technologies. Unoh Kwon has also served as fellow in various technology and product development roles in DRAM development group. Prior to joining SK hynix, he managed product integration group at GlobalFoundries and held logic technology process integration positions at IBM. Unoh Kwon holds Ph.D degree in materials science and engineering from Stanford University.

Chunsung Kim, Head of WW SSD PMO, SK hynix

Chunsung Kim, head of WW SSD PMO, is leading SK hynix world-wide SSD Program Management Office and also leading world-wide SSD SoC development efforts for both SK hynix and Solidigm. A 15-year veteran of S.LSI development, Chunsung started and built-up SK hynix in-house NAND Flash controller teams and capabilities. He also contributed in stabilizing SK hynix WW RnD operation & management and now is participating in managing Solidigm as part of management staff. With balanced knowledge and expertise of SSD engineering and business, he is playing a key role in oversea SSD RnD management and collaboration with Solidigm. Chunsung Kim earned his Master degree of Control and Instrumentation engineering from Chung Ang University in South Korea.

Keynote Description:

Generative AI, which is currently a hot topic, is evolving into GPT4, multilingual reasoning, and coding capabilities, and is expected to ultimately bring about transformations such as the "Industrial Revolution." SK hynix AI memory plays a pivotal role in AI chips, which is the core background of Generative AI, by providing differentiated values in the AI era. With the rise of Generative AI, customer pain-points are becoming more specific such as ① To maximize the learning/inferencing amount per hour; ② To minimize power consumption for learning/inferencing; ③ To minimize floor space and power utilization for storing data, which is increased for Gen AI use. As memory & storage plays a pivotal role in AI technology, SK hynix is committed to continuous innovation and technological breakthroughs to solve customer pain-points in AI memory & storage development and aims to contribute to the advancement of the ICT industry by providing world-best AI memory products and strengthening collaboration with global partners.

01:30 PM to 02:00 PM

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Open Keynote 4: Samsung: The AI Revolution: Fueling New Demands for Memory and Storage

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Sponsor:

Samsung Electronics

Keynote Speakers:

Taeksang Song, Vice President, Samsung Seminconductor Inc

Taeksang serves as Corporate Vice President at Samsung Electronics, where he leads a team dedicated to advancing cutting-edge technologies, including CXL memory expanders, fabric-attached memory solutions, and processing near memory to meet the demands of next-generation data-centric AI architectures. With nearly two decades of expertise in memory and sub-system architecture, interconnect protocols, system-on-chip design, and collaboration with cloud service providers to enable heterogeneous computing infrastructures, Taeksang is a recognized leader in the field. Prior to joining Samsung, he held leading architect positions at Rambus Inc., SK Hynix, and Micron Technology, focusing on emerging memory controllers and systems. Taeksang earned his Ph.D. from KAIST in South Korea in 2006. Dr. Song has authored and co-authored over 20 technical papers and holds more than 50 U.S. patents.

Hwaseok Oh, EVP of Solution Product Engineering, Samsung Seminconductor Inc

Hwaseok Oh leads the Solution Product Engineering team at Samsung, where he oversees the commercialization of flash storage products that include mobile memory devices like eMMC and UFS, as well as client-, server-, and enterprise-class SSDs. Hwaseok joined Samsung Electronics in 1997 as a SoC design engineer, focusing on the development of network and storage controllers. While working on flash storage products, he pioneered the world’s first UFS products. He also spearheaded the creation of high-performance NVMe SSD controllers for datacenters. More recently, he has been at the forefront of developing new flash storage technologies, contributing to innovations such as Samsung’s SmartSSD and Flash Memory-based CXL Memory Module. Hwaseok holds a Bachelor’s and a Master’s degree in Computer Science from Sogang University, earned in 1995 and 1997, respectively.

Jim Elliott, Corporate EVP, Samsung Electronics

Jim Elliott serves as Corporate Executive Vice President of Memory Sales at Samsung Semiconductor, Inc., responsible for a multi-billion-dollar revenue organization that spans Samsung’s entire memory portfolio in the Americas region. Jim is recognized as a market visionary, championing Samsung’s memory transition and market evolution to provide a synergistic product portfolio covering the server, data center, AI, PC, tablet, phone, wearable device, and automotive markets. He joined Samsung in 2001 and has held leadership positions in both marketing and sales departments. Jim holds a Bachelor of Arts degree from the University of California, Davis and received a Master’s degree in Business Administration from Cal Poly University in San Luis Obispo, CA.

Keynote Description:

As we enter a new phase of the AI revolution, significant technological advancements are reshaping the way we think about computation and data processing. The rapid growth in data generation and complex workload requirements has led to increased computational power, enabling the development of sophisticated, large-scale AI models. This shift necessitates advanced GPUs and enhanced memory and storage solutions for learning and inference. These solutions must provide substantial bandwidth, power-efficiency, and durability to maintain checkpoints and support proliferated multimodal AI models. Concurrently, there is a need to address sustainability challenges, such as increased power and cooling demands within data centers. In this keynote, we will explore cutting-edge memory products and technologies essential for various AI applications, highlighting how NAND solutions and CXL memory modules can be tailored to optimize performance across each application. We will discuss how these technologies meet and drive the demand for high-capacity storage in AI computing, aiming to improve Total Cost of Ownership (TCO) through enhanced power efficiency and effective space management. Some of the main technologies we will cover include cutting-edge DRAM technologies such as 256GB RDIMM/512GB MRDIMM and CXL 3.1 memory modules. We will also discuss high-bandwidth PCIe Gen6, enabling high-speed data access and reliability to enhance GPU efficiency.

02:00 PM to 02:30 PM

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Open Keynote 5: FADU: Navigating AI: Hyperscale Flash Standards and eSSD innovation

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Keynote Speakers:

Eric Spanneut, VP of Marketing, Western Digital

Eric Spanneut is Vice President of Flash Global Product Management at Western Digital. In this role, he is responsible for the company’s enterprise SSDs, client SSDs, eMMC and UFS product portfolio. Prior to Western Digital, Eric had management roles at Honeywell, Micron and Samsung Electronics. Eric earned his Master EE from Telecom Paris Institute of Technology and MBA from INSEAD.

Ross Stenfort, Hardware Systems Engineer, Storage, Meta

Ross is a member of Meta’s Storage Hardware team. He has over 20 years of experience developing and bringing leading edge storage products to market. Ross works closely industry partners and standards organizations including NVM Express, SNIA/EDSFF, and Open Compute Project (OCP). With experience including ASIC design, he has an appreciation for the design challenges facing SSD providers to deliver performance and QoS within a shrinking power envelop. Ross holds over 40 patents.

Jiyho Lee, CEO and Co-Founder, FADU

Jihyo Lee is the CEO and co-founder of FADU Technologies. He is a former partner at Bain & Company and a successful serial entrepreneur involved in multiple businesses in technology, telecom and energy. As CEO of FADU, he has established FADU as a fabless semiconductor innovator, uniting exceptional industry talent to create a revolution in data center and storage for next generation computing architectures.

Keynote Description:

Today Hyperscale’s wield significant influence over flash storage consumption, with a handful of vendors commanding much of the market. Amidst this dominance, the surge of AI applications stands as a pivotal force, reshaping infrastructure demands at an unprecedented pace. This keynote presentation delves into the intersection of hyperscale growth, AI expansion, and flash storage evolution. Exploring the symbiotic relationship between infrastructure advancements and flash storage requirements, we dissect the implications for standardization efforts, particularly through initiatives like the Open Compute Project (OCP). Moreover, we unravel the novel features essential for flash storage to meet the soaring demands of hyperscale environments, offering insights crucial for navigating the future of storage technology.

02:30 PM to 03:00 PM

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Open Keynote 6: Microchip: Quantum-Proofing AI: Next-Gen Security for Protecting the World’s Data

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Sponsor:

Microchip Technology

Keynote Speakers:

Rob Reed, Senior Director of Product Development, Microchip Technology

Rob Reed is Senior Director of Product Development Engineering, Data Center Solutions Group for Microchip Technology. He is responsible for managing and designing storage silicon. Prior to this role, Rob was VP of Data Center SSD Engineering at Kioxia, responsible for the design and launch of Kioxia’s first Datacenter Gen4 PCIe / BICS4 SSD. Rob also worked at Intel as Product Development Manager for Solid State Drive products. Rob has expertise in engineering management, silicon architecture, product development, strategic planning and applications engineering. He holds 6 patents in the US on SSD storage. Rob holds a Batchelor's Honors Degree in Electronics and Communication engineering from the University of Huddersfield University.

Kyle Gaede, Associate Director, Microchip Technology

Kyle Gaede has been with Microchip Technology for nearly 25 years and is currently an Associate Director for the company’s segment group with a focus on data centers. Gaede holds a Bachelor of Science in Electrical Engineering from the University of Texas Austin.

Keynote Description:

In the rapidly evolving landscape of artificial intelligence (AI), data has become the new gold. The need to protect the data and the underlying infrastructure from a myriad of threats has never been more pressing. We will look at the challenges that organizations face, the complexities of security from the ground up and provide key strategies to mitigate risk in a post-quantum world. We will examine the unique vulnerabilities inherent in AI infrastructure, from data pipelines and machine learning models to the compute resources that power them. The discussion will highlight how these vulnerabilities can be exploited by adversaries to compromise the integrity, confidentiality and availability of AI systems. We will highlight real-world scenarios where security breaches have led to significant consequences, underscoring the importance of a proactive and comprehensive security strategy. We will introduce a multi-layered approach that encompasses the latest in cybersecurity best practices, tailored specifically for the nuances of AI systems. We’ll look at security for data at rest and in transit and protecting model integrity. We will also consider the implications of quantum computing and what is needed to address those challenges. Attendees will gain an understanding of the key issues and strategies to secure their AI infrastructure effectively and how Microchip is working across our portfolio and within the industry to create a complete security solution for protecting the world’s data.

03:00 PM to 03:30 PM

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Open Keynote 7: Western Digital: New Era of NAND

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Keynote Speakers:

Robert Soderbery, Executive Vice President & General Manager, Western Digital

Prior to joining Western Digital, Soderbery served as president of UpLift, Inc., a travel finance company. Soderbery previously served as senior vice president and general manager, enterprise products, and in other senior leadership roles at Cisco Systems. He also advanced through a series of leadership roles at Symantec Corporation, including senior vice president, storage, and availability management group. Soderbery also serves as a member of UpLift’s board of directors, an advisor to Rockwell Automation, Inc. and as managing member of Acclimate Ventures LLC, a consulting, advisory and investment firm.

Keynote Description:

With the new era of NAND being driven by new industry dynamics Western Digital Executive Vice President & General Manager, Flash Business, Robert Soderbery, will discuss how the focus has shifted towards optimizing supply and demand, ensuring products meet customer needs, and navigating a market that is increasingly complex and segmented. He will share important insights on the critical role of storage in the AI data center all the way to the edge. Finally, Robert will reveal next-generation products and technologies fueling growth across the entire data cycle.

03:30 PM to 07:00 PM

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Open Grand Opening Reception

Exhibit Hall, Floor 1

Track: Exhibits

General Event Description:

FMS24 welcomes all attendees to their Grand Opening Reception in the Santa Clara Convention Center Exhibit Hall. Join fellow attendees and FMS24 sponsors to celebrate the Future of Memory and Storage!

03:40 PM to 04:45 PM

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PRO AIML-103-1: Memory to Data Center: Architectures and Interconnect Technologies

Ballroom B, Floor 1

Track: AI and ML Applications

Organizer + Chairperson:

David McIntyre, Director Product Planning, Samsung Electronics

Panel Members:

Siamak Tavallaei, Sr. Principal Engineer, Samsung

Craig Carlson, Technologist, AMD

Craig Carlson is a Sr Technologist at Marvell with over 25 years of industry experience. He is an active leader in storage and networking standards, including being a member of the SNIA Technical Council and of the Board of Directors for NVM Express, FCIA, and the Ethernet Alliance. Craig is also the Chair of ANSI T11, which defines Fibre Channel, and of FC-NVMe (NVMe over Fibre Channel). He is the technical Editor of many T11 standards, as well as standards from IEEE802.1 and IETF. He has held engineering positions with Cavium, QLogic, and Ancor and is a frequent participant in webinars, technical meetings, and conferences, including Flash Memory Summit.

Kurtis Bowman, Director, Server System Performance, AMD

Kurtis Bowman is Director, Server System Performance at AMD. With more than 25 years of experience in the architecture, development, and business justification of server, storage, commercial, and consumer computing products, his current areas of interest include converged and hyperconverged systems, heterogeneous compute elements for HPC & machine learning, and data analytics. He has built teams and managed firmware and hardware development through entire lifecycles in both startups and mature companies. Mr. Bowman earned a BSEE from New Mexico State University, holds multiple patents, and has written articles in the technical and trade press.

Willie Nelson, Technology Enabling Architect, Intel

Willie Nelson has been involved in early adoption of various storage technologies over the past 22+ years, working to enable transitions to new interfaces and use cases for areas including PCIe, CXL, NVMe, SSDs, NVDIMMs, Optane, and other Persistent Memory devices. He has been an active member of Jim Pappas' Ecosystem Enabling team, working directly with vendors for early enablement and adoption of key new I/O technologies. Willie is also heavily involved in running and managing multiple successful industry associations and cross-industry initiatives, including by way of his current roles as Treasurer for the SNIA Compute Memory and Storage Initiative (CMSI), and as Co-Chair of the CMSI Marketing Working Group.

Panel Session Description:

This exciting new session at FMS24 will discuss interconnect architecture considerations and provide an Ultra Architecture Link (UALink) and Ultra Ethernet Consortium (UEC) overview, A panel discussion will follow.

PRO AOSD-103-1: Aerospace and Outer Space Data NEW

Ballroom E, Floor 1

Track: Aerospace to Outer Space Data (AOSD)

Organizer + Chairperson:

TInh Ngo, VP Business and Technology Development, VIRTIUM

Tinh Ngo, VP of Business and Technology development at Virtium overseeing the acquisition of new business ventures and the alignment of technology to market needs. He has over 20 years of experience in strategic marketing and business development with extensive knowledge of the semiconductor space, specifically in the storage (Flash, SSD) and memory (DRAM, Packaging) markets. Prior to joining Virtium, he held VP roles responsible for leading sales, business development and marketing at Netlist and Viking Technology (Sanmina), with previous positions as Director, Marketing for HGST/STEC.

Paper Presenters:

Crystal Chang, Senior Manager, ATP Electronics

Paper Title:

Investigating NAND Storage Susceptibility to Single-Event Effects

Paper Abstract:

This study explores the susceptibilities of NAND Flash storage to both destructive and nondestructive single-event effects (SEE) induced by proton and heavy ion irradiation. The focus is on understanding how these memories respond to radiation exposure and the possible solutions based on experimental findings.

Author Bio:

Crystal Chang is an accomplished professional with a master’s degree in business administration from the University of Newcastle Upon Tyne, UK. With 15 years of experience at ATP Electronics, Crystal has demonstrated exceptional leadership in various domains. Her expertise extends to managing ATP Automotive, Thermal, and LEO satellite projects, where she drives continuous innovation and ensures successful design-ins.

George Williams, Chief AI Officer, Armijo Innovations

Paper Title:

The Next Frontier of Scaling Memory is Space

Paper Abstract:

The demand for higher density, lower latency, and more robust memory is greater than ever, and this global need is driving innovation up and down the technology stack - from new material substrates, to advanced interconnect photonics, to novel chip and datacenter architectures. Unfortunately even these measures may not be enough! Applications fueled by ever growing AI models and the burgeoning 6G internet are surpassing existing memory capacity both at the edge and at the datacenter. Pushing beyond the limitations of earth-bound commercial tech into space may just be the answer we need. The current terrestrial path of building more datacenters and installing more GPUs is not sustainable. Space, on the other hand offers infinite scaling potential for datacenters, with its nearly inexhaustible source of solar energy combined with relatively few regulations on expansion and growth. But how close are we to realizing this vision? We will talk about the R&D that is already underway to address many of the technical challenges of scaling memory and data storage into space- from advances in space-grade microelectronics, to photonic/quantum communication enabling satellite-based datacenter constellations. Along the way, disruption will occur at many levels - from a new supply chain that might require manufacturing chips in space, to new attack surfaces necessitating novel cybersecurity strategies, to the need for international collaboration beyond anything we've forged on earth.

Author Bio:

George Williams is Chief AI Officer at Armijo Innovations. He has held senior leadership roles in data science and artificial intelligence in industry at GSI Technology, Smile Identity, Capsule8, and Apple's New Product Architecture Group, as well as in academia at New York University's Courant Institute. He can talk on a broad range of topics at the intersection of e-commerce, machine learning, cybersecurity, computer hardware, computer science, and artificial intelligence. He is an author of several research papers in computer vision and deep learning, published at NeurIPS, CVPR, ICASSP, ICCV, and SIGGRAPH. George is regularly invited to present at meetups and technology conferences, including recent talks at Zilliz Unstructured Meetup, Open Compute Project, Storage Developer’s Conference, SEEMAPLD, Blackhat, Open Data Science Conference, Apache Spark Summit, JupyterCon, AnacondaCon, and Caltech’s Space Computing. He served as organizer and track chair for the Valleyml.ai conference and as a workshop program manager for the Vector Search Challenge at NeurIPS

Paul Armijo, President and CEO, Armijo Innovations

Paper Title:

The Next Frontier of Scaling Memory is Space

Paper Abstract:

Author Bio:

Paul Armijo is the President & CEO at Armijo Innovations. He has senior leadership in roles including CTO in space and technology development industry at General Dynamics Mission Systems, Northrop Grumman, BAE Systems Space & Mission Systems, Frontgrade Technologies, GSI Technology, Secure Quantum Services, and Avalanche Technology. He has had the privilege of leading numerous flagship programs and technology development efforts over his career to further enable the space community. He has served various technical and session chairs as well as presented at various conferences in the space, memory, and AI community like SEE/MAPLD, ODSC, SPWG, HEART, NSREC, Space Computing, RHET, among many others. Paul received his B.S. in electrical engineering from Arizona State University.

Sebastien Jean, CTO, Phison Electronics

Sebastien Jean is the Chief Technology Officer at Phison Electronics, where he focuses on developing technology strategy and building alliances with other innovative companies. He also works closely with engineering teams to help integrate new concepts into products. With 26 years of experience and over 30 filed patents, he has established himself as a thought leader in the storage industry. Before joining Phison, he held senior technology positions at Micron, SanDisk, and Western Digital. At Phison, he helped devise an iterative technology roadmap that advances Security, AI, Computational Storage and Space Storage Solutions. He earned a BS in Computer Science at the University of Ottawa (Canada).

Dr Nilsen, Chief Technology Strategist, Flexxon

Paper Title:

RAD-HARD NAND Storage for Aerospace and Outer Space Data (AOSD)

Paper Abstract:

The development of radiation-hardened NAND storage systems presents a critical advancement. By creating robust NAND storage solutions specifically designed to withstand the harsh radiation environments of space, a significant improvement in data reliability and longevity can be achieved. RAD-HARD NAND storage can withstand significantly higher levels of radiation than traditional NAND storage. RAD-HARD NAND storage is made from special materials and processes that make it resistant to radiation damage. This presentation will delve into the challenges faced in storing data in aerospace and outer space contexts, the unique requirements for radiation-hardened NAND storage, and the potential impact of such technology on enhancing data integrity and resilience in extreme environments.

Author Bio:

Dr Erik Nilsen is Flexxon’s Chief Technology Strategist, he works closely with the company’s executive management and R&D team to design and deploy technological roadmaps for its value-driven cybersecurity innovations. He also advises on the company’s ongoing work with its partners and customers to synthesize their needs and pain points with tailored solutions. Erik is a strong advocate for the decentralized Internet and espouses the advancement of digital methods and innovation to address the rising threat of cyberthreats. He is passionate about defining, developing, and launching new high-tech hardware & software products to meet the needs of digital citizens for the safe and secure navigation of today’s hyperconnected world. In addition to his role at Flexxon, Erik is a serial entrepreneur who co-founded TauTuk in 2021. As CTO, he led R&D efforts in next-generation cybersecurity and developed a pioneering product for out-of-band (analog) cybersecurity in industrial control systems and critical infrastructure. With advanced degrees in physics, electrical engineering, and mathematics, Erik's expertise spans signal processing and hardware & software development.

Paper Session Description:

In the realm of aerospace and outer space data storage, the development of radiation-hardened NAND storage systems is crucial. These robust solutions are specially crafted to withstand the intense radiation environments beyond Earth, ensuring enhanced data reliability and longevity. RAD-HARD NAND storage is equipped to endure high levels of radiation, thanks to its unique materials and manufacturing processes. This session will address the challenges of storing data in space, the specific requirements for radiation-hardened NAND storage, and the potential impact of this technology on fortifying data integrity in extreme conditions. It's a groundbreaking leap in data storage capabilities for the aerospace industry.

Open BMKT-103-1: CMO Panel

GAMR 1 (Great America Meeting Room 1), Floor 2

Track: Business Strategies and Memory Markets

Organizer + Chairperson:

Jay Kramer, President, Network Storage Advisors

Jay Kramer is a world recognized technology consultant specializing in training and delivering marketing services for the network storage industry. He has personally trained over 2000 professionals on storage networking, and he currently works with leading and emerging storage product companies worldwide. Jay has been VP Worldwide Marketing and Product Management for many storage companies including Sepaton (acquired by HDS), Astute Networks, iStor Networks, Infinity I/O, Maxtor, and Creative Design Solutions. He also has long experience in marketing and strategic planning at Unisys. An industry leader, he has served on the Board of Directors of the Fibre Channel Industry Association (FCIA) and was one of the Founders of the Flash Memory Summit. Jay has chaired SNIA committees and was a driving force in launching the first open systems SAN Certification Program, thus creating a career path for storage professionals. He has also been a featured speaker at industry conferences and has published articles and white papers on network storage, cloud storage, storage virtualization, data protection, and software defined storage. He is a graduate of Syracuse University’s Whitman School of Management with dual degrees in Marketing and Finance.

Panel Members:

Natasha Beckley, CMO, Quantum Corp.

As Quantum’s Chief Marketing Officer, Natasha Beckley is responsible for building and strengthening Quantum’s brand, leading the company’s multifaceted marketing strategy, and increasing worldwide demand for Quantum's solutions in both new and existing markets.

Beth Caltagirone, Head of Marketing, StorPool

Beth Caltagirone is Head of Marketing at StorPool Storage.

Gary Lyng, VP Product Marketing, Hitachi Vantara

Gary Lyng is Vice President Products & Solutions at Hitachi Vantara.

Bill Basinas, Sr. Director Product Marketing, Infinidat

Bill Basinas is Senior Director, Product Marketing at Infinidat and has been focused in the storage industry since 1994 when he joined Legato Systems as the first field systems engineer. He was also an early employee at Avamar and spent time at enterprise companies such as EMC and HPE Storage in Global Marketing and Engineering roles.

Sue Ryan, VP Marketing, Frore Systems

Sue Ryan is VP Marketing at Frore Systems.

Molly Presley, SVP Marketing, Hammerspace

Panel Session Description:

The informative and entertaining CMO Panel returns to FMS, with Marketing Officers from Frore Systems, Hammerspace, HItachi Vantara, INFINIDAT, Quantum and StorPool tackle the topic Memory and Storage Solutions Will Be Everywhere but What Are the Changing Customer Requirements and Winning Go-to-Market Strategies

PRO DCTR-103-1: Hyperscale Applications Part 2

Ballroom D, Floor 1

Track: Data Center Applications

Organizer:

Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft

Chairperson:

Marc Hamilton, Principal Storage Hardware Architect, Microsoft

Marc Hamilton has over 20 years of experience in the semiconductor industry. Although he has worked with many different types of memories at the silicon level, his greatest interest was found with the application of those memories into storage devices and storage systems. After architecting and designing solid state storage devices for Micron and Intel for more than a decade, he later transitioned to Microsoft where he focuses on developing innovative storage architectures and pioneering future storage technologies for Azure.

Paper Presenters:

Hyung Kim, Technical Sourcing Manager, SSD/NAND, Meta

Paper Title:

What Hyperscale Cares About

Paper Abstract:

This talk will cover hyperscale's view on storage challenges and needs.

Author Bio:

Hyung is a Technical Sourcing Manager at Meta focused on meeting Meta's storage needs with deep experience in memory.

Raj Ummadisetty, Sr Software Engineer, Netflix

Paper Title:

Decoupling Services from Storage Engines Through Data Abstractions at Netflix

Paper Abstract:

At Netflix, the Data Access Team is innovating data management, decoupling services from storage engines using Data abstractions. The goal of abstraction is to expose a clean, stable interface, tailored to a wide array of use cases. The cornerstone of our approach is a sophisticated capacity planner, which analyzes users' access patterns to output the most suitable storage engine for the specific use case. For Example, Key-Value abstractions can be backed by a multitude of storage engines, including Cassandra, DynamoDB, and in-memory partitioned data using RocksDB SSTables. This decoupling process enables continuous evaluation and modification of storage solutions corresponding to a use case, all executed transparently with zero impact on our customers. Key to this approach is the "dual writes" methodology, enabling early issue detection and prompt rectification, thereby ensuring safe and seamless data migration between storage engines and allowing Netflix to optimize costs. We demonstrate a new standard in data storage and management and show the effectiveness of Data abstraction in enhancing storage efficiency.

Author Bio:

Rajasekhar Ummadisetty is a distinguished software engineer with a deep-seated interest in solving complex problems in distributed systems. He brings a wealth of experience in designing, building, and maintaining software solutions that can scale and perform in distributed environments. His passion for continuous learning and staying abreast of the latest industry trends enables him to consistently drive innovation and efficiency in his work. His expertise extends to data management, where he has made significant contributions to decoupling services from storage engines using data abstractions.

Venkatraghavan Ramesh, Hardware Systems Engineer, Meta

Paper Title:

TestDrive: Diagnostic for accelerated life testing

Paper Abstract:

Presenting ocp-diag-testdrive (under active development, planned deployment in ocp-diag repo in March) which uses ML techniques to extrapolate workloads captured on live production systems to provide more representative stress for SSD/HDD testing, and linux kernel probes to capture failure state.

Author Bio:

Venkat Ramesh is a Hardware Systems Engineer working in Meta's Infrastructure Org. Venkat leads various initiatives on diagnostics and telemetry development for SSDs and AI accelerators, and has led several programs to manage the lifecycle of Meta's database and cache hardware. In his past life, he worked on SMART telemetry software, as well as performance engineering teams at a couple of Flash vendors.

Vidhya Arvind, Staff Engineer, Netflix Inc

Paper Title:

Decoupling Services from Storage Engines Through Data Abstractions at Netflix

Paper Abstract:

Author Bio:

Vidhya Arvind is a Senior Software Engineer for Netflix building abstractions. She is a founding member of Netflix’s data abstraction platform, which supports common patterns including KeyValue, Tree, TimeSeries, Table Metadata, and more. She loves learning, debugging, scaling systems, and solving hard problems. Vidhya currently spends most of her time providing scalable abstractions for thousands of developers at Netflix.

Paper Session Description:

Hyperscale is focused on tackling storage challenges head-on, addressing the needs of massive data management in today's digital landscape. This session will delve into the innovative solutions and strategies that are being implementing to optimize storage efficiency and enhance performance, including using data abstractions to create a clean and stable interface for a variety of use cases, and a diagnostic for accelerated life testing.

PRO DRAM-103-1: Influence of AI on Memory Technology NEW

Ballroom C, Floor 1

Track: DRAM

Organizer:

Ju An, STSM, IBM

Paper Presenters:

Jim Handy, General Director, Objective Analysis

Paper Title:

Is HBM Headed to New Heights, or Is This Just Hype?

Paper Abstract:

AI is taking off like a rocket. The world is both charmed and alarmed by Generative AI and the ability of models like ChatGPT to replicate a lot of processes normally performed by humans. With that, the market for GPUs has exploded, and with it demand for High Bandwidth Memory (HBM) has suddenly seen phenomenal growth. Is this sustainable, or will it fizzle in the near term? Join this session to hear what seasoned analysts Mark Webb and Jim Handy expect for HBM going forward. The session will present not only two different HBM forecasts and cost models, but will also detail the technology and the challenges that it presents for DRAM makers, their customers, and the industry as a whole.

Author Bio:

Bill Gervasi, Principal Systems Architect, Wolley Inc

Paper Title:

CXL Native Memory: Do We Really Need DDR?

Paper Abstract:

CXL memory modules enable memory expansion, enabling larger capacities to support emerging applications such as large language models where the LLMs demand 140GB or more of local capacity. HBM can't enable these large memory capacities, and CXL is a logical method to expand memory, but at significant cost in terms of power consumed and bandwidth wasted. Is DDR doing us any favors, and can we imagine a memory world without DDR? CXL Native Memory proposes to replace the inefficient DDR interface with a CXL direct physical interface that drives memory cores from the CXL FLIT without protocol retranslation. CXL Native Memory reduces memory latency overhead while saving power.

Author Bio:

Mark Webb, Analyst, MKW Ventures

Mark Webb is Principal/Consultant at MKW Ventures Consulting where he provides consulting services in SSDs, NAND, NVM, and semiconductor technology and competitive analysis. With over 25 years experience in semiconductor and system engineering and manufacturing, Mark consults with SSD OEM and ODM companies, memory manufacturers, and investment firms. Before founding MKW Ventures, Mark was Director of Manufacturing for the NVM Solutions Group at Intel, where he was responsible for SSD system and NAND component manufacturing. He also has been Corporate Product Quality and Reliability Manager for IM Flash Technologies, the widely publicized joint venture between Intel and Micron that became an industry leader in NAND technology. Mark is a frequent presenter at Flash Memory Summit and other key venues, and his analysis of technology adoption and product costs are often referenced by investment firms, analysts, technology training firms and major OEMs. He earned a BSEE at California State University, Chico.

Taekwon Jee, Principal Engineer, SK hynix

Paper Title:

A study of device yield optimization through human-AI collaboration

Paper Abstract:

Advanced generative AI technology developments such as LLM are having a significant impact on the entire semiconductor industry. Various semiconductor devices that can compute AI technology faster and more efficiently are emerging, but due to the diversity of designs, securing robustness in the various processes to actually manufacture them is becoming a major obstacle. To solve this problem, we developed a technology that can accurately predict process yield by combining the latest inline monitoring technology and vision machine learning. In this paper, the yield can be accurately predicted through experiments to secure machine learning-based process pattern fidelity in the latest N+2 DRAM node using the EPE (Edge Placement Error)-based all-in-one system, which represents process robustness. As a result, it can be seen that with the help of the latest machine learning and AI technologies, it is possible to lay a strategic foundation for securing extreme yields in various semiconductor processes.

Author Bio:

Taekwon Jee is currently working as a principal engineer at SK hynix since 2018. He is a semiconductor patterning and data analytics expert specializing in co-optimization of unit-module processes such as optical proximity correction, photolithography and dry etching. He is Interested in defect prediction, process optimization and control algorithms based on machine learning approaches and manufacturing domain knowledge. Before he join SK hynix, he has been working for the various sectors of semiconductor industry such as ASML, Samsung, Lam Research, and Intel. He got his PhD in mechanical engineering at University of California, Berkeley.

Paper Session Description:

CXL Native Memory challenges the need for DDR by proposing a more efficient memory interface that directly connects memory cores to the CXL FLIT, reducing latency overhead and power consumption. With applications like large language models demanding over 140GB of local capacity, CXL memory modules offer a solution for memory expansion that HBM cannot match. Meanwhile, the increasing demand for High Bandwidth Memory (HBM) driven by the AI boom raises questions about its sustainability. This session will discuss the future of HBM, its cost models, and the challenges it poses for DRAM makers and the industry as a whole. Advanced AI technology is also revolutionizing semiconductor device yield optimization, with the development of machine learning-based process pattern fidelity to secure extreme yields in various semiconductor processes.

Open SPOS-103-1: CXL Member Implementations NEW

Ballroom A, Floor 1

Track: Sponsored Sessions

Sponsor:

CXL Consortium

Paper Presenters:

Jim Kao, SW Director, Xconn Technologies

Paper Title:

CXL 2.0 Fabric Deployment for a Composable Memory System

Paper Abstract:

Jim Kao will present CXL 2.0 Fabric Deployment for a Composable Memory System as part of the CXL implementations discussion.

Author Bio:

JIm Kao is Software Director at Xconn Technologies and a member of the CXL Consortium.

Sandeep Dattaprasad, Senior Product Manager, Astera Labs

Paper Title:

Importance of Pre-boot Environment for CXL Type 3 Devices

Paper Abstract:

This presentation on the importance of pre-boot environment for CXL Type 3 Devices is part of the CXL implementations session at FMS 2024.

Author Bio:

Sandeep Dattaprasad is a Senior Product Manager at Astera Labs with 15+ years of experience in semiconductor, software diagnostic tools, developing security strategies and firmware development for complex SoC product lines including Compute Express Link products, SAS RAID controllers, SAS expanders and PCIe switches. He is also a contributing member of the CXL Consortium. At Astera Labs, Sandeep’s focus is on driving product strategy for new market segments by translating data center bottlenecks into profitable and competitive hardware and software solutions using CXL technology.

Geof Findley, VP Business Development, Montage Technology

Paper Title:

CXL 2.0 Use Case

Paper Abstract:

Geof will speak on CXL 2.0 Use Case – Using both DDR4 and DDR5 on the same server to allow memory and bandwidth scaling .

Author Bio:

Geof Findley is an award-winning presenter, patent holder and systems engineer with a proven track record of successfully managing multiple aspects of engineering, sales and marketing to ensure successful product launches and ramps. With over three decades of experience, Geof has developed unmatched depth and breadth of expertise across product development, sales, marketing, and channel management. Geof spent over 19 years at Intel Corporation, where he held various roles, including Director of Memory Enabling: Platform Memory Operations, Data Center Group from 2003 to 2018. Prior to Intel, Geof worked in sales and engineering roles in telecommunications for Siemens/ROLM, Altitude Software, and NICE systems. Since March 2018, Geof has served as the World Wide Vice President of Business Development/Sales at Montage Technology, Inc. where he has increased sales 4X and brought on two new product lines in Retimers and CXL along with their award winning memory products. Geof is known for his drive to collaborate with individuals and teams to identify and solve issues. He maintains a large, global network of influencers and decision-makers, contributing to his success in driving business development and sales initiatives.

Paper Session Description:

This session, sponsored by CXL Consortium, will feature presentations from three of its Member companies on their CXL implementations. • Importance of Pre-boot Environment for CXL Type 3 Devices (Astera Labs) • CXL 2.0 Use Case – Using both DDR4 and DDR5 on the same server to allow memory and bandwidth scaling (Montage Technologies) • CXL 2.0 Fabric Deployment for a Composable Memory System (Xconn Technologies)

PRO SSDT-103-1: Technologies for Improving the Endurance & Reliability of SSDs

Ballroom F, Floor 1

Track: SSD Technology

Organizer:

Erich Haratsch, Senior Director Architecture, Marvell

Chairperson:

Mats Oberg, Sr. Director, DSP, Marvell

Mats Oberg is Associate Vice President, Storage DSP and ML Architecture at Marvell. Mats earned his MS in Electrical Engineering from Lund University, Sweden, and his PhD in Electrical Engineering from University of California, San Diego. After receiving his PhD, Mats joined Marvell where he has been leading the development of read channels for perpendicular magnetic recording, two dimensional magnetic recording, and optical recording. He currently leads research and development of signal processing, compute and machine learning for storage products.

Paper Presenters:

Niles Yang, Flashtec Architect, Microchip Technology

Paper Title:

Flexible and Futureproof SSD Controller Archi\tecture for Next Gen NAND Memories

Paper Abstract:

Next generation NAND devices keep proliferating from multiple vendors with unique features and capabilities and corresponding standards. NAND devices that are obsolete or restricted prompts the use of alternative, second source devices to minimize supply chain disruptions and optimize the cost of SSDs. There are emerging needs for the versatile datacenter SSD controllers. Support for newer command sets, sequences and stringent waveform timing of the physical layer are some examples of such rising requirements for the SSD controller. Obviously, it is difficult to create an ASIC in advance of the new technologies that will match specifications that have not yet been developed. This can result in inefficiency, as well as reduced longevity of ASIC development. We will present a modern SSD controller architecture using a software controlled, high speed physical layer that allows us to specify every cycle to match any arbitrary interface waveform. This provides the required flexibility and efficiency to interoperate with the diverse high speed next generation NAND technologies and enable nimbler turnaround of SSDs with newer NAND devices.

Author Bio:

Niles Yang is an architect of the FlashtecTM® NVMe® SSD controller in the data center solutions business unit at Microchip Technology Inc. He has over 20 years of R&D experience in the field of non-volatile memory technology, design and system architecture. His current focus is on the development and optimization of the overall SSD architecture for data center applications. He holds 223 granted U.S. patents, and a Ph.D in semiconductor physics and CMOS process.

Maoruei Li, Project Deputy Manager, Silicon Motion

Paper Title:

Maximizing Cost Efficiency with True 16K LDPC for Advanced 3D NAND

Paper Abstract:

This presentation explores the transition from 4K to True 16K LDPC engines, addressing limitations of current 4K LDPC engines for next-gen NAND. We analyze power consumption and complexity in relation to correction capability, highlighting the need for flexible IU sizes in both 4K and 16K LDPC. Furthermore, we delve into overcoming performance constraints in 4K random reads with 16K LDPC codes. Additionally, we demonstrate how 16K codes offer significant benefits for advanced 3D NAND, particularly QLC, enhancing correction capability while managing power consumption effectively. Finally, we present 16K LDPC as a feasible solution, optimizing correction capability and power efficiency.

Author Bio:

Mao-Ruei Li is a Project Deputy Manager of Storage Research Department II at Silicon Motion. Prior to this role, he focused on a VLSI architecture of SERDES. He received the M.S. and Ph.D. Degrees in electrical engineering from Nation Tsing Hua University. His research in high speed SERDES and error correcting codes, including encoding/decoding algorithms, VLSI architectures. Currently, he is dedicated to developing an efficient VLSI architecture for LDPC codecs tailored for NAND applications.

Vic Ye, Manager, YeeStor Microelectronics

Paper Title:

Dynamic Read Retry Method

Paper Abstract:

As flash storage devices undergo wear and tear through program/erase cycles, they increasingly need more read retries for error correction, which slows down their read operations. The way read-retry methods are designed is crucial for maintaining the speed of these operations. Presently, flash chips use static read retry tables that don’t account for the specific read patterns or error characteristics. Our research involved analyzing various real flash chips to create models that identify the optimal read voltages for each page. With these insights, we've created a custom read retry table for each type of flash memory. This includes a dynamic process for selecting the right read voltages and a fine-tuning method to adjust them accurately. Testing with actual flash chips demonstrates that our approach significantly reduces the need for read retries, cutting the average down to less than 0.003 after 8K program/erase cycles with long-term data retention, compared to over 3 read retries for other current methods at just 3K cycles.

Author Bio:

Vic Ye holds the position of Flash Analysis Team Manager at YeeStor, a company specializing in the development of memory chips and storage controller technology. He and his team have pioneered a suite of analytical techniques for NAND flash memory, with a particular emphasis on innovating characteristics for 3D NAND technology. Previously, Vic served as an SSD Product Manager at SiliconGo and worked as an IC Design Engineer at Huawei. His academic credentials include a Ph.D. in Computer Science from the City University of Hong Kong and a Master's degree in Microelectronics from Tianjing University in China.

Doug Dumitru, CT0, EasyCo LLC dba WildFire Storage

Paper Title:

Maximizing Flash Storage Value with a Host FTL

Paper Abstract:

It has long been understood that NAND Flash performance and endurance is more a function of the logic of the controller than the NAND itself. The FTL (Flash Translation Layer) is the controller layer that maps logical blocks to NAND blocks. This layer is necessary for Flash to act like a standard block device instead of something closer to tape. By off-loading the FTL from the target SSDs to host software, we can better control performance, latency, redundancy, and wear. We will look at several approaches to FTL âoff-loadsâ including host software and co-processors boards. Using simulators and an FTL visualization, we can see how RAID, free space, over-provisioning, and compression impact performance and wear. In the end, users can optimize performance, redundancy, and operating costs without having to compromise one against the other.

Author Bio:

Doug Dumitru is CTO of Wildfire Storage. Doug has spent several decades improving the i/o performance and durability of Flash SSDs and Hard Disks through the creation and improvement of software based Flash Translation Layers.

Paper Session Description:

This session discusses technologies for improving the Endurance and reliability of SSDs, Flash storage devices require more read retries for error correction as they undergo wear and tear from program/erase cycles, slowing down operations. We will discuss various methods to analyze real flash chips, improve correction capability for advanced 3D NAND, and how to achieve better performance control and wear management, ensure longevity, and increase efficiency.

PRO UCIC-103-1: UCIe and Chiplet Ecosystem - a Panel NEW

Ballroom G, Floor 1

Track: UCIe and Chiplets

Organizer + Chairperson:

Brian Rea, Technology Initiative and Ecosystem Enablement Manager, Intel

Panel Members:

Mahmeet Walia, Executive Director of Product Management for Mixed-signal PHY IP, Synopsys

Manmeet Walia is the executive director of product management for mixed-signal PHY IP for the Synopsys Solutions Group. He brings more than 20 years of experience in product marketing, product management, and system engineering covering ASSP, ASIC, and IP products for a broad range of applications. Manmeet holds an M.S. in electrical engineering from the University of Toledo and an MBA from San Diego State University.

LK Bhupathi, VP of Products, Strategy and Ecosystem, Ayar Labs

LK joins Ayar Labs following twenty years with Marvell Semiconductor in a variety of design, technical marketing, and product roles, including a position as Vice President, Product Management / Marketing at high performance networking company Aquantia (acquired by Marvell), as well as driving CXL and Ethernet NIC product strategy and roadmap for Marvell’s next-generation cloud and enterprise datacenter applications. LK also served as the President and Marketing Chair for the NBASE-T alliance (since merged with the Ethernet Alliance). He holds an MBA from the University of California, Berkeley.

Jerome Glisse, UCIe Management & Security/Software Engineer, Google

Jerome Glisse has worked extensively throughout his career on PCI, PCIe, CXL and other interconnect technologies and standards. Open source enthusiast, has been involved in various Open Source Projects. He is the Co-Chair of the UCIe Manageability and Security Work Group, and at Google focusses on device security and interconnect.

Maulik Shah, Director of Marketing, Foundry Services, Intel

Mr. Shah is an alumni of the Stanford Graduate School of Business (LEAD program) and also holds a Masters degree in Engineering (Computer Science) from the University of Massachusetts. He also holds a Bachelors degree in Engineering (Chemical Engineering) from the University of Mumbai.

Panel Session Description:

As the Universal Chiplet Interconnect Express (UCIe) emerges as a pivotal standard in this revolution, a distinguished panel of senior leaders from Intel, Synopsys, Ayar Labs, and Google will convene to explore the latest advancements and collaborative efforts shaping the chiplet ecosystem.

05:45 PM to 07:00 PM

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Open FMS 2024 Best of Show Awards

FMS Theatre, Floor 2

Track: FMS 2024 Keynotes

Organizer + Moderator:

Jay Kramer, President, Network Storage Advisors

Jay Kramer, founder at Network Storage Advisors, is a dynamic results-oriented strategic marketing leader and creator of world-class marketing teams with a proven track record of building company brand and demand generation initiatives that accelerate sales. He has over 25 years of repeated marketing success with industry leading Fortune 500 companies (Unisys, Seagate) as well as early and late stage emerging companies. His industry knowledge spans cloud, virtualization, software defined storage (SDS), hyper convergence, data protection, SAN, NAS, and object storage solutions plus network storage technologies including Fibre Channel, iSCSI, VTL, dedup, backup, and replication. He has served as board member to technology industry associations and event development/professional conference companies.

Special Presentation Description:

The FMS24 Best of Show Awards recognize high-performance memory and storage innovations in eight distinct categories. These industry-recognized awards give winners the opportunity to effectively build their brand and image as an innovative leader in the marketplacThere are eight distinct award categories which address the wide range of high-performance memory and storage innovations in the market.

08:30 AM to 09:35 AM

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Open ASIA-201-1: Asia Memory and Storage Markets Part 1

Ballroom F, Floor 1

Track: Asia Memory and Storage Markets

Chairperson:

Avery Lu, Partner & Head of Business Development / 2015-2016 Chair, Aventurine Capital Group / IEEE Consumer Technology Society, San Francisco Bay

As Partner & Head of Business Development, Investments for Aventurine Capital Group, LLC, Avery Lu leverages his experience as a high-tech business executive in both large corporations and startups. He works directly with partners in venture capital, universities and startups as well as scientists to identify high value intellectual property. Avery has previously co-founded 3 startups; Palo Alto Scientific (AI sports analytics/wearables), ActionSpot Startup Studio (venture studio & co-working space) and WBGlobalSemi (SiC power management solutions). Early in his career, he held various senior level roles in Business Development, Segment Marketing, Product Marketing, Global Account Management and Field Applications Engineering at NXP Semiconductor, Infineon Technologies, Toshiba Semiconductor, Winbond Electronics, American Microsystems Incorporated, Cypress Semiconductor, Viewlogic Systems and Xilinx. Avery is a Senior Member of the IEEE, former chair of the IEEE Consumer Electronics Society and executive committee member of the IEEE Startup SIG, in Silicon Valley. He has served on the Board of Directors of CASPA (Chinese American Semiconductor Professional Association) since 2011, and is currently on the Advisory Board of the Center for Innovation and Entrepreneurship at his alma mater, Santa Clara University, where he earned his B.S. in Electrical Engineering.

Organizer:

Janet Liu, Project Manager, Sage Micro

Janet Liu is a project manager at Sage Microelectronics.

Paper Presenters:

Bryan Ao, Research Manager, TrendForce Corp.

Paper Title:

NAND market update- projection into 2025

Paper Abstract:

The NAND market has recently recovered from the server oversupply of 2023. TrendForce will provide a retrospective analysis of the NAND industry's capex and operating margin records over the past decade. We'll examine supply and demand dynamics to forecast future NAND price responses to market pressures. This presentation offers a strategic roadmap of NAND supply/demand, sufficiency ratios, and ASP trends. It will also explore major supplier strategies, capacity adjustments, and growth projections for the 2025 NAND market and beyond, outlining strategic implications for future trends.

Author Bio:

Analyst in NAND for over 5 years. Before I became an analyst, I was in sales across foundry, SSD controller and eletronic components for tier 1 OE/ODM factory in Asia

Alex Xie, Engineering Director, Suzhou OKN Technology Co., LTD.

Paper Title:

Testing technology energize high-quality development of the storage industry

Paper Abstract:

With high grow of semiconductor storage products, testing technology becomes one of the key factors to ensure products' quality and cost. OKN's storage test systems are designed for SSD and DDR,