2024 Program at a Glance
01:00 PM to 02:45 PM
PRO
PDSA1: Quantum Memory: Superconducting Qubits & Quantum Computer HW Design - Pt 1
Room 209, Floor 2
Track:
Professional Development Series (Pre-Conference)
Organizer + Presenter:
Pre-Con Seminar Description:
WeiTi Liu, General Partner, Quantum Technology
Wei-Ti Liu is a General Partner of Quantum Technology, LLC. He was previously Co-Founder/GM/VP Engineering at PLX Technology, a maker of PCI-based chipsets. At PLX, he oversaw operations, directly managed the engineering group, and managed the foundry interface. He was President/CEO of NetChip Technology (now Broadcom Inc), a USB controller maker, and a security device manufacturer. Wei-Ti has extensive experience in ASIC VLSI chip designs, and has also been a design engineer for IBM, AMD, and Intel. He earned an MSEE from the City College of New York and a BSEE from the National Taiwan University. He has presented at several Flash Memory Summits and holds twelve US patents in that area. Areas of Interest includes: Investing Quantum Technology, and Advising on Semiconductor related technology projects, MRAM design, 3D Die stacking, and Heterogeneous Integration Architecture Design. Quantum Computing Workshop Presenter, “The Fundamental of Quantum Computation and Quantum Information for Engineer— A Practical Approach”. Grove School of Engineering, The City College of The City University of New York. Tutorial Course Agenda: 1. Introduction to Quantum Computing and Application 2. Review of Linear Algebra—Basic 3. Qubits, Operators and Measurement 4. Quantum Gates 5. Complexity Theory—Introduction 6. Quantum Communication 7. Quantum Computing with IBM Quantum Experience (Hands-on experience) 8. Quantum Algorithms 9. Quantum Error Correction.
Unlike classical memory, quantum computing's "no-clone theorem" limited Quantum memory using classical memory's read/write operations; when we access or measure qubits, their information is inevitably destroyed. Therefore, we must rely on quantum operations, precisely entanglement, to access qubits. As quantum computers advance, they demand many digital and analog circuits to execute control and measurement functions. The proliferation of qubits in an array has led to a significant increase in control and measurement signals. This signal surge has created a scalability issue for quantum computers, posing a challenge in their design and operation. The number of digital and analog cryogenic CMOS circuits has also escalated, leading to power and scalability issues, necessitating innovative solutions for quantum memory hardware design. Quantum memory is essential to quantum computing applications like finance, quantum chemistry, cryptography, and scientific research. Quantum networks enable secure, faster, and longer-distance transfer of quantum information. Moreover, they require quantum repeaters and quantum memory. This Professional Development Session aims to motivate experienced hardware and software engineers to explore the quantum field. We are exploring the advantages of quantum computing in finance, cryptography, chemistry, and optimization. Furthermore, quantum networks enable faster, longer-distance quantum information transfer with a secure network. Quantum memory is a significant element of quantum computing, and we are gaining knowledge of quantum hardware design using superconducting qubits. Part 1: • Gain knowledge of quantum computing hardware elements and understand the technical knowledge needed to design quantum computers with quantum process units (QPU) interfaces with quantum control and measurements. • Gain the engineering knowledge for implementing quantum vs classical algorithms. • Gain knowledge of engineering requirements for quantum computing and understand the quantum advantage over classical computers. • We summarized the quantum computing hardware's requirements for quantum memory.
PRO
PDSB1: CXL for Disaggregated Memory & Accelerators in Data Ctrs - Pt 1
Room 203, Floor 2
Track:
Professional Development Series (Pre-Conference)
Organizer + Moderator:
Pankaj Mehra, Founder, Elephance
Pankaj Mehra is President and CEO of Elephance Memory. A contributor to InfiniBand 1.0 spec and an inventor of the first RDMA persistent memory devices and filesystems, Pankaj is a systems and software practitioner who conducts his research at the intersection of infrastructure and intelligence. He is a co-author/co-editor/co-inventor on 3 books, and over 100 papers and patents, and a builder of systems that have won recognition from NASA, Sandia National Labs, and Samsung Electronics, among others. He was a VP of Storage Pathfinding at Samsung, Senior Fellow and VP at SanDisk and Western Digital, WW CTO of Fusion-io, and Distinguished Technologist at HP Labs. Pankaj has held faculty positions at IIT Delhi and UC Santa Cruz.
Speakers:
Pre-Con Seminar Description:
Samir Rajadnya, Principal Architect, Microsoft
Samir Rajadnya is a Principal Architect in Microsoft Azure Hardware Architecture team where he works on future memory systems. Prior to Microsoft, Samir spent many years innovating in memory, storage, and networking. Samir was key architect to productize 3DXP technology at Micron, architect, and designer at disruptive storage startup DSSD. He was an SOC architect and designer at Juniper Networks, Netronome and Intel. Samir has served as part of multiple industry standards bodies throughout his career, including CXL and CCIX. Samir received his master’s in electrical engineering from Indian Institute of Technology Bombay.
Manoj Wadekar, Hardware System Technologist, Meta
Manoj is the HW technologist and Mr. "Storage Guy" working at Meta. He is transforming hyper-scale infrastructure to drive performance and efficiency (proven for "ebay servers". He loves Technology Research and Innovation, Product and Technology Strategy, and defining Product Roadmaps/Business cases. He constantly drives Cross-industry initiatives and collaborations.
Siamak Tavallaei, Sr. Principal Engineer, Samsung
Siamak Tavallaei is Sr. Principal Engineer at Samsung. He joined the CXL effort as a founding member of the CXL Consortium and co-chair of the Technical Task Force (TTF) in 2019 to develop the CXL 2.0 specification. He has served on the CXL Board of Directors and as the CXL President. In 2016, he joined Open Compute Project (OCP) as a co-lead of Server Project. He later served as the Incubation Committee Representative for the Server Project and Steering Committee where he drives open-sourced modular design concepts for integrated hardware/software solutions. Previously, he has served as Distinguished Technologist at HP, Senior Principal Architect at Microsoft Azure, and Chief Systems Architect at Google.
The motivation for disaggregating memory is rooted in a desire to support and promote vast in-memory computing systems but without the issues of stranding and up-front provisioning. The speakers in this session will systematically comprehensively cover the topic of memory disaggregation leveraging the CXL standard from a software and hardware perspective, highlighting both challenges and opportunities. We will pay close attention to characteristics and use of memory at a distance. We conclude with our projections about the future of memory attachment in data centers. Topics: - CXL 3 and an update on standards covering P2P - Composable Memory Systems and OpenCompute Project - AI roadmap through 2030, the AI flywheel and data, and specific projections regarding memory and storage needs of AI - An updated analysis of memory expansion for AI, Database, and Virtual Machine workloads - Computational Memory and Storage Programming - Updated findings from architecture and operating systems for disaggregated memory
PRO
PDSC1: DRAM in an Increasingly Diverse Platform
Room 212, Floor 2
Track:
Professional Development Series (Pre-Conference)
Organizer + Presenter:
Pre-Con Seminar Description:
Bill Gervasi, Principal Systems Architect, Wolley Inc
Mr. Gervasi has over 45 years of experience in high speed memory subsystem definition, design, and product development. Career highlights include 19 years at Intel where he was systems hardware designer, software designer, and strategic accounts manager. Mr. Gervasi became a memory specialist for companies including S3, Transmeta, Netlist, SimpleTech, and Nantero, and is now Principal Systems Architect for Wolley, developing CXL based memory solutions. Mr. Gervasi been involved in the definition of Double Data Rate SDRAM since its earliest inception. He has served on the JEDEC Board of Directors and chaired committees for DRAM parametrics and memory modules during the development of DDR1 through DDR6. He is currently the chairman of the JEDEC Alternative Memory committee. He received the JEDEC Technical Excellence award, their highest honor, in 2020.
Long gone are the days where DRAM and storage were the only two options for computer architectures. Chiplets, fabrics, and switching tiers have all entered the equation, and hybrids of memory and storage contribute to a top to bottom rethinking of data flow. Artificial intelligence as a dominant emerging technology is also affecting the equation where memory capacity requirements force a blending of multiple memory approaches to feed the beast. These new requirements are also driving an energy crisis, so total cost of ownership analyses are required to make good tradeoffs. Takeaways from this session: • Understand the new memory tiers including HBM and CXL • Analyze the new hybrid memory concepts such as memory semantic storage • Impact of artificial intelligence and new automotive architectures • What trends are on the mobile client and edge fronts • Why data centers waste so much energy and what can be done about it
PRO
PDSD1: Advanced HDD Technology for the Data Center
Room 204, Floor 2
Track:
Professional Development Series (Pre-Conference)
Organizer + Presenter:
Mohamad El-Batal, Sr. Director of Architecture, Seagate
Mohamad is on the Board of Directors of the Non-Volatile Memory Express (NVMe), Flash Memory Summit (FMS), and Open Compute Project (OCP). Mohamad is currently the chair of the NVMe-HDD working group and driving its requirements specification. He is also the chair of the OCP PCIe External Connectivity Workstream enabling PCIe to evolve with NVMe and Computer Express Link (CXL) into the Ultra-Low-Latency of optical fabric of choice. He was the author and chair of the Storage Bridge Bay (SBB) specification and was on the SBB board of directors for multiple years. Mohamad participated technically and influenced various industry groups including the FC, SAS, NVMe, CXL and GenZ consortiums. In his career, Mohamad worked at leading enterprise storage technology and cloud provider companies, including Tandem, EMC, Mylex, IBM, LSI, Engenio, NetApp and now Seagate. Mohamad has 30+ year history of enterprise and cloud storage architecture knowledge, experience, and innovation. Mohamad holds 50+ issued and 20+ pending patents, covering: High-Availability/Resiliency Storage and Memory solutions, SSD controller and Systems architecture focus areas.
Speakers:
Pre-Con Seminar Description:
Praveen Viraraghavan, Technologist, Seagate
Praveen Viraraghavan is the Technologist of the Product Line Management organization. In his role at Seagate, Praveen is given the opportunity to collaborate with other leaders to shape the portfolio across all parts of the Seagate product and research ecosystem. Praveen works closely with all customers to help align their storage strategy to Seagate’s product and technology roadmap. Praveen has a proven record owning hardware and software architecture strategy working with multiple levels of technical and corporate leadership. Praveen has a knowledge of the ecosystem related to data management, which allows advocacy for the customer’s requirements while still prioritizing the company’s business and technical options. Praveen holds a BS degree in Electrical Engineering and did some graduate work on VLSI design in 1997 from Purdue University at West Lafayette. During his storage career Praveen has worked from the lowest embedded layers, silicon development, product architecture and development up through to the software layer. Praveen led the architecture of many new first-pass success silicon developments and new HDD and SSD product lines at leading storage companies serving cloud and OEM customers. Praveen transitioned to a startup where is helped redefine the storage stack used in the cutting edge S3 on premise object storage software solution, the company was later acquired. Praveen has been a contributor to many industry standard bodies. In his career, Praveen worked at leading storage technology and cloud companies, including Western Digital, LSI Logic, Cleversafe (acquired by IBM) and now Seagate. Praveen has 25+ year history of enterprise and cloud storage architecture knowledge, experience, and innovation. Praveen holds 50+ issued and 25+ pending patents, covering: Silicon Control and Datapath, Command Handling, Distributed Object Storage, Filesystems, and Memory solutions. Praveen has won innovation awards from LSI and IBM and was an IBM Master Inventor. Praveen currently serves on 4 Seagate patent review boards in support of their continued innovation.
Greater than 88% of today's cloud storage is stored on Hard Disk Drive (HDD) media, and this majority percentage is expected to remain true for the near future. These storage track sessions will discuss why this is the case and will go deep into the incredibly complex but commoditized and simplified technologies that enabled this fact. We will present on the substantial technical breakthroughs that have enabled HDDs to continue their capacity growth rate, and then explain the difference between the major formatting technologies, CMR vs. SMR, then discuss in detail the PMR technical capabilities and limitations and then dive into HAMR media and recording technologies. We plan to discuss some of the myths surrounding HDD Near-Line storage capabilities and limitations and explain the justifications behind some of the current and future engineering innovations that enable HDDs to maintain their Total Cost of Ownership (TCO) supremacy over other leading storage solutions. Our intent is to inform and empower the audience of these sessions with key information and strategies that would help them understand the difference between the various available HDD technologies and enable them to best pick the right storage for the right usage model to optimize their storage TCO.
03:15 PM to 05:00 PM
PRO
PDSA2: Quantum Memory: Superconducting Qubits & Quantum Computer HW Design - Pt 2
Room 209, Floor 2
Track:
Professional Development Series (Pre-Conference)
Organizer + Presenter:
Pre-Con Seminar Description:
Wei Lu, General Partner, Quantum Technology
Bio Not Available
Unlike classical memory, quantum computing's "no-clone theorem" limited Quantum memory using classical memory's read/write operations; when we access or measure qubits, their information is inevitably destroyed. Therefore, we must rely on quantum operations, precisely entanglement, to access qubits. As quantum computers advance, they demand many digital and analog circuits to execute control and measurement functions. The proliferation of qubits in an array has led to a significant increase in control and measurement signals. This signal surge has created a scalability issue for quantum computers, posing a challenge in their design and operation. The number of digital and analog cryogenic CMOS circuits has also escalated, leading to power and scalability issues, necessitating innovative solutions for quantum memory hardware design. Quantum memory is essential to quantum computing applications like finance, quantum chemistry, cryptography, and scientific research. Quantum networks enable secure, faster, and longer-distance transfer of quantum information. Moreover, they require quantum repeaters and quantum memory. This Professional Development Session aims to motivate experienced hardware and software engineers to explore the quantum field. We are exploring the advantages of quantum computing in finance, cryptography, chemistry, and optimization. Furthermore, quantum networks enable faster, longer-distance quantum information transfer with a secure network. Quantum memory is a significant element of quantum computing, and we are gaining knowledge of quantum hardware design using superconducting qubits. Part 2: • Understanding the quantum memory hardware design's challenges and qubit requirements • Understanding the critical difference between quantum memory vs classical memory array, Gaining knowledge of engineering requirements for quantum memory design • The hardware of a quantum computer-- system partition based on heat load • We summarize the technology requirements for quantum memory and quantum computers to scale up for sizeable quantum computing systems.
PRO
PDSB2: CXL for Disaggregated Memory & Accelerators in Data Ctrs - Pt 2
Room 203, Floor 2
Track:
Professional Development Series (Pre-Conference)
Organizer + Chairperson:
Pankaj Mehra, Founder, Elephance
Pankaj Mehra is President and CEO of Elephance Memory. A contributor to InfiniBand 1.0 spec and an inventor of the first RDMA persistent memory devices and filesystems, Pankaj is a systems and software practitioner who conducts his research at the intersection of infrastructure and intelligence. He is a co-author/co-editor/co-inventor on 3 books, and over 100 papers and patents, and a builder of systems that have won recognition from NASA, Sandia National Labs, and Samsung Electronics, among others. He was a VP of Storage Pathfinding at Samsung, Senior Fellow and VP at SanDisk and Western Digital, WW CTO of Fusion-io, and Distinguished Technologist at HP Labs. Pankaj has held faculty positions at IIT Delhi and UC Santa Cruz.
Speakers:
Pre-Con Seminar Description:
Siamak Tavallaei, Sr. Principal Engineer, Samsung
Siamak Tavallaei is Sr. Principal Engineer at Samsung. He joined the CXL effort as a founding member of the CXL Consortium and co-chair of the Technical Task Force (TTF) in 2019 to develop the CXL 2.0 specification. He has served on the CXL Board of Directors and as the CXL President. In 2016, he joined Open Compute Project (OCP) as a co-lead of Server Project. He later served as the Incubation Committee Representative for the Server Project and Steering Committee where he drives open-sourced modular design concepts for integrated hardware/software solutions. Previously, he has served as Distinguished Technologist at HP, Senior Principal Architect at Microsoft Azure, and Chief Systems Architect at Google.
Samir Rajadnya, Principal Architect, Microsoft
Samir Rajadnya is Cloud Infrastructure, and Systems architect at Microsoft bridging the gap between computing and memory/storage. He is passionate about innovating in cloud infrastructure optimizations. Vertical integration between applications, software, systems, and silicon can bring tremendous benefits in large-scale cloud environments. He has led/worked on systems and chips (FPGAs and ASICs) from concept to silicon with several first pass silicon successes.
Manoj Wadekar, Hardware System Technologist, Meta
Manoj Wadekar is a Hardware Systems Technologist driving storage and memory technology and roadmaps at Meta. Manoj has been designing and building servers, storage, and network solutions for over 30 years. He is leading the Composable Memory Systems group in OCP. Manoj has evangelized Memory and Storage Disaggregation, NVMe over Fabric, Lossless Ethernet (DCB/CEE) in industry conferences. Before joining Meta, he held engineering positions at eBay, QLogic and Intel.
The motivation for disaggregating memory is rooted in a desire to support and promote vast in-memory computing systems but without the issues of stranding and up-front provisioning. The speakers in this session will systematically comprehensively cover the topic of memory disaggregation leveraging the CXL standard from a software and hardware perspective, highlighting both challenges and opportunities. We will pay close attention to characteristics and use of memory at a distance. We conclude with our projections about the future of memory attachment in data centers. Topics: - CXL 3 and an update on standards covering P2P - Composable Memory Systems and OpenCompute Project - AI roadmap through 2030, the AI flywheel and data, and specific projections regarding memory and storage needs of AI - An updated analysis of memory expansion for AI, Database, and Virtual Machine workloads - Computational Memory and Storage Programming - Updated findings from architecture and operating systems for disaggregated memory
PRO
PDSC2: Introduction to High Bandwidth Memory (HBM)
Room 212, Floor 2
Track:
Professional Development Series (Pre-Conference)
Organizer + Presenter:
Pre-Con Seminar Description:
Marc Greenberg, Principal Consultant and CEO, Marc Greenberg Consulting, LLC
Marc Greenberg is an independent consultant in memory, semiconductor and IP. Marc currently serves as VP of Product for Cassia.ai, an AI IP company, as vice-chair of an undisclosed task group at JEDEC, and as advisor to several other companies. Marc was responsible for product management of HBM and other memory and storage IP products at Denali, Cadence and Synopsys for 20 years out of a 30-year career in semiconductor and IP. Marc has a master's degree in Electronics from the University of Edinburgh in Scotland.
In this Professional Development Series session, you'll learn about key aspects of High Bandwidth Memory (HBM): What is HBM, a short history of HBM, why is HBM important right now, how Large Language Models (LLMs) and Generative AI are driving demand for HBM technology, comparison of HBM with other popular memory types (DDR, LPDDR and GDDR), a high level view of HBM architecture, PCB and package requirements to implement chips deploying HBM, a view of the market for HBM and the chips that use it, and a review of public information on the future development of high bandwidth memories.
PRO
PDSD2: Optimizing HDD Performance in the Generative AI Data Center
Room 204, Floor 2
Track:
Professional Development Series (Pre-Conference)
Organizer + Presenter:
Mohamad El-Batal, Sr. Director of Architecture, Seagate
Mohamad is on the Board of Directors of the Non-Volatile Memory Express (NVMe), Flash Memory Summit (FMS), and Open Compute Project (OCP). Mohamad is currently the chair of the NVMe-HDD working group and driving its requirements specification. He is also the chair of the OCP PCIe External Connectivity Workstream enabling PCIe to evolve with NVMe and Computer Express Link (CXL) into the Ultra-Low-Latency of optical fabric of choice. He was the author and chair of the Storage Bridge Bay (SBB) specification and was on the SBB board of directors for multiple years. Mohamad participated technically and influenced various industry groups including the FC, SAS, NVMe, CXL and GenZ consortiums. In his career, Mohamad worked at leading enterprise storage technology and cloud provider companies, including Tandem, EMC, Mylex, IBM, LSI, Engenio, NetApp and now Seagate. Mohamad has 30+ year history of enterprise and cloud storage architecture knowledge, experience, and innovation. Mohamad holds 50+ issued and 20+ pending patents, covering: High-Availability/Resiliency Storage and Memory solutions, SSD controller and Systems architecture focus areas.
Speakers:
Pre-Con Seminar Description:
Praveen Viraraghavan, Technologist, Seagate
Praveen Viraraghavan is the Technologist of the Product Line Management organization. In his role at Seagate, Praveen is given the opportunity to collaborate with other leaders to shape the portfolio across all parts of the Seagate product and research ecosystem. Praveen works closely with all customers to help align their storage strategy to Seagate’s product and technology roadmap. Praveen has a proven record owning hardware and software architecture strategy working with multiple levels of technical and corporate leadership. Praveen has a knowledge of the ecosystem related to data management, which allows advocacy for the customer’s requirements while still prioritizing the company’s business and technical options. Praveen holds a BS degree in Electrical Engineering and did some graduate work on VLSI design in 1997 from Purdue University at West Lafayette. During his storage career Praveen has worked from the lowest embedded layers, silicon development, product architecture and development up through to the software layer. Praveen led the architecture of many new first-pass success silicon developments and new HDD and SSD product lines at leading storage companies serving cloud and OEM customers. Praveen transitioned to a startup where is helped redefine the storage stack used in the cutting edge S3 on premise object storage software solution, the company was later acquired. Praveen has been a contributor to many industry standard bodies. In his career, Praveen worked at leading storage technology and cloud companies, including Western Digital, LSI Logic, Cleversafe (acquired by IBM) and now Seagate. Praveen has 25+ year history of enterprise and cloud storage architecture knowledge, experience, and innovation. Praveen holds 50+ issued and 25+ pending patents, covering: Silicon Control and Datapath, Command Handling, Distributed Object Storage, Filesystems, and Memory solutions. Praveen has won innovation awards from LSI and IBM and was an IBM Master Inventor. Praveen currently serves on 4 Seagate patent review boards in support of their continued innovation.
Citigroup inc. analysts quote "Enterprise data is expected to continue to grow at over 40% CAGR as AI becomes an incremental driver for data creation, storage, and data management" Today's AI ecosystem require fundamental shifts in the requirements of every datacenter infrastructure component. The predominant AI infrastructure strategy tends to currently focus on the most drastically impactful infrastructure components, as in GPUs, CPUs and Memory. Unfortunately, this leaves a major gap in the detailed understanding of the various AI Storage Infrastructure usage models with regards to the various TCO optimized storage tiers and their requirements from a Capacity, Workloads and Performance.