Program at a Glance

01:00 PM to 02:45 PM
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PRO PDSA1: Quantum Memory: Superconducting Qubits & Quantum Computer HW Design - Pt 1
Track: Professional Development Series (Pre-Conference)
Organizer + Presenter:
WeiTi Liu, General Partner, Quantum Technology
Session Description:
Unlike classical memory, quantum computing's "no-clone theorem" limited Quantum memory using classical memory's read/write operations; when we access or measure qubits, their information is inevitably destroyed. Therefore, we must rely on quantum operations, precisely entanglement, to access qubits. As quantum computers advance, they demand many digital and analog circuits to execute control and measurement functions. The proliferation of qubits in an array has led to a significant increase in control and measurement signals. This signal surge has created a scalability issue for quantum computers, posing a challenge in their design and operation. The number of digital and analog cryogenic CMOS circuits has also escalated, leading to power and scalability issues, necessitating innovative solutions for quantum memory hardware design. Quantum memory is essential to quantum computing applications like finance, quantum chemistry, cryptography, and scientific research. Quantum networks enable secure, faster, and longer-distance transfer of quantum information. Moreover, they require quantum repeaters and quantum memory. This Professional Development Session aims to motivate experienced hardware and software engineers to explore the quantum field. We are exploring the advantages of quantum computing in finance, cryptography, chemistry, and optimization. Furthermore, quantum networks enable faster, longer-distance quantum information transfer with a secure network. Quantum memory is a significant element of quantum computing, and we are gaining knowledge of quantum hardware design using superconducting qubits. Part 1: • Gain knowledge of quantum computing hardware elements and understand the technical knowledge needed to design quantum computers with quantum process units (QPU) interfaces with quantum control and measurements. • Gain the engineering knowledge for implementing quantum vs classical algorithms. • Gain knowledge of engineering requirements for quantum computing and understand the quantum advantage over classical computers. • We summarized the quantum computing hardware's requirements for quantum memory.
About the Organizer + Presenter:
Wei-Ti Liu is a General Partner of Quantum Technology, LLC. He was previously Co-Founder/GM/VP Engineering at PLX Technology, a maker of PCI-based chipsets. At PLX, he oversaw operations, directly managed the engineering group, and managed the foundry interface. He was President/CEO of NetChip Technology (now Broadcom Inc), a USB controller maker, and a security device manufacturer. Wei-Ti has extensive experience in ASIC VLSI chip designs, and has also been a design engineer for IBM, AMD, and Intel. He earned an MSEE from the City College of New York and a BSEE from the National Taiwan University. He has presented at several Flash Memory Summits and holds twelve US patents in that area. Areas of Interest includes: Investing Quantum Technology, and Advising on Semiconductor related technology projects, MRAM design, 3D Die stacking, and Heterogeneous Integration Architecture Design. Quantum Computing Workshop Presenter, “The Fundamental of Quantum Computation and Quantum Information for Engineer— A Practical Approach”. Grove School of Engineering, The City College of The City University of New York. Tutorial Course Agenda: 1. Introduction to Quantum Computing and Application 2. Review of Linear Algebra—Basic 3. Qubits, Operators and Measurement 4. Quantum Gates 5. Complexity Theory—Introduction 6. Quantum Communication 7. Quantum Computing with IBM Quantum Experience (Hands-on experience) 8. Quantum Algorithms 9. Quantum Error Correction.
PRO PDSB1: CXL for Disaggregated Memory & Accelerators in Data Ctrs - Pt 1
Track: Professional Development Series (Pre-Conference)
Organizer + Moderator:
Dr. Pankaj Mehra, Founder, Elephance
Speakers:
  • Samir Rajadnya, Principal Architect, Microsoft
  • Manoj Wadekar, Hardware System Technologist, Meta
  • Siamak Tavallaei, CXL™ Consortium President, CXL Consortium
Session Description:
The motivation for disaggregating memory is rooted in a desire to support and promote vast in-memory computing systems but without the issues of stranding and up-front provisioning. The speakers in this session will systematically comprehensively cover the topic of memory disaggregation leveraging the CXL standard from a software and hardware perspective, highlighting both challenges and opportunities. We will pay close attention to characteristics and use of memory at a distance. We conclude with our projections about the future of memory attachment in data centers. Topics: - CXL 3 and an update on standards covering P2P - Composable Memory Systems and OpenCompute Project - AI roadmap through 2030, the AI flywheel and data, and specific projections regarding memory and storage needs of AI - An updated analysis of memory expansion for AI, Database, and Virtual Machine workloads - Computational Memory and Storage Programming - Updated findings from architecture and operating systems for disaggregated memory
About the Organizer + Moderator:
Pankaj Mehra is President and CEO of Elephance Memory. A contributor to InfiniBand 1.0 spec and an inventor of the first RDMA persistent memory devices and filesystems, Pankaj is a systems and software practitioner who conducts his research at the intersection of infrastructure and intelligence. He is a co-author/co-editor/co-inventor on 3 books, and over 100 papers and patents, and a builder of systems that have won recognition from NASA, Sandia National Labs, and Samsung Electronics, among others. He was a VP of Storage Pathfinding at Samsung, Senior Fellow and VP at SanDisk and Western Digital, WW CTO of Fusion-io, and Distinguished Technologist at HP Labs. Pankaj has held faculty positions at IIT Delhi and UC Santa Cruz.
PRO PDSC1: DRAM in an Increasingly Diverse Platform
Track: Professional Development Series (Pre-Conference)
Session Description:
Long gone are the days where DRAM and storage were the only two options for computer architectures. Chiplets, fabrics, and switching tiers have all entered the equation, and hybrids of memory and storage contribute to a top to bottom rethinking of data flow. Artificial intelligence as a dominant emerging technology is also affecting the equation where memory capacity requirements force a blending of multiple memory approaches to feed the beast. These new requirements are also driving an energy crisis, so total cost of ownership analyses are required to make good tradeoffs. Takeaways from this session: • Understand the new memory tiers including HBM and CXL • Analyze the new hybrid memory concepts such as memory semantic storage • Impact of artificial intelligence and new automotive architectures • What trends are on the mobile client and edge fronts • Why data centers waste so much energy and what can be done about it
PRO PDSD1: Advanced HDD Technology for the Data Center
Track: Professional Development Series (Pre-Conference)
Organizer + Presenter:
Mohamad El-Batal, Sr. Director of Architecture, Seagate
Speakers:
  • Praveen Viraraghavan, Technologist, Seagate
Session Description:
Greater than 88% of today's cloud storage is stored on Hard Disk Drive (HDD) media, and this majority percentage is expected to remain true for the near future. These storage track sessions will discuss why this is the case and will go deep into the incredibly complex but commoditized and simplified technologies that enabled this fact. We will present on the substantial technical breakthroughs that have enabled HDDs to continue their capacity growth rate, and then explain the difference between the major formatting technologies, CMR vs. SMR, then discuss in detail the PMR technical capabilities and limitations and then dive into HAMR media and recording technologies. We plan to discuss some of the myths surrounding HDD Near-Line storage capabilities and limitations and explain the justifications behind some of the current and future engineering innovations that enable HDDs to maintain their Total Cost of Ownership (TCO) supremacy over other leading storage solutions. Our intent is to inform and empower the audience of these sessions with key information and strategies that would help them understand the difference between the various available HDD technologies and enable them to best pick the right storage for the right usage model to optimize their storage TCO.
About the Organizer + Presenter:
Mohamad is on the Board of Directors of the Non-Volatile Memory Express (NVMe), Flash Memory Summit (FMS), and Open Compute Project (OCP). Mohamad is currently the chair of the NVMe-HDD working group and driving its requirements specification. He is also the chair of the OCP PCIe External Connectivity Workstream enabling PCIe to evolve with NVMe and Computer Express Link (CXL) into the Ultra-Low-Latency of optical fabric of choice. He was the author and chair of the Storage Bridge Bay (SBB) specification and was on the SBB board of directors for multiple years. Mohamad participated technically and influenced various industry groups including the FC, SAS, NVMe, CXL and GenZ consortiums. In his career, Mohamad worked at leading enterprise storage technology and cloud provider companies, including Tandem, EMC, Mylex, IBM, LSI, Engenio, NetApp and now Seagate. Mohamad has 30+ year history of enterprise and cloud storage architecture knowledge, experience, and innovation. Mohamad holds 50+ issued and 20+ pending patents, covering: High-Availability/Resiliency Storage and Memory solutions, SSD controller and Systems architecture focus areas.
03:15 PM to 05:00 PM
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PRO PDSA2: Quantum Memory: Superconducting Qubits & Quantum Computer HW Design - Pt 2
Track: Professional Development Series (Pre-Conference)
Session Description:
Unlike classical memory, quantum computing's "no-clone theorem" limited Quantum memory using classical memory's read/write operations; when we access or measure qubits, their information is inevitably destroyed. Therefore, we must rely on quantum operations, precisely entanglement, to access qubits. As quantum computers advance, they demand many digital and analog circuits to execute control and measurement functions. The proliferation of qubits in an array has led to a significant increase in control and measurement signals. This signal surge has created a scalability issue for quantum computers, posing a challenge in their design and operation. The number of digital and analog cryogenic CMOS circuits has also escalated, leading to power and scalability issues, necessitating innovative solutions for quantum memory hardware design. Quantum memory is essential to quantum computing applications like finance, quantum chemistry, cryptography, and scientific research. Quantum networks enable secure, faster, and longer-distance transfer of quantum information. Moreover, they require quantum repeaters and quantum memory. This Professional Development Session aims to motivate experienced hardware and software engineers to explore the quantum field. We are exploring the advantages of quantum computing in finance, cryptography, chemistry, and optimization. Furthermore, quantum networks enable faster, longer-distance quantum information transfer with a secure network. Quantum memory is a significant element of quantum computing, and we are gaining knowledge of quantum hardware design using superconducting qubits. Part 2: • Understanding the quantum memory hardware design's challenges and qubit requirements • Understanding the critical difference between quantum memory vs classical memory array, Gaining knowledge of engineering requirements for quantum memory design • The hardware of a quantum computer-- system partition based on heat load • We summarize the technology requirements for quantum memory and quantum computers to scale up for sizeable quantum computing systems.
PRO PDSB2: CXL for Disaggregated Memory & Accelerators in Data Ctrs - Pt 2
Track: Professional Development Series (Pre-Conference)
Organizer + Chairperson:
Dr. Pankaj Mehra, Founder, Elephance
Speakers:
  • Siamak Tavallaei, CXL™ Consortium President, CXL Consortium
  • Samir Rajadnya, Principal Architect, Microsoft
  • Manoj Wadekar, Hardware System Technologist, Meta
Session Description:
The motivation for disaggregating memory is rooted in a desire to support and promote vast in-memory computing systems but without the issues of stranding and up-front provisioning. The speakers in this session will systematically comprehensively cover the topic of memory disaggregation leveraging the CXL standard from a software and hardware perspective, highlighting both challenges and opportunities. We will pay close attention to characteristics and use of memory at a distance. We conclude with our projections about the future of memory attachment in data centers. Topics: - CXL 3 and an update on standards covering P2P - Composable Memory Systems and OpenCompute Project - AI roadmap through 2030, the AI flywheel and data, and specific projections regarding memory and storage needs of AI - An updated analysis of memory expansion for AI, Database, and Virtual Machine workloads - Computational Memory and Storage Programming - Updated findings from architecture and operating systems for disaggregated memory
About the Organizer + Chairperson:
Pankaj Mehra is President and CEO of Elephance Memory. A contributor to InfiniBand 1.0 spec and an inventor of the first RDMA persistent memory devices and filesystems, Pankaj is a systems and software practitioner who conducts his research at the intersection of infrastructure and intelligence. He is a co-author/co-editor/co-inventor on 3 books, and over 100 papers and patents, and a builder of systems that have won recognition from NASA, Sandia National Labs, and Samsung Electronics, among others. He was a VP of Storage Pathfinding at Samsung, Senior Fellow and VP at SanDisk and Western Digital, WW CTO of Fusion-io, and Distinguished Technologist at HP Labs. Pankaj has held faculty positions at IIT Delhi and UC Santa Cruz.
PRO PDSC2: Introduction to High Bandwidth Memory (HBM)
Track: Professional Development Series (Pre-Conference)
Organizer + Presenter:
Marc Greenberg, Principal Consultant and CEO, Marc Greenberg Consulting, LLC
Session Description:
In this Professional Development Series session, you'll learn about key aspects of High Bandwidth Memory (HBM): What is HBM, a short history of HBM, why is HBM important right now, how Large Language Models (LLMs) and Generative AI are driving demand for HBM technology, comparison of HBM with other popular memory types (DDR, LPDDR and GDDR), a high level view of HBM architecture, PCB and package requirements to implement chips deploying HBM, a view of the market for HBM and the chips that use it, and a review of public information on the future development of high bandwidth memories.
About the Organizer + Presenter:
Marc Greenberg is an independent consultant in memory, semiconductor and IP. Marc currently serves as VP of Product for Cassia.ai, an AI IP company, as vice-chair of an undisclosed task group at JEDEC, and as advisor to several other companies. Marc was responsible for product management of HBM and other memory and storage IP products at Denali, Cadence and Synopsys for 20 years out of a 30-year career in semiconductor and IP. Marc has a master's degree in Electronics from the University of Edinburgh in Scotland.
PRO PDSD2: Optimizing HDD Performance in the Generative AI Data Center
Track: Professional Development Series (Pre-Conference)
Organizer + Presenter:
Mohamad El-Batal, Sr. Director of Architecture, Seagate
Speakers:
  • Praveen Viraraghavan, Technologist, Seagate
Session Description:
Citigroup inc. analysts quote "Enterprise data is expected to continue to grow at over 40% CAGR as AI becomes an incremental driver for data creation, storage, and data management" Today's AI ecosystem require fundamental shifts in the requirements of every datacenter infrastructure component. The predominant AI infrastructure strategy tends to currently focus on the most drastically impactful infrastructure components, as in GPUs, CPUs and Memory. Unfortunately, this leaves a major gap in the detailed understanding of the various AI Storage Infrastructure usage models with regards to the various TCO optimized storage tiers and their requirements from a Capacity, Workloads and Performance.
About the Organizer + Presenter:
Mohamad is on the Board of Directors of the Non-Volatile Memory Express (NVMe), Flash Memory Summit (FMS), and Open Compute Project (OCP). Mohamad is currently the chair of the NVMe-HDD working group and driving its requirements specification. He is also the chair of the OCP PCIe External Connectivity Workstream enabling PCIe to evolve with NVMe and Computer Express Link (CXL) into the Ultra-Low-Latency of optical fabric of choice. He was the author and chair of the Storage Bridge Bay (SBB) specification and was on the SBB board of directors for multiple years. Mohamad participated technically and influenced various industry groups including the FC, SAS, NVMe, CXL and GenZ consortiums. In his career, Mohamad worked at leading enterprise storage technology and cloud provider companies, including Tandem, EMC, Mylex, IBM, LSI, Engenio, NetApp and now Seagate. Mohamad has 30+ year history of enterprise and cloud storage architecture knowledge, experience, and innovation. Mohamad holds 50+ issued and 20+ pending patents, covering: High-Availability/Resiliency Storage and Memory solutions, SSD controller and Systems architecture focus areas.
08:30 AM to 09:35 AM
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Open AIML-101-1: Storage for AI: Technology
Ballroom B, Floor 1
Track: AI and ML Applications
Organizer + Moderator:
David McIntyre, Director Product Planning, Samsung Electronics
Paper Presenters:
  • Tejas Chopra, Sr. Engineer, Netflix, Inc.
  • Chanson Lin, Founder/CEO, Embestor Technology
  • Molly Presley, SVP Marketing, Hammerspace
Session Description:
As the demand for high-performance AI/ML systems continues to grow, the need for multi-layered data storage architecture has become crucial. Traditional single-layered devices are unable to meet the high bandwidth memory and storage requirements of AI inferencing and ML learning processes. A novel approach incorporating SRAM, DRAM, and NAND Flash memory pools has been developed to enhance I/O and memory access speeds, improving overall system performance. This advanced architecture, utilizing CXL or multiple bus channels, aims to boost the efficiency of AI/ML computing systems by providing high-speed access to data storage layers. Attendees will gain insights into how this innovative design can drive business outcomes by optimizing operational efficiencies, fostering innovation, and preparing organizations for future challenges.
About the Organizer + Moderator:
David McIntyre focuses on computational storage acceleration solutions development and strategic business enablement for cloud to edge applications including AI inference/video analytics, database processing and blockchain networks. He has held senior management positions with IBM, Samsung, Xilinx, Intel (formerly Altera) and at Silicon Valley startups. He has consulted for institutional investors including Fidelity, Goldman Sachs and UBS. David is a frequent presenter and chairperson at the Flash Memory Summit and other technical conferences including SNIA.
Open BMKT-101-1: Market Analyst Panel
GAMR 1 (Great America Meeting Room 1), Floor 2
Track: Business Strategies and Memory Markets
Organizer + Moderator:
Jean Bozman, President, Cloud Architects Advisors
Panel Members:
  • Camberley Bates, VP and Practice Lead, Futurum Group
  • Simone Bertolazzi, Technology and Market Analyst, Yole Intelligence
  • Avril Wu, Senior Research Vice President, TrendForce Corp.
  • Jeff Janukowicz, Vice President, IDC
Session Description:
In a shifting landscape of the DRAM market, the emergence of AI applications brings both challenges and opportunities for stakeholders. DDR5 technology is set to lead the charge in driving innovation and market growth. Our in-depth analysis explores the intricate dynamics of supply and demand, forecasting how DRAM prices will react to market forces. As DDR5 advances towards 1anm and 1bnm processes, alongside the increasing focus on HBM, the intersection with AI becomes paramount. This strategic roadmap provides valuable insights into supply/demand dynamics, capacity adjustments, growth projections, and major supplier strategies in the evolving DRAM market of 2025 and beyond.
About the Organizer + Moderator:
Jean S. Bozman is President of Cloud Architects Advisors, a market research and consulting firm focused on hardware and software for enterprise and hybrid multi-cloud computing. She analyzes the markets for servers, storage, and software related to datacenters and cloud infrastructure. A highly-respected IT professional, she has spent many years covering the worldwide markets for operating environments, servers, and server workloads. She was a Research VP at IDC, where she focused on the worldwide markets for servers and server operating systems. She is a frequent conference participant as a speaker, chairperson, and organizer at such events as Flash Memory Summit, OpenStack, and Container World. She is often quoted in a variety of publications including BusinessWeek, Investor’s Business Daily, the Los Angeles Times, CNET, Bloomberg, and Reuters. Ms. Bozman has also been VP/Principal Analyst at Hurwitz and Associates and Sr Product Marketing Manager at Sandisk. She earned a master’s degree from Stanford.
Open DRAM-101-1: DRAM Technology-Scaling Challenges & Future Directions
Ballroom C, Floor 1
Track: DRAM
Paper Presenters:
  • Ataberk Olgun, PhD Student, SAFARI Research Group at ETH Zurich
  • Abdullah Giray Yaglikci, Ph.D. Student, SAFARI Research Group at ETH Zurich
  • ByeongSoo Kang, ETCH ENGINEER, SK hynix
  • Ju Jin An, STSM, IBM
Session Description:
In this session, we delve into the realm of enhancing Generative AI with cutting-edge memory architectures. Faced with the ever-increasing demands of AI applications, the shift towards 3D DRAM technology is deemed essential. We will discuss technical innovations such as HBM with TSV, COP DRAM architecture, and the groundbreaking 4F2 architecture, and the future for memory architectures in bolstering Generative AI applications. We will also examine challenges in DRAM technology and solutions to combat vulnerabilities in DRAM chips, ensuring optimal performance without incurring unnecessary overhead.
Open FARP-101-1: FDP and ZNS
Ballroom D, Floor 1
Track: Flash Architectures and Provisioning
Organizer + Moderator:
Brian Berg, President, Berg Software Design
Paper Presenters:
  • Mariusz Barczak, Principal Engineer - Storage Software Architect, Solidigm
  • Jonmichael Hands, Sr Director Strategic Planning, Fadu
  • William Cheng, Director, Enterprise Marketing, Silicon Motion
  • Matias Bjorling, Distinguished Engineer and Country Manager, R&D Engineering, Western Digital
  • Rory Bolt, Principal Architect, KIOXIA
Session Description:
The demand for QLC adoption in the Enterprise storage market continues to grow, but the challenge of using QLC NAND has been a hindrance. However, the introduction of Flexible Data Placement (FDP) Technology is changing the game. FDP is being utilized in high-capacity QLC NAND applications to optimize data placement, improving performance and reducing costs. The benefits of using FDP in QLC applications are evident, as seen in increased efficiency and lifespan of devices. In a similar manner, Cloud Storage Acceleration Layer (CSAL) is leveraging Gen5 FDP NVMe Technologies to provide a high-density and high-performance local disks for cloud storage, reducing user costs and driving down expenses. Furthermore, FDP is a powerful new standard that every storage architect should be aware of, allowing for unprecedented control over data organization within SSDs. By reducing Write Amplification, FDP enhances device performance and lifespan. Finally, FDP performance in VMs with multiple NVMe namespaces has been proven through case studies, showcasing the benefits for hyperscalers and cloud-native workloads. Zoned storage, on the other hand, has become widely available across various storage devices, proving to be an effective way to reduce TCO and improve system performance. The past, present, and future of zoned storage will be discussed, highlighting the scalability benefits and advancements in software support.
About the Organizer + Moderator:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley Section, Director and past Chair of the Consultants Network of Silicon Valley, Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for Outstanding Service to the Consulting and Electrical Engineering profession, and the 2012 Outstanding Leadership and Professional Service Award for Region 6.
Open INVT-101-1: Invited Talk with Andrew Tomlin
Ballroom E, Floor 1
Track: Invited Talks
Organizer + Chairperson:
Leah Schoeb, Sr. Developer Relations Manager, AMD
Paper Presenters:
  • Andrew Tomlin, CEO, QiStor
Session Description:
In this Invited Talk, Andrew Tomlin, founder of QiStor, will discuss how advancements in storage acceleration technology have not kept pace with other technological domains, such as AI. Key-Value databases have emerged as the fastest-growing database technology, crucial for powering webscale applications and services. He will examine an NVMe Key-Value solution employing FPGAs within the data center, and its potential benefits for customers, and will offer insights into the workings of Key-Value databases with traditional flash devices, and how the device-level Key-Value interface revolutionizes the landscape by impacting both cost and performance. He will also explore the hurdles encountered in developing this technology, and will propose solutions that can be extrapolated to other hardware projects.
About the Organizer + Chairperson:
Leah Schoeb is a Sr Developer Relations Manager in AMD's platform architecture team, where she engages with solid state storage vendors on storage technology futures. She has over 25 years of experience in the computer industry, and was previously Acting Director of Reference Architecture at Intel where she led a team of segment managers and architects managing cross functional teams for flash- and NVMe-based data solutions. Leah has held management and engineering positions at VMware, Dell, and Sun Microsystems, and was also a Senior Partner at the analyst firm Evaluator Group, where she focused on storage, virtualization, and cloud infrastructure. Leah has ten technical publications, and has presented at many technical conferences. Her MBA us from the Univ. of Phoenix, and heer BSEE is from the Univ. of Maryland, College Park.
Open SPOS-101-1: Boost Memory Capacity & Performance For Modern Workloads with CXL
Ballroom A, Floor 1
Track: Sponsored Sessions
Session Sponsor:
NVM Express
Session Description:
Compute Express Link (CXL) is a cache-coherent interface that enables memory expansion and heterogeneous memory for disaggregated systems. CXL technology helps reduce storage latency, boost system performance and efficiency, and break through the limitations of current memory interface technology. This panel will share data points from CXL technology implementations to show how CXL meets the memory capacity and bandwidth needs for AI, HPC, and in-memory database applications. Attendees will gain insights into the solutions that are readily available within the market.
Open SSDT-101-1: Flash & Memory Controller Technologies for AI
Ballroom F, Floor 1
Track: SSD Technology
Organizer:
Erich Haratsch, Senior Director Architecture, Marvell
Paper Presenters:
  • Dr. Tao Lu, Research Manager, DapuStor
  • Licheng Xue, ASIC digital design manager, Starblaze
  • Vasanthi Jagatha, Senior Manager, Product Marketing, Marvell
  • Yuyang Sun, Product Marketing Engineer, Solidigm
Session Description:
In the ever-evolving landscape of artificial intelligence (AI), the demand for faster and more efficient data processing is at an all-time high. Flash storage technology has emerged as a pivotal player in the AI hardware infrastructure, offering the potential to optimize data-intensive tasks and enhance system performance. However, challenges such as dynamic data loading from Flash to DRAM for LLM inference and finding the right flash controllers for Gen AI applications have arisen. Additionally, the innovative CXL2P protocol has been introduced to address DRAM shortages in large-capacity SSDs and reduce costs, ensuring optimal performance without compromising efficiency. Join us as we explore the exciting possibilities of flash storage in the AI era.
About the Organizer:
Erich Haratsch is Senior Director Architecture at Marvell, where he leads the architecture definition for Bravera SSD controllers and other memory-based products. Prior to joining Marvell, he worked at Seagate and LSI, where he worked on Nytro and SandForce branded SSD controllers. Earlier in his career, he developed signal processing and error correction technologies for multiple generations of HDD controllers at LSI and Agere Systems. He started his career at AT&T and Lucent Bell Labs, where he worked on Gigabit Ethernet over copper, optical communications and the MPEG-4 video standard. He is the author of over 40 peer-reviewed journal and conference papers, and holds more than 200 U.S. patents. He also is a Senior Member of IEEE, and earned his MS and PhD degrees from the Technical University of Munich (Germany).
Open UCIC-101-1: UCIe Solution Technology Innovations NEW
Ballroom G, Floor 1
Track: UCIe and Chiplets
Organizer:
Brian Rea, Technology Initiative and Ecosystem Enablement Manager, Intel
Paper Presenters:
  • David Kulansky, Director of Product Marketing, Alphawave Semi
  • Randy White, Memory Solutions Program Manager, Keysight
  • Nilesh Shah, VP, Business Development, ZeroPoint Technologies
  • Prashant Dixit, Senior Engineering Manager, Siemens EDA
Session Description:
In this session, we will first examine how chiplet-based dompressed LLC cache and memory expansion utilizes cutting-edge hardware-accelerated chiplet IP to overcome memory and SRAM scaling challenges in data centers and smart devices. This IP achieves real-time memory compression with sub 10ns latency, seamlessly integrating with various memory chiplets while enhancing cost-effectiveness and preserving performance. We will then discuss how to address the challenges in functional verification for UCIe designs, offering strategies for die-level testbench reuse and synchronization. We will then explore how UCIe enables efficient communication between components for improved performance and reduced power consumption. UCIe and how to enable an open chiplet ecosystem discuss the standardization of die-to-die interfaces and the importance of test and validation tools for an interconnected chiplet ecosystem.
About the Organizer:
Brian Rea has served as a marketing work group co-chair of UCIe since 2022 and is a Technology Initiative and Ecosystem Enablement Manager at Intel. Rea holds a MBA from the University of Washington and a B.S. in Electrical Engineering from the University of Texas at Austin.
09:45 AM to 10:50 AM
No search results found in this timeslot.
PRO AIML-102-1: Storage for AI: Applications
Ballroom B, Floor 1
Track: AI and ML Applications
Organizer:
David McIntyre, Director Product Planning, Samsung Electronics
Paper Presenters:
  • Swapna Yasarapu, Azure Storage Architecture, Microsoft
  • John Mazzie, Senior Solutions Engineer, Micron Technology
  • Surendar Saini, Engineering Manager, Solidigm
Session Description:
This session examines a variety of approaches and applications used in storage for artificial intelligence, including direct memory access transfers between the GPU and storage device, eliminating the need for intermediate copies in CPU memory. We will also discuss RAG optimized SSD solutions for the Generative AI era, and explore how storage media and architecture are evolving to cater to AI workloads. Join us in analyzing workloads using storage as memory replacement for large model training.
About the Organizer:
David McIntyre focuses on computational storage acceleration solutions development and strategic business enablement for cloud to edge applications including AI inference/video analytics, database processing and blockchain networks. He has held senior management positions with IBM, Samsung, Xilinx, Intel (formerly Altera) and at Silicon Valley startups. He has consulted for institutional investors including Fidelity, Goldman Sachs and UBS. David is a frequent presenter and chairperson at the Flash Memory Summit and other technical conferences including SNIA.
Open BMKT-102-1: Memory Markets
GAMR 1 (Great America Meeting Room 1), Floor 2
Track: Business Strategies and Memory Markets
Organizer + Chairperson:
Jean Bozman, President, Cloud Architects Advisors
Paper Presenters:
  • James Pan, Senior Principal Engineer Project Manager, Northrop Grumman
  • Ronen Hyatt, Founder and CEO, Unifabrix
  • John Lorenz, Senior Analyst, Yole Group
  • Jim Handy, General Director, Objective Analysis
  • Nilesh Shah, VP, Business Development, ZeroPoint Technologies
Session Description:
This session provides insight into the market outlook amidst great changes in semiconductor consumption due to factors like AI system adoption, trade wars, and new technologies. We will discuss the foreseeable impacts and challenges in the evolving memory landscape. The dynamics of IP licensing economics in memory and storage SoC/chiplets development will be explored in-depth, covering market trends, leveraging IP ecosystems, cost-benefit analysis, risk management, and technological advancements. We will aim to shed light on the complex economic landscape of IP licensing within the semiconductor industry. We will also explore the use of nonlinear optical materials and processes, and the revolution in optical computing. Additionally, the memory market recovery and focus on datacenter and CXL demand will be analyzed, highlighting the rebound of DRAM and NAND markets and the factors contributing to their recovery.
About the Organizer + Chairperson:
Jean S. Bozman is President of Cloud Architects Advisors, a market research and consulting firm focused on hardware and software for enterprise and hybrid multi-cloud computing. She analyzes the markets for servers, storage, and software related to datacenters and cloud infrastructure. A highly-respected IT professional, she has spent many years covering the worldwide markets for operating environments, servers, and server workloads. She was a Research VP at IDC, where she focused on the worldwide markets for servers and server operating systems. She is a frequent conference participant as a speaker, chairperson, and organizer at such events as Flash Memory Summit, OpenStack, and Container World. She is often quoted in a variety of publications including BusinessWeek, Investor’s Business Daily, the Los Angeles Times, CNET, Bloomberg, and Reuters. Ms. Bozman has also been VP/Principal Analyst at Hurwitz and Associates and Sr Product Marketing Manager at Sandisk. She earned a master’s degree from Stanford.
PRO COMP-102-1: CS Solution/Technology Innovations NEW
Ballroom C, Floor 1
Track: Computational Storage
Organizer:
Scott Shadley, Strategic Planner, Solidigm
Paper Presenters:
  • Nika Mansouri Ghiasi, PhD Student, SAFARI Research Group at ETH Zurich
  • Woosuk Chung, Storage Software Team Lead, SK hynix
  • Ujjwal Negi, Member Technical Staff, Siemens EDA
  • Qing Zheng, Scientist, Los Alamos National Laboratory
Session Description:
In this session, we dive into the world of object-based computational storage for data analytics, which is revolutionizing the way data analytics systems process and transfer data. Verification of computational storage designs, crucial for ensuring the functionality and reliability of computational storage systems, uses APIs, UVM features, and efficient testing techniques to reduce time to market. Lastly, storage-centric computing for genomics and metagenomics is reshaping the field by addressing data movement overheads and improving performance in genomic applications with innovative in-storage processing system. Let's continue pushing the boundaries of computational storage for a brighter future in data analytics and genomics.
About the Organizer:
Scott Shadley has spent over 25 years in the semiconductor and storage space. He has time in Production, Engineering, R&D, Customer focused roles including Marketing and Strategy. His current focus is in efforts to drive adoption of new storage technology as a Director of Strategic Planning at Solidigm. He has been a key figure in promoting SNIA as a second term Board member and leading the computational storage efforts as a co-chair of the SNIA Technical Working Group. He participates in several industry efforts like Open Compute, NVM Express and is seen as a subject matter expert in SSD technology and semiconductor design. He has and still speaks on the subject at events like the Open Compute Summit, Flash Memory Summit, SDC, and many other events, press interviews, blogs, and webinars. While at NGD Systems, Scott developed and managed the Computational Storage products and ecosystem. Scott previously managed the Product Marketing team at Micron, was the Business Line Manager for the SATA SSD portfolio, and was the Principal Technologist for the SSD and emerging memory portfolio. He launched four successful innovative SSDs for Micron and two for STEC, all of which were billion dollar programs. Scott earned a BSEE in Device Physics from Boise State University and an MBA in marketing from University of Phoenix.
PRO CXLT-102-1: CXL Fabric Management
Ballroom E, Floor 1
Track: CXL
Paper Presenters:
  • Grant Mackey, CTO, Jackrabbit Labs
  • Sudhir Balasubramanian, Sr Staff Solution Architect - Oracle, VMware by Broadcom
  • Yong Tian, Field CTO, MemVerge
  • Bhushan Chitlur, Sr Principal Engineer, Datacenter & AI Group, Intel
  • Navneet Rao, Engineer, Intel
Session Description:
This session discusses how memory innovations are leveraging technologies like persistent memory, memory tiering, and the latest addition of CXL. Open source fabric management and orchestration layers for CXL devices and switches can offer best practices for seamless integration with familiar platform management tools. Additionally, with CXL 1.1, servers now supporting memory expansion through CXL Memory Add-in Cards and E3.S memory modules, sellers and buyers can now integrate cost-effective and high-capacity solutions. Attendees will gain valuable insights into the benefits and strategies of incorporating mixed memory configurations in server environments, ultimately optimizing application performance.
PRO DCTR-102-1 Hyperscale Applications Part 1
Ballroom D, Floor 1
Track: Data Center Applications
Organizer:
Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft
Paper Presenters:
  • Vineet Parekh, Hardware Systems Engineer, Meta
  • Lee Prewitt, Principal Hardware Program Manager, Microsoft
  • Wei Zhang, Software Engineer, Meta
  • Ross Stenfort, Hardware Systems Engineer, Storage, Meta
Session Description:
This session will share the latest updates on storage from a hyperscale perspective in the storage industry. We will delve into the use of SSDs in Meta datacenters, exploring the challenges faced in designing and maintaining storage in the Meta fleet. We’ll also shed light on the changing landscape of the storage ecosystem and Meta's role in shaping it. Additionally, the discussion on Flexible Data Placement (FDP) in the real world will highlight the advantages of FDP at scale, offering insights into its practical applications and benefits.
About the Organizer:
Jonathan Hinkle is Senior Director - Azure Memory and Storage Pathfinding at Microsoft. He previously was In Micron's Storage Business Unit, where he investigated new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.
Open SPOS-102-1: SNIA: Data and Storage Standards to Accelerate Implementations NEW
Ballroom A, Floor 1
Track: Sponsored Sessions
Session Sponsor:
SNIA
Organizer + Chairperson:
Bill Martin, Principal Engineer SSD I/O Standards, Samsung Electronics
Paper Presenters:
  • Anthony Constantine, SFF Co-Chair and SNIA Technical Council, SNIA
  • Richelle Ahlvers, Storage Technology Enablement Architect, Intel
  • Shyam Iyer, Distinguished Engineer, Dell
Session Description:
SNIA develops standards across a wide range of data and storage technologies today. This session will provide a brief overview of the organization’s scope, and dive into three of SNIA’s key standards that affect the future of memory and storage. SNIA has led the development of standards-based management standards and conformance programs for over 20 years. Get an update on the latest work from SNIA and its alliance partners to provide integrated manageability standards across technologies. SNIA’s SFF specifications provide the necessary connectors and form factors to deliver interoperable systems. Recent demand for offload-based data processing is driving increased demand for accelerators, and in turn, for standardization of accelerator usage
About the Organizer + Chairperson:
Bill Martin has over 30 years of experience in the storage industry. He is currently responsible for driving Solid State Storage forward within the industry for Samsung in a variety of standards arenas, including NVM Express board member, Co-Chair of the SNIA Technical Council, Chair of the SCSI T10 Committee, Co-Chair of the of the NVMe Computational Storage Task Group, Co-Chair of the SNIA Computational Storage Technical Work Group, Secretary of ATA T13 Committee, and editor of the SCSI T10 Block Commands document. He has also had extensive experience in the Fibre Channel arena including with the T11 Standards committee and leading FC interoperability events. His employers have included HP, Gadzoox, Brocade, Sierra Logic, Emulex and now Samsung. His industry work has been recognized with numerous awards from NVMe, INCITS, FCIA and SNIA.
PRO SSDT-102-1: SSD Technologies for Compute Use Cases
Ballroom F, Floor 1
Track: SSD Technology
Organizer:
Erich Haratsch, Senior Director Architecture, Marvell
Paper Presenters:
  • Trent Johnson, SSD Hardware Architect, IBM
  • Nick Snow, Product Manager, Enterprise SSDs, KIOXIA America, Inc
  • Nikhil Garg, Senior Engineer, Micron Technology
  • Devesh Rai, Sr. Staff Strategic Marketing Manager, KIOXIA America, Inc
  • Chandra Nelogal, Distinguished Member of Technical Staff, Trusted Computing Group
Session Description:
In this session, we look at SSD technologies for compute use cases. PCIe 6.0 SSDs are revolutionizing the future of compute and storage with their incredible speed and performance, doubling that of the previous generation. As NVMe solid state drives continue to evolve, new considerations such as signal integrity and thermal constraints must be taken into account to fully leverage the power of PCIe 6.0. RAID offload technology offers a promising solution to reduce compute and DRAM usage in data redundancy applications, making it adaptable in various areas such as data scrubbing, network traffic reduction, and data center applications. The FlashCore Module from IBM is the engine behind their Flash Systems, providing enterprise-level storage with cost-saving features and improved performance. Knowledge Aware SSDs are introducing a novel method to rebuild failed RAID drives, leveraging firmware to offload host system resources and optimize overall system performance.
About the Organizer:
Erich Haratsch is Senior Director Architecture at Marvell, where he leads the architecture definition for Bravera SSD controllers and other memory-based products. Prior to joining Marvell, he worked at Seagate and LSI, where he worked on Nytro and SandForce branded SSD controllers. Earlier in his career, he developed signal processing and error correction technologies for multiple generations of HDD controllers at LSI and Agere Systems. He started his career at AT&T and Lucent Bell Labs, where he worked on Gigabit Ethernet over copper, optical communications and the MPEG-4 video standard. He is the author of over 40 peer-reviewed journal and conference papers, and holds more than 200 U.S. patents. He also is a Senior Member of IEEE, and earned his MS and PhD degrees from the Technical University of Munich (Germany).
PRO UCIC-102-1: UCIe Technology Opportunities & Benefits NEW
Ballroom G, Floor 1
Track: UCIe and Chiplets
Organizer:
Brian Rea, Technology Initiative and Ecosystem Enablement Manager, Intel
Paper Presenters:
  • Mayank Bhatnagar, Product Marketing Director, Cadence Design Systems
Session Description:
UCIe (Universal Chiplet Interconnect Express) is revolutionizing the field of SoC construction by providing an open industry standard that allows for more customizable package-level integration. Founded by key players in the semiconductor industry, UCIe 1.1 Specification was introduced at FMS 2023, bringing significant improvements to the chiplet ecosystem. This session will highlight the enhancements made in the UCIe 1.1 specification, as well as how it simplifies system setups and compliance testing for device interoperability. By reducing the barrier to entry for boutique chiplet designers and enabling a "chiplet marketplace," UCIe is paving the way for a more innovative and competitive future in chiplet design.
About the Organizer:
Brian Rea has served as a marketing work group co-chair of UCIe since 2022 and is a Technology Initiative and Ecosystem Enablement Manager at Intel. Rea holds a MBA from the University of Washington and a B.S. in Electrical Engineering from the University of Texas at Austin.
10:50 AM to 11:00 AM
No search results found in this timeslot.
Open Chairman's Welcome
Mission City Ballroom, Floor 1
Track: FMS 2024 Special Sessions
Session Description:
FMS Conference Chair Chuck Sobey welcomes all to FMS24 - the Future of Memory and Storage, and provides an overview of the three day event.
11:00 AM to 11:30 AM
No search results found in this timeslot.
Open Keynote 1: KIOXIA
Mission City Ballroom, Floor 1
Track: FMS 2024 Keynotes
Session Sponsor:
KIOXIA
Speakers:
  • Atsushi Inoue, VP and Technology Executive, KIOXIA
  • Neville Ichhaporia, Sr. VP & General Manager, KIOXIA America, Inc
Session Description:
With continued pursuit of innovation for more than 35 years, NAND flash memory has become an indispensable technology to capture data – the “new currency” of our digital world – fueling emerging paradigms in the world of AI, Cloud, and Edge Computing. Looking toward the future, KIOXIA’s BiCS FLASH™ 3D generations will continue to scale, enabling higher density and performance along with cost and power improvements. KIOXIA will lead the way and present cutting edge memory and SSD technologies, as well as highlight advanced developments to address the memory and storage needs for next-generation applications with innovations and optimizations rooted in flash-memory based technologies and approaches. No matter what your application, get there with KIOXIA.
11:30 AM to 11:40 AM
No search results found in this timeslot.
Open 2024 Lifetime Achievement Award
Mission City Ballroom, Floor 1
Track: FMS 2024 Special Sessions
Organizer + Moderator:
Brian Berg, President, Berg Software Design
Organizer + Moderator:
Jim Handy, General Director, Objective Analysis
Session Description:
The FMS Lifetime Achievement Award recognizes individuals who have shown outstanding leadership in promoting the development and use of memory, storage, and/or associated or related technologies, including one or more of the following: - Creating or promoting an important memory or storage technology, or a related technology, - Leadership of a major memory or storage company, business effort, or academic program, - Bringing memory or storage technology to a new and important application Lifetime Achievement Award winners may be for a single person, or for a small team or group of individuals with an important connection. By bestowing this award, FMS hopes to help foster further advances in the memory and storage industries.
About the Organizer + Moderator:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley Section, Director and past Chair of the Consultants Network of Silicon Valley, Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for Outstanding Service to the Consulting and Electrical Engineering profession, and the 2012 Outstanding Leadership and Professional Service Award for Region 6.
About the Organizer + Moderator:
Jim Handy, Objective Analysis, is a leading semiconductor analyst. After positions at Intel, National Semi, and Infineon he is respected for his tech depth, accurate forecasts, and numerous reports. See http://Objective-Analysis.com, http://TheMemoryGuy.com, and http://TheSSDguy.com.
11:40 AM to 11:45 AM
No search results found in this timeslot.
Open 2024 Special Award
Mission City Ballroom, Floor 1
Track: FMS 2024 Special Sessions
Session Description:
Description Not Available
11:45 AM to 12:15 AM
No search results found in this timeslot.
Open Keynote 2: NEO Semiconductor
Mission City Ballroom, Floor 1
Track: FMS 2024 Keynotes
Session Sponsor:
NEO Semiconductor
Speakers:
  • Andy Hsu, CEO, NEO Semiconductor
Session Description:
The demand to accelerate artificial intelligence applications (AI apps) continues growing, especially for emerging workloads involving artificial neural networks like generative AI. Current AI Chips simulate neural networks for AI apps using a processor (GPU), memory (HBM), and software, but architectural inefficiencies waste significant amounts of performance and power. Next-generation AI Chips will use totally new AI Chip technology to perform neural network operations inside 3D DRAM, enabling 100x higher performance and 99% lower power consumption. New 3D architectures have the potential to enable the next wave of AI applications with more innovative memory and storage solutions.
01:00 PM to 01:30 PM
No search results found in this timeslot.
Open Keynote 3: SK hynix
Mission City Ballroom, Floor 1
Track: FMS 2024 Keynotes
Session Sponsor:
SK hynix
Speakers:
  • Unoh Kwon, VP, Head of HBM PI, SK hynix
  • Chunsung Kim, VP, Head of WW SSD, SK hynix
Session Description:
Generative AI, which is currently a hot topic, is evolving into GPT4, multilingual reasoning, and coding capabilities, and is expected to ultimately bring about transformations such as the "Industrial Revolution." SK hynix AI memory plays a pivotal role in AI chips, which is the core background of Generative AI, by providing differentiated values in the AI era. With the rise of Generative AI, customer pain-points are becoming more specific such as ① To maximize the learning/inferencing amount per hour; ② To minimize power consumption for learning/inferencing; ③ To minimize floor space and power utilization for storing data, which is increased for Gen AI use. As memory & storage plays a pivotal role in AI technology, SK hynix is committed to continuous innovation and technological breakthroughs to solve customer pain-points in AI memory & storage development and aims to contribute to the advancement of the ICT industry by providing world-best AI memory products and strengthening collaboration with global partners.
01:30 PM to 02:00 PM
No search results found in this timeslot.
Open Keynote 4: Samsung
Mission City Ballroom, Floor 1
Track: FMS 2024 Keynotes
Session Sponsor:
Samsung Semiconductor
Speakers:
  • Taeksang Song, Vice President, Samsung Seminconductor Inc
  • Hwaseok Oh, EVP of Solution Product Engineering, Samsung Seminconductor Inc
  • Jim Elliott, , Samsung Electronics
Session Description:
As we enter a new phase of the AI revolution, significant technological advancements are reshaping the way we think about computation and data processing. The rapid growth in data generation and complex workload requirements has led to increased computational power, enabling the development of sophisticated, large-scale AI models. This shift necessitates advanced GPUs and enhanced memory and storage solutions for learning and inference. These solutions must provide substantial bandwidth, power-efficiency, and durability to maintain checkpoints and support proliferated multimodal AI models. Concurrently, there is a need to address sustainability challenges, such as increased power and cooling demands within data centers. In this keynote, we will explore cutting-edge memory products and technologies essential for various AI applications, highlighting how NAND solutions and CXL memory modules can be tailored to optimize performance across each application. We will discuss how these technologies meet and drive the demand for high-capacity storage in AI computing, aiming to improve Total Cost of Ownership (TCO) through enhanced power efficiency and effective space management. Some of the main technologies we will cover include cutting-edge DRAM technologies such as 256GB RDIMM/512GB MRDIMM and CXL 3.1 memory modules. We will also discuss high-bandwidth PCIe Gen6, enabling high-speed data access and reliability to enhance GPU efficiency.
02:00 PM to 02:30 PM
No search results found in this timeslot.
Open Keynote 5: FADU
Mission City Ballroom, Floor 1
Track: FMS 2024 Keynotes
Session Sponsor:
FADU
Speakers:
  • Eric Spanneut, VP of Marketing, Western Digital
  • Ross Stenford, Hardware Storage Engineer, Meta
  • Jiyho Lee, CEO and Co-Founder, FADU
Session Description:
Today Hyperscale’s wield significant influence over flash storage consumption, with a handful of vendors commanding much of the market. Amidst this dominance, the surge of AI applications stands as a pivotal force, reshaping infrastructure demands at an unprecedented pace. This keynote presentation delves into the intersection of hyperscale growth, AI expansion, and flash storage evolution. Exploring the symbiotic relationship between infrastructure advancements and flash storage requirements, we dissect the implications for standardization efforts, particularly through initiatives like the Open Compute Project (OCP). Moreover, we unravel the novel features essential for flash storage to meet the soaring demands of hyperscale environments, offering insights crucial for navigating the future of storage technology.
02:30 PM to 03:00 PM
No search results found in this timeslot.
Open Keynote 6: Microchip
Mission City Ballroom, Floor 1
Track: FMS 2024 Keynotes
Session Sponsor:
Microchip Technology Inc.
Speakers:
  • Rob Reed, Senior Director of Product Development, Microchip Technology
Session Description:
In the rapidly evolving landscape of artificial intelligence (AI), data has become the new gold. The need to protect the data and the underlying infrastructure from a myriad of threats has never been more pressing. We will look at the challenges that organizations face, the complexities of security from the ground up and provide key strategies to mitigate risk in a post-quantum world. We will examine the unique vulnerabilities inherent in AI infrastructure, from data pipelines and machine learning models to the compute resources that power them. The discussion will highlight how these vulnerabilities can be exploited by adversaries to compromise the integrity, confidentiality and availability of AI systems. We will highlight real-world scenarios where security breaches have led to significant consequences, underscoring the importance of a proactive and comprehensive security strategy. We will introduce a multi-layered approach that encompasses the latest in cybersecurity best practices, tailored specifically for the nuances of AI systems. We’ll look at security for data at rest and in transit and protecting model integrity. We will also consider the implications of quantum computing and what is needed to address those challenges. Attendees will gain an understanding of the key issues and strategies to secure their AI infrastructure effectively and how Microchip is working across our portfolio and within the industry to create a complete security solution for protecting the world’s data.
03:00 PM to 03:30 PM
No search results found in this timeslot.
Open Keynote 7: Western Digital
Mission City Ballroom, Floor 1
Track: FMS 2024 Keynotes
Session Sponsor:
Western Digital
Speakers:
  • Robert Soderbery, Executive Vice President & General Manager, Western Digital
Session Description:
With the new era of NAND being driven by new industry dynamics Western Digital Executive Vice President & General Manager, Flash Business, Robert Soderbery, will discuss how the focus has shifted towards optimizing supply and demand, ensuring products meet customer needs, and navigating a market that is increasingly complex and segmented. He will share important insights on the critical role of storage in the AI data center all the way to the edge. Finally, Robert will reveal next-generation products and technologies fueling growth across the entire data cycle.
03:30 PM to 07:00 PM
No search results found in this timeslot.
Open Grand Opening Reception
Exhibit Hall, Floor 1
Track: Exhibits
Session Description:
FMS24 welcomes all attendees to their Grand Opening Reception in the Santa Clara Convention Center Exhibit Hall. Join fellow attendees and FMS24 sponsors to celebrate the Future of Memory and Storage!
03:40 PM to 04:45 PM
No search results found in this timeslot.
PRO AIML-103-1: Memory to Data Center: Architectures and Interconnect Technologies
Ballroom B, Floor 1
Track: AI and ML Applications
Organizer:
David McIntyre, Director Product Planning, Samsung Electronics
Panel Members:
  • Siamak Tavallaei, CXL™ Consortium President, CXL Consortium
  • Kurtis Bowman, Director, Server System Performance, AMD
Session Description:
This exciting new session at FMS24 will discuss interconnect architecture considerations and provide an Ultra Architecture Link (UALink) and Ultra Ethernet Consortium (UEC) overview, A panel discussion will follow.
About the Organizer:
David McIntyre focuses on computational storage acceleration solutions development and strategic business enablement for cloud to edge applications including AI inference/video analytics, database processing and blockchain networks. He has held senior management positions with IBM, Samsung, Xilinx, Intel (formerly Altera) and at Silicon Valley startups. He has consulted for institutional investors including Fidelity, Goldman Sachs and UBS. David is a frequent presenter and chairperson at the Flash Memory Summit and other technical conferences including SNIA.
PRO AOSD-103-1: Aerospace and Outer Space Data NEW
Ballroom E, Floor 1
Track: Aerospace to Outer Space Data (AOSD)
Paper Presenters:
  • Crystal Chang, Senior Manager, ATP Electronics
  • George Williams, , Armijo Innovations
  • Paul Armijo, , Armijo Innovations
  • Sebastien Jean, CTO, Phison Electronics
  • Dr Erik Nilsen, Chief Technology Strategist, Flexxon
Session Description:
In the realm of aerospace and outer space data storage, the development of radiation-hardened NAND storage systems is crucial. These robust solutions are specially crafted to withstand the intense radiation environments beyond Earth, ensuring enhanced data reliability and longevity. RAD-HARD NAND storage is equipped to endure high levels of radiation, thanks to its unique materials and manufacturing processes. This session will address the challenges of storing data in space, the specific requirements for radiation-hardened NAND storage, and the potential impact of this technology on fortifying data integrity in extreme conditions. It's a groundbreaking leap in data storage capabilities for the aerospace industry.
Open BMKT-103-1: CMO Panel
GAMR 1 (Great America Meeting Room 1), Floor 2
Track: Business Strategies and Memory Markets
Session Description:
Description Not Available
PRO DCTR-103-1: Hyperscale Applications Part 2
Ballroom D, Floor 1
Track: Data Center Applications
Organizer:
Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft
Paper Presenters:
  • Hyung Kim, Technical Sourcing Manager, SSD/NAND, Meta
  • Venkatraghavan Ramesh, Hardware Systems Engineer, Meta
  • Vidhya Arvind, Staff Engineer, Netflix Inc
Session Description:
Description Not Available
About the Organizer:
Jonathan Hinkle is Senior Director - Azure Memory and Storage Pathfinding at Microsoft. He previously was In Micron's Storage Business Unit, where he investigated new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.
PRO DRAM-103-1: Influence of AI on Memory Technology NEW
Ballroom C, Floor 1
Track: DRAM
Organizer:
Ju Jin An, STSM, IBM
Paper Presenters:
  • Bill Gervasi, Principal Systems Architect, Wolley Inc
  • Jim Handy, General Director, Objective Analysis
  • Taekwon Jee, Principal Engineer, SK hynix
Session Description:
CXL Native Memory challenges the need for DDR by proposing a more efficient memory interface that directly connects memory cores to the CXL FLIT, reducing latency overhead and power consumption. With applications like large language models demanding over 140GB of local capacity, CXL memory modules offer a solution for memory expansion that HBM cannot match. Meanwhile, the increasing demand for High Bandwidth Memory (HBM) driven by the AI boom raises questions about its sustainability. This session will discuss the future of HBM, its cost models, and the challenges it poses for DRAM makers and the industry as a whole. Advanced AI technology is also revolutionizing semiconductor device yield optimization, with the development of machine learning-based process pattern fidelity to secure extreme yields in various semiconductor processes.
About the Organizer:
Ju Jin serves as a Senior Technical Staff Member at IBM's Infrastructure Supply Chain Organization, drawing upon more than twenty years of experience in the semiconductor industry. Her expertise lies in silicon fabrication processes and process integration, areas critical to her leadership in advancing the main memory system for IBM's Power and z Systems. She holds an MS/Ph.D. in Chemical Engineering from MIT, solidifying her academic foundation and enhancing her contributions to the field.
Open SPOS-103-1: CXL Consortium NEW
Ballroom A, Floor 1
Track: Sponsored Sessions
Session Description:
This session, sponsored by CXL Consortium, will feature presentations from three of its Member companies. • Importance of Pre-boot Environment for CXL Type 3 Devices (Astera Labs) • CXL 2.0 Use Case – Using both DDR4 and DDR5 on the same server to allow memory and bandwidth scaling (Montage Technologies) • CXL 2.0 Fabric Deployment for a Composable Memory System (Xconn Technologies)
PRO SSDT-103-1: Technologies for Improving the Endurance & Reliability of SSDs
Ballroom F, Floor 1
Track: SSD Technology
Organizer:
Erich Haratsch, Senior Director Architecture, Marvell
Paper Presenters:
  • Niles Yang, Flashtec Architect, Microchip Technology Inc.
  • Maoruei Li, Project Deputy Manager, Silicon Motion
  • Vic Ye, Manager, YeeStor Microelectronics
  • Doug Dumitru, CT0, EasyCo LLC dba WildFire Storage
Session Description:
This session discusses technologies for improving the Endurance and reliability of SSDs, Flash storage devices require more read retries for error correction as they undergo wear and tear from program/erase cycles, slowing down operations. We will discuss various methods to analyze real flash chips, improve correction capability for advanced 3D NAND, and how to achieve better performance control and wear management, ensure longevity, and increase efficiency.
About the Organizer:
Erich Haratsch is Senior Director Architecture at Marvell, where he leads the architecture definition for Bravera SSD controllers and other memory-based products. Prior to joining Marvell, he worked at Seagate and LSI, where he worked on Nytro and SandForce branded SSD controllers. Earlier in his career, he developed signal processing and error correction technologies for multiple generations of HDD controllers at LSI and Agere Systems. He started his career at AT&T and Lucent Bell Labs, where he worked on Gigabit Ethernet over copper, optical communications and the MPEG-4 video standard. He is the author of over 40 peer-reviewed journal and conference papers, and holds more than 200 U.S. patents. He also is a Senior Member of IEEE, and earned his MS and PhD degrees from the Technical University of Munich (Germany).
PRO UCIC-103-1: UCIe and Chiplets: A Panel NEW
Ballroom G, Floor 1
Track: UCIe and Chiplets
Organizer + Presenter:
Brian Rea, Technology Initiative and Ecosystem Enablement Manager, Intel
Session Description:
Description Not Available
About the Organizer + Presenter:
Brian Rea has served as a marketing work group co-chair of UCIe since 2022 and is a Technology Initiative and Ecosystem Enablement Manager at Intel. Rea holds a MBA from the University of Washington and a B.S. in Electrical Engineering from the University of Texas at Austin.
05:45 PM to 07:00 PM
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Open FMS 2024 Best of Show Awards
FMS Theatre, Floor 2
Track: FMS 2024 Special Sessions
Organizer + Moderator:
Jay Kramer, President, Network Storage Advisors
Session Description:
The FMS24 Best of Show Awards recognize high-performance memory and storage innovations in eight distinct categories. These industry-recognized awards give winners the opportunity to effectively build their brand and image as an innovative leader in the marketplacThere are eight distinct award categories which address the wide range of high-performance memory and storage innovations in the market.
About the Organizer + Moderator:
Jay Kramer, founder at Network Storage Advisors, is a dynamic results-oriented strategic marketing leader and creator of world-class marketing teams with a proven track record of building company brand and demand generation initiatives that accelerate sales. He has over 25 years of repeated marketing success with industry leading Fortune 500 companies (Unisys, Seagate) as well as early and late stage emerging companies. His industry knowledge spans cloud, virtualization, software defined storage (SDS), hyper convergence, data protection, SAN, NAS, and object storage solutions plus network storage technologies including Fibre Channel, iSCSI, VTL, dedup, backup, and replication. He has served as board member to technology industry associations and event development/professional conference companies.
08:30 AM to 09:35 AM
No search results found in this timeslot.
Open ASIA-201-1: Asia Memory and Storage Markets Part 1
Ballroom F, Floor 1
Track: Asia Memory and Storage Markets
Organizer:
Janet Liu Erickson, Project Manager, Sage Micro
Paper Presenters:
  • Bryan Ao, Research Manager, TrendForce Corp.
  • Alex Xie, Engineering Director, Suzhou OKN Technology Co., LTD.
Session Description:
Emerging trends in automotive technology are driving efficiency and innovation through the integration of Dynamic Random Access Memory (DRAM) in automotive systems. DRAM like HBM3 and GDDR6 enable faster data processing, improved real-time decision-making, and enhanced safety features in modern vehicles. This comprehensive analysis explores the impact of DRAM integration in areas such as advanced driver assistance systems, autonomous driving platforms, and vehicle-to-everything communication networks. Furthermore, we examine the convergence of high-bandwidth and low power consuming DRAM technology in automotive innovation, highlighting the transformative potential for smarter, safer, and more efficient vehicles.
About the Organizer:
Janet Liu Erickson is a project manager at Sage Microelecronics.
Open CLDS-201-1: Cloud Architectures
Ballroom B, Floor 1
Track: Cloud Storage and Applications
Organizer:
Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft
Paper Presenters:
  • Nick Kriczky, Vice President, Teledyne LeCroy - Austin Labs
  • Chunmei Liu, Senior Engineer, Intel
  • Douglas Arens, Technical Staff, Applications Engineer, DCS, Microchip Technology
Session Description:
In this presentation, we will delve into the world of virtualization in cloud computing and how newer technologies such as Scalable IO Virtualization (SIOV) are revolutionizing the way we handle hardware resources in data centers and cloud storage. We will explore the transition from SR-IOV to SIOV, and how this shift is pushing the boundaries of virtualization to achieve greater scalability and efficiency. Additionally, we will discuss the performance analysis and optimization for multicore Crimson Ceph, highlighting the benefits of refactoring ceph osd based on the shared-nothing seastar framework. We will dive into the challenges faced during implementation and the solutions found to improve performance. Finally, we will explore the importance of OCP compliance for NVMe SSD drives in hyperscale compute environments, showcasing the new test requirements and benefits provided by the OCP specification. Join us to learn from industry experts and discover the future of virtualization, storage, and performance optimization.
About the Organizer:
Jonathan Hinkle is Senior Director - Azure Memory and Storage Pathfinding at Microsoft. He previously was In Micron's Storage Business Unit, where he investigated new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.
Open COMP-201-1: Computational Storage Use Cases NEW
Ballroom G, Floor 1
Track: Computational Storage
Organizer:
Scott Shadley, Strategic Planner, Solidigm
Paper Presenters:
  • JB Baker, VP Marketing, ScaleFlux
  • Pan Zicheng, IC Application, staff engineer, Beijing Starblaze Technology
  • Tim Fisher, Flash Controller HW Lead, IBM
Session Description:
With the rise of PCIe and advanced architecture in SSDs, distributed software architecture is transforming the way computational tasks are handled. By offloading tasks from the host system to SSDs, significant improvements in performance and efficiency can be achieved. For example, utilizing "File System in SSD" and "Database in SSD" showcases enhanced computational throughput and reduced latency. Furthermore, combining deduplication and compression at the SSD level can optimize storage utilization, performance, and cost in enterprise storage appliances. Join us for a panel discussion with industry experts to explore real-world case studies and applications of computational storage, highlighting the tangible benefits and future developments in this space.
About the Organizer:
Scott Shadley has spent over 25 years in the semiconductor and storage space. He has time in Production, Engineering, R&D, Customer focused roles including Marketing and Strategy. His current focus is in efforts to drive adoption of new storage technology as a Director of Strategic Planning at Solidigm. He has been a key figure in promoting SNIA as a second term Board member and leading the computational storage efforts as a co-chair of the SNIA Technical Working Group. He participates in several industry efforts like Open Compute, NVM Express and is seen as a subject matter expert in SSD technology and semiconductor design. He has and still speaks on the subject at events like the Open Compute Summit, Flash Memory Summit, SDC, and many other events, press interviews, blogs, and webinars. While at NGD Systems, Scott developed and managed the Computational Storage products and ecosystem. Scott previously managed the Product Marketing team at Micron, was the Business Line Manager for the SATA SSD portfolio, and was the Principal Technologist for the SSD and emerging memory portfolio. He launched four successful innovative SSDs for Micron and two for STEC, all of which were billion dollar programs. Scott earned a BSEE in Device Physics from Boise State University and an MBA in marketing from University of Phoenix.
Open CXLT-201-1: CXL Form Factors
Ballroom E, Floor 1
Track: CXL
Organizer + Chairperson:
Arthur Sainio, Director, Product Marketing, SMART Modular Technologies
Paper Presenters:
  • Andrew Mills, Snr Director Advanced Product Development, Smart Modular Technologies
  • Ron Swartzentruber, Director of Engineering, Lightelligence
  • Bill Gervasi, Principal Systems Architect, Wolley Inc
Session Description:
As CXL integration expands into large systems, the focus shifts to bringing CXL to embedded environments like motherboards. We’ll discuss how next-gen systems are using CXL's versatile interfaces for memory, storage, and accelerators. The session will also discuss the latest options for CXL memory expansion in X86 servers, both volatile and non-volatile, with a glimpse into future trends and optical connectivity advancements, with real-world examples. We will also take a look at the impact of optical CXL on datacenter architecture for AI and LLM processing, offering bandwidth and latency solutions for massive memory pooling applications.
About the Organizer + Chairperson:
Arthur Sainio is Director of Product Marketing at SMART Modular Technologies, where he leads efforts in new technologies such as persistent memory including MRAM and NVDIMMs. He has been a major promoter of persistent memory and NVDIMMs since they were first introduced. He has organized and presented sessions at Flash Memory Summit, Storage Developer Conference, and the SNIA Compute, Memory, and Storage Summit and has participated in many webinars and blogs. He is the co-chair of the Persistent Memory Special Interest Group within SNIA, which is focused on accelerating the awareness and adoption of persistent memory and creating new standards. Arthur was honored with the SNIA Exceptional Leadership Award in 2022. Before joining SMART Modular, Arthur was a product marketing manager at Hitachi Semiconductor. Arthur earned an MBA from San Francisco State University and an MS from Arizona State University.
Open DCTR-201-1: Enterprise Storage Part 1
Ballroom D, Floor 1
Track: Data Center Applications
Organizer:
Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft
Paper Presenters:
  • Patrick Chiu, Sr. Director, Product Management, Storage Systems, Super Micro Computer, Inc.
  • Tim Fisher, Flash Controller HW Lead, IBM
  • Odie Killen, VP Hardware Engineering, Viking Enterprise Solutions
Session Description:
With the rise of PCIe and advanced architecture in SSDs, distributed software architecture is transforming the way computational tasks are handled. By offloading tasks from the host system to SSDs, significant improvements in performance and efficiency can be achieved. For example, utilizing "File System in SSD" and "Database in SSD" showcases enhanced computational throughput and reduced latency. Furthermore, combining deduplication and compression at the SSD level can optimize storage utilization, performance, and cost in enterprise storage appliances. Join us for a panel discussion with industry experts to explore real-world case studies and applications of computational storage, highlighting the tangible benefits and future developments in this space.
About the Organizer:
Jonathan Hinkle is Senior Director - Azure Memory and Storage Pathfinding at Microsoft. He previously was In Micron's Storage Business Unit, where he investigated new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.
Open INVT-201-1: Invited Talk with Andrew Walls
GAMR 1 (Great America Meeting Room 1), Floor 2
Track: Invited Talks
Organizer + Chairperson:
Leah Schoeb, Sr. Developer Relations Manager, AMD
Paper Presenters:
  • Andrew Walls, IBM Fellow, CTO FlashSystem, IBM
Session Description:
QLC advances in layer count and therefore density will allow for large increases in SSD capacities in the near future. IBM has developed computational storage capabilities to provide data reduction on large capacities without huge controller and memory costs. Having this computational storage capability combined with large capacities will challenge the need and complexity for Nearline drives in all in enterprise storage. In this talk, Andy Walls will explain how this can truly reduce the TCO to the point where simple and extremely dense and power-efficient SSD arrays will eliminate the need to have a tier of Nearline HDDs.
About the Organizer + Chairperson:
Leah Schoeb is a Sr Developer Relations Manager in AMD's platform architecture team, where she engages with solid state storage vendors on storage technology futures. She has over 25 years of experience in the computer industry, and was previously Acting Director of Reference Architecture at Intel where she led a team of segment managers and architects managing cross functional teams for flash- and NVMe-based data solutions. Leah has held management and engineering positions at VMware, Dell, and Sun Microsystems, and was also a Senior Partner at the analyst firm Evaluator Group, where she focused on storage, virtualization, and cloud infrastructure. Leah has ten technical publications, and has presented at many technical conferences. Her MBA us from the Univ. of Phoenix, and heer BSEE is from the Univ. of Maryland, College Park.
Open OMEM-201-1: Emerging Memories
Ballroom C, Floor 1
Track: Other Memory Technologies
Organizer + Chairperson:
Dave Eggleston, Sr Business Development Manager, Microchip Technology
Paper Presenters:
  • Amir Regev, CTO, Weebit-nano
  • James Pan, Senior Principal Engineer Project Manager, Northrop Grumman
  • Manus Hayne, Chief Technology Officer, Quinas Technology
  • Jim Handy, General Director, Objective Analysis
Session Description:
In this session, we discuss emerging memories. Ultra-High Speed Photonic NAND FLASH technology revolutionizes memory operations by achieving ultra-high speeds with lower voltages and power consumption. This technology combines vertical NAND FLASH transistors with lasers/LEDs and photon sensors for efficient READ operations. ReRAM is now mainstream in applications such as automotive and edge AI due to its low power, scalability, and resilience to environmental conditions. We will explore the technology enhancements needed for wider adoption and the latest developments in advanced processes. ULTRARAM boasts exceptional properties like energy efficiency and extreme temperature tolerance, making it ideal for space and high-performance computing applications. We will highlight progress in fabrication processes and potential applications. Finally, we will discuss life beyond flash and the future of memory technologies like MRAM, ReRAM, PCM, and FRAM. Analysts will explore the impact on computer architectures, AI, and the memory market in the next 20 years, emphasizing the inevitability of transitioning to emerging memory types.
About the Organizer + Chairperson:
Dave Eggleston is Sr. Business Development Manager at Microchip. Dave's extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at SanDisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.
Open SPOS-201-1: NVMe 2.1 Specification, CXL Support & Windows Innovations NEW
Ballroom A, Floor 1
Track: Sponsored Sessions
Chairperson + Speaker:
Peter Onufryk, Fellow Data Center Solutions BU, Intel
Paper Presenters:
  • Bill Martin, Principal Engineer SSD I/O Standards, Samsung Electronics
  • Jason Molgaard, Principal Storage Solutions Architect, Solidigm
  • Scott Lee, Software Engineer Lead, Microsoft
Session Description:
NVMe technology has become synonymous with high-performance storage and with widespread adoption in client, cloud, and enterprise applications. Although initially developed for direct-attached PCIe SSDs, NVMe architecture is now widely used in both direct-attached and fabric-attached applications. This presentation provides an overview of the latest NVMe technologies, summarizes the NVMe standards roadmap, and describes new NVMe standardization initiatives. NVM Express (NVMe) Support for CXL As CXL becomes the memory interface protocol of choice, connecting CXL memory and NVMe Subsystem Local Memory (SLM) becomes critical. SLM allows access to memory on an NVMe device with NVMe commands. This memory is then used for the Computational Programs Command set. To improve performance and to enable new paradigms of Computational Programs, it is beneficial for the SLM to be able to be accessed using CXL. NVMe Host Addressable SLM is being developed to allow the mapping of SLM to the Host Physical Memory Address space using Host-Managed Device Memory (HDM) addressing. This presentation will bring you up to speed on where this development effort is. NVMe Innovations in Windows The session will provide updates on Windows support of the NVMe family of specifications providing information on new features available and guidance to the industry on how best to work with some existing and new features planned in the areas of device power and device reliability.
About the Chairperson + Speaker:
Peter is an Intel Fellow in the Design Engineering Group at Intel. He has been active in NVMe standardization as an NVMe Board Member, NVMe Management Workgroup Chair, and NVMe Technical Workgroup Chair. Peter holds over 40 patents and has written several published articles and books. Before Intel, Peter was a Fellow in the Data Center Solutions business unit at Microchip responsible for storage product architecture. He was previously Director of Engineering at Integrated Device Technology (IDT) and a research staff member at AT&T Bell Labs. Peter earned a Ph.D. in Electrical and C
09:45 AM to 10:50 AM
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PRO ASIA-202-1: Asia Memory and Storage Markets Part 2
Ballroom F, Floor 1
Track: Asia Memory and Storage Markets
Organizer:
Janet Liu Erickson, Project Manager, Sage Micro
Paper Presenters:
  • Mark Liu, Research Manager, TrendForce Corp.
  • Jianjun (Jerome) Luo, President, Sage Microelectronics
  • Jonathan Chou, Product Marketing Manager, Silicon Motion
Session Description:
In the ever-evolving landscape of the Server market, the impact of AI cannot be overstated. Our analysis dives deep into the dynamic interplay between AI and Server/CSP manufacturers, forecasting how Server DRAM prices will ebb and flow in response to market forces. With a laser focus on strategic implications, we outline supplier strategies, capacity adjustments, and growth forecasts that will shape the Server DRAM market in 2025 and beyond. This strategic roadmap is essential for stakeholders looking to navigate the complexities of AI's influence on the Server market with confidence and clarity. The rise of AI technologies, spearheaded by advancements like ChatGPT, has revolutionized the SSD markets in Asia at an unprecedented pace. As generative imagery continues to drive demand for high-speed, high-capacity portable SSDs, we anticipate a surge in uptake across the region. Our analysis delves into the current applications of portable SSDs, offering insights into market trends and localization strategies tailored for the Asian market. As the SSD landscape continues to evolve in the wake of AI innovation, stakeholders can leverage these insights to capitalize on emerging opportunities and stay ahead of the curve.
About the Organizer:
Janet Liu Erickson is a project manager at Sage Microelecronics.
PRO CLDS-202-1: Cloud Software
Ballroom B, Floor 1
Track: Cloud Storage and Applications
Organizer:
Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft
Paper Presenters:
  • Dmitry Livshits, CEO, Xinnor
  • Sujit Somandepalli, Principal Storage Solutions Enginee, Micron Technology
  • Wojciech Malikowski, Software Engineer, Solidigm
  • Dan Helmick, NVMe SSD Interface Architect, Samsung Electronics
Session Description:
Distributed Erasure Coding for NVMe SSDs in a Virtualized Cloud Infrastructure introduces a new approach to storage software cache, addressing common technical problems such as write amplification factor and cache fragmentation. Cloud Storage Acceleration Layer (CSAL) using append cache offers advantages such as faster data lookup and reduced WAF. Quantifying Power Efficiency with Real Workloads in the Data Center discusses methodologies for measuring power consumption in data centers to improve efficiency. SSD Implementation of Live Migration explores the PCIe infrastructure for live migration, emphasizing the need for reliable and compliant SSD implementations to meet the standards set by NVMe. The presentation highlights concerns and differences in implementation for NVMe-oF systems
About the Organizer:
Jonathan Hinkle is Senior Director - Azure Memory and Storage Pathfinding at Microsoft. He previously was In Micron's Storage Business Unit, where he investigated new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.
PRO COMP-202-1: Computational Storage Futures NEW
Ballroom G, Floor 1
Track: Computational Storage
Organizer:
Scott Shadley, Strategic Planner, Solidigm
Paper Presenters:
  • Nilesh Shah, VP, Business Development, ZeroPoint Technologies
  • David McIntyre, Director Product Planning, Samsung Electronics
  • John Li, VP of Marketing and Operations, DapuStor
Session Description:
As data centers strive for improved performance and efficiencies, computational storage has emerged as a solution with advancements in CXL memory and in-memory compute. This session delves into architecture developments and application use cases, such as data analytics and database performance enhancements. Design considerations for deploying computational storage in data center infrastructures will be discussed, along with application development and integration from a software perspective. With the demand for terabytes of data in Generative AI and cloud-native applications, new storage and memory compression technologies are being explored. We will discuss industry responses that include process node shrink and new form factors to process data at scale. We will also examine how the impact of garbage collection on flash-based SSDs is being mitigated and more efficient approach leveraging compression ratios as data features and customized clustering methods, automatic and host-transparent stream management which can achieve improved performance without host dependencies.
About the Organizer:
Scott Shadley has spent over 25 years in the semiconductor and storage space. He has time in Production, Engineering, R&D, Customer focused roles including Marketing and Strategy. His current focus is in efforts to drive adoption of new storage technology as a Director of Strategic Planning at Solidigm. He has been a key figure in promoting SNIA as a second term Board member and leading the computational storage efforts as a co-chair of the SNIA Technical Working Group. He participates in several industry efforts like Open Compute, NVM Express and is seen as a subject matter expert in SSD technology and semiconductor design. He has and still speaks on the subject at events like the Open Compute Summit, Flash Memory Summit, SDC, and many other events, press interviews, blogs, and webinars. While at NGD Systems, Scott developed and managed the Computational Storage products and ecosystem. Scott previously managed the Product Marketing team at Micron, was the Business Line Manager for the SATA SSD portfolio, and was the Principal Technologist for the SSD and emerging memory portfolio. He launched four successful innovative SSDs for Micron and two for STEC, all of which were billion dollar programs. Scott earned a BSEE in Device Physics from Boise State University and an MBA in marketing from University of Phoenix.
Open CRER-202-1: Career Strategies Part 1
GAMR 1 (Great America Meeting Room 1), Floor 2
Track: Career Strategies
Session Description:
Description Not Available
PRO CXLT-202-1: CXL Memory Pooling
Ballroom E, Floor 1
Track: CXL
Organizer + Chairperson:
Anil Godbole, Xeon CXL Strategy & Marketing Manager at Intel Corporation, Intel
Paper Presenters:
  • Jianping Jiang, VP, Xconn Technologies
  • Brian Pan, General Manager, H3 Platform
  • Jungmin Choi, Memory System Architect, SK hynix
  • Sanjay Goyal, Sr Technical Dir, Rambus
Session Description:
In the quest to reduce memory costs in server/datacenter operations, pooling and sharing of memory have emerged as viable solutions. By utilizing mechanisms like MH-SLD and MLD provided by CXL 3.1, organizations can optimize memory utilization and minimize data movement expenses. This session will examine the benefits of MH-SLD over MLD for initial CXL device deployment, particularly focusing on the efficiency of dynamic memory allocation using DCD features. Additionally, a detailed look at the implementation of a CXL memory pooling system and its performance study will be showcased, revealing insights on memory expansion, pooling, and sharing within a multi-host environment.
About the Organizer + Chairperson:
Anil is Xeon CXL Strategy & Marketing Manager at Intel Corporation.
PRO OMEM-202-1: Memory for AI - Solutions
Ballroom C, Floor 1
Track: Other Memory Technologies
Organizer:
Dave Eggleston, Sr Business Development Manager, Microchip Technology
Paper Presenters:
  • Jack Guedj, CEO, Numem
  • Simone Bertolazzi, Technology and Market Analyst, Yole Intelligence
  • Geraldo Francisco De Oliveira Junior, PhD Candidate, ETH Zurich
Session Description:
This session will discuss solutions for memory in AI, and how they address the exponential growth in high-performance memory capacity, reduce power consumption and memory density while lowering total cost of ownership. We will discuss tools and system support for processing-in-memory architectures, aiming to ease the adoption of PIM in current and future systems. Lastly, we will overview emerging non-volatile memory markets and technologies, highlighting the challenges and opportunities for mass adoption in embedded applications.
About the Organizer:
Dave Eggleston is Sr. Business Development Manager at Microchip. Dave's extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at SanDisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.
Open SPOS-202-1: SNIA: The Future of Data and Storage Technologies NEW
Ballroom A, Floor 1
Track: Sponsored Sessions
Organizer + Chairperson:
Richelle Ahlvers, Storage Technology Enablement Architect, Intel
Paper Presenters:
  • Jason Molgaard, Principal Storage Solutions Architect, Solidigm
  • Dave Landsman, Director of Industry Standards, Western Digital
  • Eric Hibbard, CISSP, FIP, CISA, Director, Product Planning – Security, , Samsung Semiconductor, Inc.
Session Description:
As the world both produces and consumes more data, SNIA is investigating technologies and developing standards to support and manage the proliferation of data, and the storage infrastructure it sits in. With the rapid explosion in data density, we need much more efficient ways to store data; DNA data storage looks at mimicking the efficiency of DNA to store user-generated data. With the increase of shared memory and memory at the edge, there is a need to minimize movement of data from that disaggregated memory to the host. Computational memory investigates how to perform compute in or near that memory. While the technologies in the systems integrate increasingly complex protection technologies (ala post-quantum cryptography), data protection, privacy and security concerns continue to grow. There is still much work to do to ensure secure systems.
About the Organizer + Chairperson:
Richelle Ahlvers serves as Vice Chair on the Board of Directors of the Storage Networking Industry Association (SNIA). Richelle has been engaged with industry standards initiatives with SNIA and DMTF for many years. She served as the SNIA Technical Council Chair and has been engaged across a breadth of technologies ranging from storage management to solid state storage, cloud, and green storage. She is currently Chair of the SNIA Storage Management Initiative. At Intel, Richelle is a Storage Technology Enablement Architect, where she promotes and drives enablement of new technologies and standards strategies. She has spent over 25 years in Enterprise Storage R&D teams in a variety of technical roles, leading the architecture, design and development of storage array software, storage management software user experience projects including mobility, developing new storage industry categories including SAN management, storage grid and cloud, and storage technology portfolio solutions.
PRO SUST-202-1: Sustainable Data Centers and Energy Efficiency
Ballroom D, Floor 1
Track: Sustainability
Organizer:
Wayne Adams, SNIA Chairman Emeritus, SNIA
Paper Presenters:
  • Qingru Meng, Principal Engineer, Solidigm
  • Toru Tanzawa, Professor, Shizuoka University
  • Satvik Vyas, Strategic Marketing Manager for SSDs, KIOXIA America, Inc
Session Description:
In the realm of NAND Flash Design, ensuring a 30% reduction in power consumption is critical for the sustainability of data centers. In this session, we examine a number of methods to achieve this goal while maintaining compatibility with existing NAND interfaces, including plug-in designs, controller scalability, optimizing power consumption, and offloading data scrubbing.
About the Organizer:
Wayne Adams has over 35 years of IT industry experience spanning business development, technical product/solution management, and partner ecosystems. Wayne has been involved in SNIA leadership roles since 2002. Wayne has served on the SNIA Board of Directors since 2003 including roles as Chair, Chair Emeritus, Treasurer in addition to a number of leadership roles for forums and initiatives, conferences, and strategic alliances. He has spoken at numerous industry forums and events. Over his career, Wayne M. Adams was a Senior Technologist and Director of Standards within the Office of the CTO at EMC, technical alliances partner manager, and a manager of product managers for its portfolio of SRM products. Prior to EMC, Wayne was responsible for product marketing and business development for several strategic software and hardware products at Digital Equipment Corporation. He started his high-tech career at Eastman Kodak as a system designer of real-time control systems. Wayne has been involved in many industry associations including serving on the DMTF Board of Directors, serving as Advisory Committee member of W3C, contributing to the Industrial Internet Consortium for IoT/big data test-beds, leadership of the Fibre Alliance, and participating with various committees within INCITS, OASIS, Cloud Security Alliance, and TheGreenGrid. Wayne holds a Bachelor of Science degree with a dual major in Computer Science and Mathematics from the University of Pittsburgh.
11:00 AM to 11:30 AM
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Open Keynote 8: Micron
Mission City Ballroom, Floor 1
Track: FMS 2024 Keynotes
Session Sponsor:
Micron Technology
Speakers:
  • Raj Narasimhan, Senior VP and GM, Compute & Networking Business Unit, Micron
Session Description:
In the rapidly evolving landscape of AI, data drives our insights, decisions, and innovations. This keynote will highlight the key role that Micron storage and memory play in this dynamic ecosystem, starting with the data center's role in enabling AI. As AI applications expand into every corner of our lives, they will rapidly exceed the confines of the data center to the edge - the car, the PC, the phone, and beyond – to deliver amazing real-time user experiences. Edge devices, equipped with advanced storage and memory capabilities, are playing a crucial role in bringing AI to the real world. We will explore how Micron’s leading technologies – such as HBM3E, high-capacity DDR5 DIMMs, high-performance NVMe™ SSDs, and high-capacity SSDs – are revolutionizing data center architectures, enabling faster, more power efficient ingestion, processing and analysis of vast data volumes. Join us as we look at Micron’s memory and storage innovation from cloud to edge and explore how AI is integrating seamlessly into our lives – enriching our future.
11:30 AM to 11:40 AM
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Open Special Presentation: SuperWomen of FMS Leadership Award
Mission City Ballroom, Floor 1
Track: FMS 2024 Special Sessions
Session Sponsor:
Evaluator Group
Session Description:
The SuperWomen of FMS Leadership Award recognizes women who have shown outstanding leadership in the growth, development and use of flash memory and associated or related technologies and systems. The previous awards recognized Amy Fowler, VP and GM of FlashBlade Pure Storage, Amber Huffman, Intel Fellow, Calline Sanchez, IBM Vice President, Barbara Murphy, VP WekaIO and Dr. Yan Li, VP Western lDigital. This special presentation will recognize the 2024 winner.
11:40 AM to 12:10 PM
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Open Keynote 9: Silicon Motion
Mission City Ballroom, Floor 1
Track: FMS 2024 Keynotes
Session Sponsor:
Silicon Motion
Speakers:
  • Gary Adams, Associate VP of Enterprise Marketing, SMI
  • Robert Fan, President of Silicon Motion, Inc., USA, Silicon Motion
Session Description:
Artificial Intelligence is driving the implosion of data usage. Whether data is used for training or inference, it needs to be processed, secured, and stored. For both the Cloud and the Edge, AI will require high capacity, high performance, and low power characteristics of NAND storage as well as the cost-effectiveness of QLC NAND. In the coming years, new categories of AI servers, AI PCs, and AI smartphones will drive device growth. AI servers, AI PCs, and AI Smartphones will need the high performance of PCIe Gen 5 SSDs and UFS 4.0 solutions to optimize for AI storage performance. Silicon Motion, as a leading merchant supplier of SSD controllers and solutions, will discuss the current and future SSD controller innovations to address the evolving and unique requirements in cloud storage and edge devices and introduce how our latest technology and comprehensive product portfolio drive AI innovations in flash storage.
01:10 PM to 01:40 PM
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Open Keynote 10: Phison
Mission City Ballroom, Floor 1
Track: FMS 2024 Keynotes
Session Sponsor:
Phison Electronics Corp.
Speakers:
  • Chris Ramseyer, Director of Technical Marketing, Phison Electronics
  • Sebastien Jean, CTO, Phison Electronics
  • KS Pua, Chairman, Phison Electronics
Session Description:
Embark on an exclusive journey with K.S. Pua, Chairman and CEO of Phison Electronics Corp., as we unveil a new enterprise brand - Pascari. Phison enterprise emerges as a beacon of innovation within the industry, pioneering revolutionary storage technologies tailored for seamless integration into the forefront of next-generation data centers. Engineered with an unwavering commitment to efficiency, Pascari sets the standard for rapid deployment, ensuring optimal performance and operational excellence. Join us for a glimpse into the future of storage solutions. This presentation will also explore Phison's innovative utilization of NAND flash technology to effectively mitigate the challenge of exponential data expansion in AI training, particularly in developing large-language models. By harnessing the power of NAND flash, Phison empowers applications to achieve unprecedented milestones, enabling them to deliver responses from generative AI models that rival human-like capabilities.
01:40 PM to 01:50 PM
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Open Addressing Storage and Data Technology Challenges with Industry Standards
Mission City Ballroom, Floor 1
Track: FMS 2024 Special Sessions
Session Sponsor:
SNIA
Session Description:
Richelle Ahlvers, SNIA Vice Chair, will highlight the latest developments in standards-based technology trends in storage and data, and discuss how SNIA’s data-centric focus combined with their strong standards alliances help not only address today’s and tomorrow’s challenges, but accelerate solutions.
01:50 PM to 02:20 PM
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Open Keynote 11: Western Digital
Mission City Ballroom, Floor 1
Track: FMS 2024 Keynotes
Session Sponsor:
Western Digital
Session Description:
Description Not Available
02:20 PM to 02:50 PM
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Open Keynote 12: KOVE
Mission City Ballroom, Floor 1
Track: FMS 2024 Keynotes
Session Sponsor:
KOVE
Speakers:
  • Ian A. Hood, CTO/Chief Strategist, Red Hat
  • Thomas Zscharch, Chief Innovation Officer, SWIFT
  • Dr. John Overton, CEO, KOVE
Session Description:
Software-Defined Memory (SDM) addresses the next wave of memory solutions to address the challenges of the “memory wall”. It performs like local memory, scales linearly, and works on any hardware - right now. In this talk, Kove and Red Hat will show how Software-Defined Memory technology has arrived. Red Hat will illustrate technology and operational benefits based on empirical test results of Kove:SDM™ configured on Red Hat OpenShift application platform using StressNG, Intel P- States, and standard Supermicro server hardware. Our comprehensive test data shows power savings from 12-54%, near-local CPU performance, and superior performance from remote memory compared to local memory. We’ll show real world use cases in multiple industry sectors that demonstrate Kove’s pooled memory solution Kove:SDM™ working on existing infrastructure, with no code changes. We’ll close with a leading expert from Swift discussing how they are changing the game for preventing economic crime for their customers with Kove:SDM™, where the stakes couldn’t be higher.
03:00 PM to 04:05 PM
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PRO AIML-203-1: Generative AI
Ballroom B, Floor 1
Track: AI and ML Applications
Organizer:
David McIntyre, Director Product Planning, Samsung Electronics
Paper Presenters:
  • Prasad Venkatachar, Solutions Director, Pliops
  • John Lorenz, Senior Analyst, Yole Group
  • Assaf Sella, Senior Director Machine Learning R&D, KIOXIA
  • Vishwas Saxena, Technologist, Firmware Engineering, Western Digital
Session Description:
Generative AI has revolutionized the business and tech landscape, with Gen AI applications transforming industries like Retail, Fintech, and Insurance. This session explores the foundational elements of building a Gen AI application, from Prompt Engineering to Fine Tuning LLM models. Real world use cases in customer support, marketing, and HR will be discussed, showcasing the impact of generative AI across enterprise functions. On the hardware side, LLM acceleration presents challenges in computational and memory requirements, especially for edge computing. The session will explore innovative approaches to reduce GPU DRAM usage and system RAM, making LLMs more accessible on client PCs. Audience will also gain insights into memory trends and the booming HBM market in 2024.
About the Organizer:
David McIntyre focuses on computational storage acceleration solutions development and strategic business enablement for cloud to edge applications including AI inference/video analytics, database processing and blockchain networks. He has held senior management positions with IBM, Samsung, Xilinx, Intel (formerly Altera) and at Silicon Valley startups. He has consulted for institutional investors including Fidelity, Goldman Sachs and UBS. David is a frequent presenter and chairperson at the Flash Memory Summit and other technical conferences including SNIA.
Open CRER-203-1: Career Strategies Part 2
GAMR 1 (Great America Meeting Room 1), Floor 2
Track: Career Strategies
Panel Members:
  • Vincent Phipps, Chief Executive Officer & Owner of Communication VIP Training & Coaching, Communication VIP Training & Coaching
Session Description:
Description Not Available
PRO CXLT-203-1: CXL Memory Tiering
Ballroom E, Floor 1
Track: CXL
Organizer + Chairperson:
Anil Godbole, Xeon CXL Strategy & Marketing Manager at Intel Corporation, Intel
Paper Presenters:
  • Joergen Hansen, Sr. Technologist, Western Digital
  • Manzanares Adam, Senior Manager, Samsung Electronics
  • Divya Vijayaraghavan, Technical Lead, Intel Programmable Solutions Group
  • Andy Banta, Storage Janitor, Magnition IO
Session Description:
In this session, we dive into the fiery world of hot data detection for CXL memory, emphasizing the importance of understanding data placement in heterogeneous memory for optimal application performance. We discuss the significance of data and control plane separation in CXL memory, highlighting its load/store access capabilities and command-based interface for RAS features. Additionally, we examine memory compression within CXL memory controllers, and touch on use cases for CXL-based active memory tiering and near memory accelerators, shedding light on the challenges and expected performance metrics in implementing these innovative approaches.
About the Organizer + Chairperson:
Anil is Xeon CXL Strategy & Marketing Manager at Intel Corporation.
PRO OMEM-203-1: Heterogeneous Solutions for Performance
Ballroom C, Floor 1
Track: Other Memory Technologies
Organizer + Chairperson:
Dave Eggleston, Sr Business Development Manager, Microchip Technology
Paper Presenters:
  • Hieu Tran, Sr. Technical Fellow, Microchip Technology
  • Igor Sharovar, Chief Technology Officer, Truememorytechnology LLC
  • Norio Chujo, Senior Researcher, Hitachi Data Systems
  • Mark Webb, Analyst, MKW Ventures
Session Description:
This session will discuss heterogeneous Solutions for Performance. Chiplets and hybrid bonding have revolutionized the landscape of memory technologies, eliminating previous limitations and opening up new possibilities We will discuss how they are paving the way for innovative solutions that surpass our expectations from just a few years ago. We will also discuss breakthroughs in analog Compute-in-Memory, providing unparalleled efficiency for edge AI/ML Accelerators, and NVDIMM solutions for embedded systems utilizing DDR-4 and DDR5 memory interfaces to deliver unparalleled bandwidth up to 40GB/s. Finally we will examine a solution for near-memory computing that optimizes interconnectvity and power efficiency.
About the Organizer + Chairperson:
Dave Eggleston is Sr. Business Development Manager at Microchip. Dave's extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at SanDisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.
Open SPOS-203-1: NVMe Live Migration, High Availability & Event Notification NEW
Ballroom A, Floor 1
Track: Sponsored Sessions
Chairperson + Speaker:
Mike Allison, Sr. Director, Samsung Electronics
Paper Presenters:
  • Nicolae Mogoreanu, Staff Software Engineer, Google
  • Chaitanya Kulkarni, Director, NVIDIA
  • Austin Bolen, Account Coordinator, Nereus
  • Myron Loewen, Platform Architect in NVM Solutions Group, Intel
  • Klaus Jensen, Staff Engineer, Samsung Electronics
  • Lee Prewitt, Principal Hardware Program Manager, Microsoft
Session Description:
NVM Express Standardization of Live Migration Panel At FMS 2023, NVM Express outlined the work being done to standardize Live Migration. That work is complete and NVM Express has ratified Tracking LBA Allocation with Granularity and PCIe Infrastructure for Live Migration. This presentation details the new capabilities included in the NVM Express (NVMe) family of specifications that allow a host to seamlessly migrate a Virtual Machine (VM) and associated resources without affecting the user experience for use in data center load balancing and system maintenance. The presentation covers the migration of namespaces, tracking modifications to VM memory during the migration, and the migration of the controller. Manageability Adds High Availability and Event Notification The NVMe-MI workgroup added new features for High Availability and Asynchronous Event notifications to the NVM Express Management Interface Specification, Revision 1.3. This session will demonstrate how multiple BMCs can manage a dual-port NVMe storage device via SMBus/I2C. It will also demonstrate how BMCs can subscribe to receive asynchronous event notifications from NVMe storage devices to avoid costly polling.
About the Chairperson + Speaker:
Mike Allison is a Sr. Director in the Samsung DSA Product Planning and Business Enablement team focusing on standards for existing and future products. He has been a participating member of NVM Express since 2016, co-author of many technical proposals, chair of the NMVe Errata Task Group, Samsung alternate for the NVMe Board of Directors, and a represents the OCP Storage Project on the OCP Steering Committee. For over 38 years, Mike has been an embedded firmware engineer and architect working on systems and simulations for laser beam recorders, fighter aircraft, graphics cards, high end servers, and is now focusing on Solid State Drives. He holds 31 patents in graphics, servers, and storage. He has earned a BSEE/CS at University of Colorado, Boulder.
PRO SSDT-203-1: Performance Optimization & Modeling Techniques for SSDs
Ballroom F, Floor 1
Track: SSD Technology
Organizer:
Erich Haratsch, Senior Director Architecture, Marvell
Paper Presenters:
  • Eelin Tseng, Director, Enterprise SSD R&D HW, Silicon Motion
  • Jaehoon Shim, Student, Seoul National University
  • Gary Adams, Associate VP of Enterprise Marketing, SMI
  • Rakesh Nadig, Ph.D. Student, SAFARI Research Group at ETH Zurich
Session Description:
In the world of SSD performance enhancement, the implementation of multi-segment L2P table lookups with hardware acceleration is a game-changer. By optimizing memory access performance through L2P acceleration engines and cache controllers, the performance bottleneck caused by costly CPU cycles is effectively eliminated. Additionally, SSD IO performance shaping using multiple virtual functions enables user-defined QoS groups to achieve subscribed performance levels, maximizing IO traffic efficiency. This innovative approach empowers storage systems research and development with the introduction of NVMeVirt, a versatile tool for emulating various NVMe-based storage devices at the software level. Through the introduction of conflict-free accesses with Venice, SSD parallelism is significantly improved, leading to enhanced performance and energy efficiency.
About the Organizer:
Erich Haratsch is Senior Director Architecture at Marvell, where he leads the architecture definition for Bravera SSD controllers and other memory-based products. Prior to joining Marvell, he worked at Seagate and LSI, where he worked on Nytro and SandForce branded SSD controllers. Earlier in his career, he developed signal processing and error correction technologies for multiple generations of HDD controllers at LSI and Agere Systems. He started his career at AT&T and Lucent Bell Labs, where he worked on Gigabit Ethernet over copper, optical communications and the MPEG-4 video standard. He is the author of over 40 peer-reviewed journal and conference papers, and holds more than 200 U.S. patents. He also is a Senior Member of IEEE, and earned his MS and PhD degrees from the Technical University of Munich (Germany).
PRO SUST-203-1: Circular Economy for Storage
Ballroom D, Floor 1
Track: Sustainability
Organizer:
Wayne Adams, SNIA Chairman Emeritus, SNIA
Paper Presenters:
  • David Logue, Operations Manager | Lead Data Recovery Engineer, Ontrack
  • Jonmichael Hands, VP Storage, Chia Network
  • Shruti Sethi, Sr. PM, Microsoft
Session Description:
In a world where data is king, complying with evolving modern-day data sanitization and verification standards is crucial. With the growing cyber threats and regulations surrounding data protection, organizations must ensure complete data sanitization and verification to avoid costly breaches. This session will explore various methods of data sanitization for different storage media, the importance of third-party verification, and a real OEM case study on implementing and verifying a sanitization process. We will look at new futuristic storage solutions like a DNA data storage system. We will also discuss the Circular Drive Initiative (CDI) and its approach to data management in the ICT industry. Finally we will explore OCP's programs like S.A.F.E, L.O.C.K, and Caliptra that ensure data security and trust for enabling storage reuse. Join the movement towards sustainable practices that reduce e-waste and environmental impact while maintaining data security and longevity.
About the Organizer:
Wayne Adams has over 35 years of IT industry experience spanning business development, technical product/solution management, and partner ecosystems. Wayne has been involved in SNIA leadership roles since 2002. Wayne has served on the SNIA Board of Directors since 2003 including roles as Chair, Chair Emeritus, Treasurer in addition to a number of leadership roles for forums and initiatives, conferences, and strategic alliances. He has spoken at numerous industry forums and events. Over his career, Wayne M. Adams was a Senior Technologist and Director of Standards within the Office of the CTO at EMC, technical alliances partner manager, and a manager of product managers for its portfolio of SRM products. Prior to EMC, Wayne was responsible for product marketing and business development for several strategic software and hardware products at Digital Equipment Corporation. He started his high-tech career at Eastman Kodak as a system designer of real-time control systems. Wayne has been involved in many industry associations including serving on the DMTF Board of Directors, serving as Advisory Committee member of W3C, contributing to the Industrial Internet Consortium for IoT/big data test-beds, leadership of the Fibre Alliance, and participating with various committees within INCITS, OASIS, Cloud Security Alliance, and TheGreenGrid. Wayne holds a Bachelor of Science degree with a dual major in Computer Science and Mathematics from the University of Pittsburgh.
PRO TEST-203-1: Testing NVMe Devices
Track: Testing and Performance
Organizer:
Christopher Cox, Fellow, AMD
Paper Presenters:
  • Swati Chawdhary, Senior Manager, Samsung Electronics
  • Kiran Bhat, Product Marketing Engineer, Solidigm
  • Aldo Cometti, Strategic Advisor, NplusT
  • Carter Snay, Technical Manager, UNH-IOL
Session Description:
There are a variety of approaches to test NVMe devices. Reliability Testing of Emerging NVMs: We look at the challenge of measuring reliability, endurance, and understanding characteristics of emerging non-volatile memory technologies to shorten time-to-results while ensuring high-quality technology data. We delve into the process of developing new tests for the latest NVMe features, such as computational storage. We discuss an NVMe/NVMe-oF Compliance Test Platform offering a cost-effective, pluggable solution. We explore the importance of optimizing SSD storage for AI and ML applications by understanding the AI and ML pipeline, workload characteristics, and data requirements.
About the Organizer:
Christopher Cox is a Fellow at AMD. Previously he was the Vice President of Technology at Montage Technology. Prior to joining Montage, he was with Intel for over 21 years focused primarily on Memory Architecture with previous time at 3Dfx and AMD. Cox is currently the JEDEC JC42 (All Memories) Committee Chair, the CXL Consortium’s DRAM Subcommittee Chair and is on the Board of Directors for JEDEC and RangerRoad.org (a non-profit disabled veterans’ organization). He has been in the semiconductor industry for about 30 years, including some time in the U.S. Air Force. He holds over 170 issued and pending patents.
04:00 PM to 06:15 PM
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Open SuperWomen at FMS Reception
Evolution Courtyard, Floor 1
Track: Sponsored Sessions
Session Sponsor:
SK hynix and KIOXIA
Session Description:
Join industry leaders at the SuperWomen at FMS Reception sponsored by SK hynix and KIOXIA, celebrating the successes of women in the memory and storage sector, while also advocating for increased female participation in this dynamic field. This event, and other industry activities at FMS24 foster a diverse community interested in advancing the role of women in memory and storage technology.
07:15 PM to 09:00 PM
No search results found in this timeslot.
Open FMS 2024 Chat with the Experts
Ballroom A-D, Floor 1
Track: FMS 2024 Special Sessions
Session Description:
This popular annual session at FMS is your chance to network in person with industry leaders in the major technology segments influencing the future of memory and storage. Come prepared with your questions, grab some food and beverage, and find a table or tables that meet your interests!
08:30 AM to 09:35 AM
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Open BMKT-301-1: AI and Storage
GAMR 1 (Great America Meeting Room 1), Floor 2
Track: Business Strategies and Memory Markets
Organizer + Moderator:
Jean Bozman, President, Cloud Architects Advisors
Paper Presenters:
  • Glenn Fuller, Sr. Director of Software Engineering, Viking Enterprise Solutions
  • Jin Kim, CEO, MetisX
  • Vince Chen, Director of Solution Architecture, Super Micro Computer, Inc.
  • Frank Kung, Senior Analyst, TrendForce Corp.
  • Jeff Yang, Director, Silicon Motion
Session Description:
This session begins by examining the complexity of achieving high performance on a single NAND package for AI applications, addressing noise issues and latency concerns. We will explore innovative solutions to the Memory Wall problem in AI Data Centers, showcasing the benefits of CXL Computational Memory in optimizing data processing. We’ll dive into market forecasts and the growing trend of self-developed AI chips by major CSPs. Finally, we will offer insights into optimizing AI solutions for small to medium-sized enterprises, and discuss storage solutions for accelerating AI data pipelines.
About the Organizer + Moderator:
Jean S. Bozman is President of Cloud Architects Advisors, a market research and consulting firm focused on hardware and software for enterprise and hybrid multi-cloud computing. She analyzes the markets for servers, storage, and software related to datacenters and cloud infrastructure. A highly-respected IT professional, she has spent many years covering the worldwide markets for operating environments, servers, and server workloads. She was a Research VP at IDC, where she focused on the worldwide markets for servers and server operating systems. She is a frequent conference participant as a speaker, chairperson, and organizer at such events as Flash Memory Summit, OpenStack, and Container World. She is often quoted in a variety of publications including BusinessWeek, Investor’s Business Daily, the Los Angeles Times, CNET, Bloomberg, and Reuters. Ms. Bozman has also been VP/Principal Analyst at Hurwitz and Associates and Sr Product Marketing Manager at Sandisk. She earned a master’s degree from Stanford.
Open COLD-301-1: Archive Market Trends, Applications and Technology Solutions Part 1
Ballroom B, Floor 1
Track: Cold Data
Organizer + Chairperson:
Rich Gadomski, Head of Tape Evangelism, FUJIFILM Recording Media USA
Paper Presenters:
  • Alistair Symon, Vice President, Storage System Development, IBM Storage
  • John Monroe, , Further Market Research
  • Lee Prewitt, Principal Hardware Program Manager, Microsoft
  • Dave Landsman, Director Standards Group, Western Digital
Session Description:
Despite a downturn in demand, the active installed base of data continues to grow exponentially. With the majority of data becoming "cool" or "cold" within 60 days of creation, there is a pressing need for more sustainable, immutable, and secure storage solutions. This session will provide a futures outlook and challenges facing the enterprise data storage industry. Tape storage has seen a resurgence due to its security, low CO2 emissions, and cost efficiency, making it a key technology for storing cold data. HDDs remain vital in the face of increasing archival storage demand, with technical advancements driving growth and efficiency. Finally, we will discuss valuable insights from an end user perspective on the evolving archive market trends, applications, and technologies.
About the Organizer + Chairperson:
As Head of Tape Evangelism for FUJIFILM Recording Media U.S.A., Inc., Rich is responsible for driving industry awareness and end user understanding of the purpose and value proposition of modern tape technology. Rich joined Fujifilm in 2003 as Director of Product Management, Computer Products Division, where he oversaw marketing of optical, magnetic, and flash storage products.
Open CXLT-301-1: CXL Use Cases
Ballroom E, Floor 1
Track: CXL
Paper Presenters:
  • Arun Bosco, Associate Director, Samsung Semiconductor India Research
  • Jim Handy, General Director, Objective Analysis
  • Mahinder Saluja, Director, SSD Strategy, KIOXIA
  • Brian Morris, Platform memory technology lead, Google
Session Description:
The exciting world of CXL continues to evolve, with advancements in GenZ, CCIX, and OpenCAPI being incorporated into CXL specifications. But where is this technology headed? This session will provide valuable insights on the practical applications of CXL, from its core purpose to the needs of potential users, culminating in a forecast of CXL adoption and its impact on future computing architectures. We will also explore the potential of CXL in memory expansion and flash memory applications, offering cost-effective solutions for scaling memory capacity and enhancing performance in AI use cases.
Open DSEC-301-1: AI/ML Attacks Ransomware
Ballroom D, Floor 1
Track: Data Security/Ransomware Protection
Organizer + Chairperson:
Camberley Bates, VP and Practice Lead, Futurum Group
Panel Members:
  • Eric Herzog, Chief Marketing Officer, Infinidat
  • Dejan Kocic, Sr Systems Engineer, NetApp
  • Roman Pletka, Research Staff Member, IBM Research
Session Description:
Yes, AI / ML is a boon to the bad guys, but it is also a lever for the good guys to implement. In this session three leading systems providers will outline how and where they are using ML/AI to thwart the cyber criminals
About the Organizer + Chairperson:
Camberley serves as the VP and Practice Lead at The Futurum Group bringing over 25 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm. She joined The Futurum Group through their acquisition of Evaluator Group in 2023. As the Managing Director at Evaluator Group from 2009 until 2023 she built a highly respected team, known for its deep technical expertise delivering competitive and market knowledge backed by data based economic and hands-on experience with the technology and IT consulting services. Camberley began her career at IBM in sales and management. She holds a BS degree in International Business from California State University - Long Beach and executive certificates from Wellesley and Wharton School of Business.
Open NETC-301-1: Networking Flash Based Storage for AI
Ballroom F, Floor 1
Track: Networks and Connections
Organizer + Chairperson:
Rob Davis, VP Storage Technology - Networking Business Unit, NVIDIA
Paper Presenters:
  • CJ Newburn, HPC Lead, NVIDIA
  • Al Yanes, STSM, PCI-SIG
Session Description:
For networked flash storage in AI, high capacity, performance, and low latency are crucial to support data ingestion and training stages. This session explores key PCIe benefits for AI/ML, including low-power modes and security features like Integrity and Data Encryption. The upcoming PCIe 7.0 specification (targeting 128 GT/s) provides a clear growth path for AI chipset vendors and developers. We will discuss how the PCIe Specification offers a high bandwidth interconnect solution for AI and ML applications, allowing developers to build accelerators regardless of ASIC technology. With PCIe technology, developers can add AI accelerators in servers using various form factors for high or low power needs We will also discuss various protocols, networks, security, and scaling of storage capacity, including how accelerating GPU access to networked flash datasets requires support for fine-grained GPU accesses and secure storage technologies to prevent attacks.
About the Organizer + Chairperson:
Rob Davis is Vice President of Storage Technology at NVIDIA where he focuses on ways to apply their high-speed interfaces (such as 40G and 100G) to storage systems. Over the last two years he has moved NVIDIA into a leadership position in NVMe over Fabrics. As a technology leader and visionary for over 35 years, he has been a key figure in the development of an entire generation of storage networking products. Davis was previously VP/CTO at QLogic, where he drove development and marketing of Fibre Channel, Ethernet, and InfiniBand technology into new markets such as blade servers. Before joining QLogic, Davis worked at Ancor Communications, where he drove development and marketing of Fibre Channel and InfiniBand products. Davis’ areas of expertise include virtualization, Fibre Channel, InfiniBand, RoCE (remote DMA over converged Ethernet), and NVMe.
Open OPSW-301-1: Linux Mainline Project Status
Ballroom C, Floor 1
Track: Open Source Software
Organizer:
Javier Gonzalez, Principal Software Engineer, Samsung Electronics
Paper Presenters:
  • Ben Walker, Principal Software Engineer, NVIDIA
  • Keith Busch, Software Engineer, Meta
  • Jim Harris, Principal Engineer, Samsung
Session Description:
The Storage Performance Development Kit (SPDK) remains a cornerstone of the open source storage software landscape. In this session, we will delve into the latest advancements within SPDK, with a particular emphasis on its application in DPU use cases and offloading accelerators. As the demand for distributed storage solutions grows, DPUs have emerged as a key technology for offloading infrastructure tasks and enhancing network security. We will explore the development of an open software framework, inspired by the success of SPDK, that empowers users to customize and extend DPU devices We will also examine the evolution of the Linux NVMe driver, with numerous enhancements and features being added. Join us for an insightful overview of the latest developments across different transports supported by the Linux kernel.
About the Organizer:
Javier Gonzalez leads Samsung Memory Solutions' Global Open-Source Team (GOST), managing a distributed team of engineers who are focused on open-source software. He is the founder and site manager for Samsung Semiconductor Denmark Research (SSDR) -- which is Samsung’s Memory Solutions first R&D center in Europe and its fifth such center worldwide. Javier’s interests are centered in the hardware/software co-design space, where systems software, hardware architecture, and open-source meet. He contributes to a wide range of open- source projects, including the evolution of the Linux Kernel. He is a regular speaker at several top industry and academic conferences each year.
Open SPOS-301-1: UCI Express NEW
Ballroom A, Floor 1
Track: Sponsored Sessions
Session Description:
Description Not Available
Open TEST-301-1: Memory Device Testing
Ballroom G, Floor 1
Track: Testing and Performance
Organizer + Chairperson:
Christopher Cox, Fellow, AMD
Paper Presenters:
  • Erin Holley, Senior Member of Technical Staff, Introspect Technology
  • Haocong Luo, PhD Student, SAFARI Research Group at ETH Zurich
  • Seshu Madhavepeddy, CEO, Frore Systems
  • Shyam Sharma, Software Architect, Cadence Design Systems
Session Description:
In this session, we explore the new era of high-performance memory device testing solutions. We’ll address the unique challenges posed by GDDR7, from analog design trade offs to digital testing technologies. We discuss two open-source software infrastructure for DRAM simulation and testing to improve DRAM in all aspects and overcome DRAM scaling challenges, Experts will discuss rising to the challenges of AI accelerated computing on storage, memory, and thermal solutions. We will also examine high memory sub system level verification needs for protocol compliance of recent generation memory subsystems and solutions that extend to volatile and non volatile designs.
About the Organizer + Chairperson:
Christopher Cox is a Fellow at AMD. Previously he was the Vice President of Technology at Montage Technology. Prior to joining Montage, he was with Intel for over 21 years focused primarily on Memory Architecture with previous time at 3Dfx and AMD. Cox is currently the JEDEC JC42 (All Memories) Committee Chair, the CXL Consortium’s DRAM Subcommittee Chair and is on the Board of Directors for JEDEC and RangerRoad.org (a non-profit disabled veterans’ organization). He has been in the semiconductor industry for about 30 years, including some time in the U.S. Air Force. He holds over 170 issued and pending patents.
09:45 AM to 10:50 AM
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Open BMKT-302-1: CTO Panel
GAMR 1 (Great America Meeting Room 1), Floor 2
Track: Business Strategies and Memory Markets
Panel Members:
  • Greg Lavender, , Intel
  • Rita Wouhaybi, AI Fellow, Solidigm
  • Manoj Wadekar, Hardware System Technologist, Meta
  • Paul Borrill, Founder and CTO, Daedaelus
  • Bijan Nowroozi, CTO, OCP
  • Steve Scott, Corporate Fellow Network & Systems Architecture at AMD, AMD
Session Description:
CTOs and their staff do not have an easy life in the flash memory industry. Things are changing rapidly, and the road ahead is almost impossible to discern or understand. So what are these people thinking currently? What do they see as basic trends that will determine the course of artificial intelligence, memory technology, and storage? And what do they think are just transient issues that will soon be forgotten? What prized techniques can they recommend for gauging the future?
PRO COLD-302-1: Archive Market Trends, Applications and Technology Solutions Part 2
Ballroom B, Floor 1
Track: Cold Data
Organizer + Chairperson:
Rich Gadomski, Head of Tape Evangelism, FUJIFILM Recording Media USA
Paper Presenters:
  • Shashidhar Joshi, Principal PM, Microsoft
  • Olivier Lauvray, CTO, Biomemory
  • Steffen Hellmold, Director, Cerabyte, Inc.
Session Description:
In this new session to FMS24, we will look at archive applications and technology solutions. Ceramic nano memory is a cutting-edge storage technology revolutionizing the AI Storage Dataverse, addressing the growing demand for sustainable and cost-effective data storage solutions. Concurrently, advancements in archive/cold data storage landscape and emerging technologies like silica are paving the way for even greater storage efficiency and scalability. Biomemory, on the other hand, is pushing DNA Data Storage beyond traditional cold storage applications, revolutionizing the way data is stored and accessed in data centers.
About the Organizer + Chairperson:
As Head of Tape Evangelism for FUJIFILM Recording Media U.S.A., Inc., Rich is responsible for driving industry awareness and end user understanding of the purpose and value proposition of modern tape technology. Rich joined Fujifilm in 2003 as Director of Product Management, Computer Products Division, where he oversaw marketing of optical, magnetic, and flash storage products.
PRO CXLT-302-1: CXL AI Implications NEW
Ballroom E, Floor 1
Track: CXL
Paper Presenters:
  • David McIntyre, Director Product Planning, Samsung Electronics
  • Khurram Malik, Director of Product Marketing, Marvell
  • Harry Kim, CPO, MetisX
Session Description:
In the world of AI and data systems, the key to unlocking peak performance lies not in sheer computational power, but in the balance of memory capacity and bandwidth. The advent of Compute Express Link (CXL) technology offers a groundbreaking solution to this challenge, ushering in a new era of data-centric computing. With CXL, data center infrastructure can be optimized for maximum efficiency, reducing the strain on processor complexes and networks. The benefits are clear: improved performance, resource utilization, and power efficiencies, ultimately leading to lower operating costs. Thios session will delve into the transformative potential of CXL technology and its ability to revolutionize memory and computing in AI and data systems.
PRO DSEC-302-1: Cryptographic Keys/Quantum Cryptography
Ballroom D, Floor 1
Track: Data Security/Ransomware Protection
Organizer + Chairperson:
Camberley Bates, VP and Practice Lead, Futurum Group
Paper Presenters:
  • Dan Helmick, NVMe SSD Interface Architect, Samsung Electronics
  • Jeff Andersen, Staff Software Engineer, Google, LLC
Session Description:
This session will explore some of the latest approaches for locking down devices and systems. No single approach to security is enough, especially as the finish line seems to move each time we get closer. And, we are facing advanced systems that will be able to crack the codes we have used in the past. Hear from some leading technologist on what they are doing to address the hardened systems.
About the Organizer + Chairperson:
Camberley serves as the VP and Practice Lead at The Futurum Group bringing over 25 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm. She joined The Futurum Group through their acquisition of Evaluator Group in 2023. As the Managing Director at Evaluator Group from 2009 until 2023 she built a highly respected team, known for its deep technical expertise delivering competitive and market knowledge backed by data based economic and hands-on experience with the technology and IT consulting services. Camberley began her career at IBM in sales and management. She holds a BS degree in International Business from California State University - Long Beach and executive certificates from Wellesley and Wharton School of Business.
PRO NETC-302-1: NVMe over Fabrics Is Everywhere
Ballroom F, Floor 1
Track: Networks and Connections
Chairperson:
John Kim, Director of Storage Marketing, NVIDIA
Paper Presenters:
  • Orit Wasserman, Distinguished Engineer, IBM
  • Mahinder Saluja, Sr. Specialist, Outbound Marketing, KIOXIA
  • Mark Miquelon, Partner Alliance Director, Western Digital
  • Odie Killen, VP Hardware Engineering, Viking Enterprise Solutions
Session Description:
Join us for a technical deep dive into the groundbreaking advancements in open-source storage with Ceph and its NVMe-oF target. This session will explore the seamless integration of Ceph clusters with industry-standard protocols like NVMe-oF, revolutionizing data storage efficiency. Delve into the architectural decisions behind this integration, learn about the implementation challenges faced, and discover the key considerations for achieving high availability and exceptional performance. Additionally, gain insights into the widespread adoption of NVMe-oF as a universal host interface scheme, the benefits of offloading data redundancy computation to SSDs, and the latest developments in Ethernet-attached SSDs and HDDs technology for AI applications and beyond. Don't miss this opportunity to expand your knowledge and push the boundaries of storage capabilities.
About the Chairperson:
John KIm is Director of Storage Marketing at NVIDIA
PRO OPSW-302-1: Databases
Ballroom C, Floor 1
Track: Open Source Software
Paper Presenters:
  • Brian Carrig, Sr Program manager, Microsoft
  • Prasad Venkatachar, Solutions Director, Pliops
  • Hao Wu, Software Engineer, Meta
  • Arun George, Senior Staff Engineer, Samsung Electronics
Session Description:
In this session we explore a variety of databases that address multi-tenant caching challenges, incorporate Flexible Data Placement (FDP) with NVMe technology, and offer better performance and isolation among tenants sharing the same SSD. We will also discuss solutions that target database acceleration strategies for performance scaling and QoS requirements. Lastly, the session will look at how Microsoft SQL Server continues to evolve with advancements in memory and flash storage technologies like PMEM and SLC flash.
Open SPOS-302-1: JEDEC Session Highlighting AI and LPDDR6 Developments at FMS 2024
Ballroom A, Floor 1
Track: Sponsored Sessions
Organizer + Moderator:
Hung Vuong, Director of Technical Standards, Qualcomm
Paper Presenters:
  • Manoj Wadekar, Hardware System Technologist, Meta
  • Eric Oh, LPDDR Product Planning Park Leader, Samsung Semiconductor
  • Howard David, Principal Technical Product Manager for Memory Interface IP, Synopsys
  • Frank Ross, Sr. Member Technical Staff, Micron Technology
Session Description:
JEDEC is the global standards organization that leads the development of the industry's memory standards including DRAM and NAND flash. With more than 3,000 volunteers representing over 350 member companies, JEDEC is the key forum where companies come together to decide and define the future for memory. The presentations in this session highlight JEDEC standards and how they enable and address the future of AI, cloud, and automotive applications, and will also highlight new technology initiatives important to the industry and emerging trends critical to planning for the future.
About the Organizer + Moderator:
Hung Vuong is Director of Technical Standards at Qualcomm Corporation
PRO TEST-302-1: General Testing Methods
Ballroom G, Floor 1
Track: Testing and Performance
Paper Presenters:
  • Clinton Aaron Beetham, Staff Engineer, Samsung Semiconductor India Research
  • Christopher Cox, Fellow, AMD
  • Sayali Shirode, Systems Performance Engineer, Micron Technology
  • Mike Dearman, CEO, Quarch Technology
Session Description:
In this session, we discuss new approaches to general testing methods. Autopilot for FW Validation and Test Gap Identification performs automated testing for FW releases. Integrated with CI/CD, this AI/ML-powered tool automatically configures test priorities based on FW features and changes from GIT diff. We will look at lessons learned from PCIe and NVM in testing new CXL designs and share best practice tests for controllers and devices to mitigate risks. We will also look at the importance of deep learning recommended model training in personalized recommendations and the critical role of Data Ingest in DLRM training
11:00 AM to 12:00 PM
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Open Executive AI Premier Level Panel
Mission City Ballroom, Floor 1
Track: FMS 2024 Special Sessions
Session Sponsor:
NVIDIA
Session Description:
Storage and Memory Innovation for AI Workloads. Hosted and Moderated by NVIDIA. Panelists: KIOXIA, Samsung, Supermicro, Vast Data
12:10 PM to 01:15 PM
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PRO AIML-303-1: AI and ML Techniques
Ballroom B, Floor 1
Track: AI and ML Applications
Organizer + Moderator:
David McIntyre, Director Product Planning, Samsung Electronics
Paper Presenters:
  • Wesley Vaske, Principal Storage Solutions Enginee, Micron Technology
  • Sandeep Dattaprasad, Senior Product Manager, Astera Labs
  • Ramyakanth Edupuganti, Staff Applications Engineer, Microchip Technology
  • Arun Pillai, Staff Engineer, SSIR (Samsung Semiconductor India Research)
  • Ramya BT, Senior Staff Engineer, Samsung Semiconductor India Research
Session Description:
This session dives into the world of AI and ML acceleration with CXL-Attached Memory, addressing the memory and performance bottlenecks faced by AI applications in multi-processor systems. By utilizing Compute Express Link (CXL), AI data centers can expand memory capacity and bandwidth, improving efficiency and reducing errors. A case study demonstrates the optimized performance and reduced total cost of ownership (TCO) achieved through CXL-based platforms for memory-intensive AI workloads. Additionally, the potential use of machine learning in automating UVM test case generation and the importance of application-agnostic machine learning engines in SSD controllers are discussed. Lastly, the MLPerf Storage Benchmark Suite simplifies storage sizing and benchmarking for AI workloads, aiding in representation and generation of synthetic datasets for accurate analysis.
About the Organizer + Moderator:
David McIntyre focuses on computational storage acceleration solutions development and strategic business enablement for cloud to edge applications including AI inference/video analytics, database processing and blockchain networks. He has held senior management positions with IBM, Samsung, Xilinx, Intel (formerly Altera) and at Silicon Valley startups. He has consulted for institutional investors including Fidelity, Goldman Sachs and UBS. David is a frequent presenter and chairperson at the Flash Memory Summit and other technical conferences including SNIA.
PRO AUTO-303-1: Software Defined Vehicles NEW
Ballroom A, Floor 1
Track: Automotive Applications
Organizer + Chairperson:
Bill Gervasi, Principal Systems Architect, Wolley Inc
Paper Presenters:
  • Nicolas Leng, Assistant Manager, Product Management, ATP Electronics
  • Sandeep Krishnegowda, Sr Director of Marketing and Applications, Infineon Technologies
  • Xian Liu, Associate Director, Technology Development, Silicon Storage Technology, Inc.
  • Antony Ambrose, Storage Subsystem Architect, Bosch
  • Ritesh Thakur, Staff Engineer, Samsung
Session Description:
Adaptive memory technology in the automotive industry involves the dynamic allocation and optimization of memory resources within a vehicle's ECU and computing systems, enhancing performance, safety, and efficiency through memory allocation adjustments based on driving scenarios. Challenges in PCIe SSD robustness in cross-temperature applications are explored, focusing on overcoming overheating issues to ensure reliability and performance. The importance of flash memory storage in modern vehicles is highlighted, addressing the need for high-performance, secure solutions to enable advanced functionalities. As software-defined vehicles become prevalent, the need for high-performance, safe, and secure flash memories is emphasized to support evolving automotive architectures and standards. Embedded automotive-grade flash technology is also discussed for reliable and stable vehicle operation.
About the Organizer + Chairperson:
Mr. Gervasi has over 45 years of experience in high speed memory subsystem definition, design, and product development. Career highlights include 19 years at Intel where he was systems hardware designer, software designer, and strategic accounts manager. Mr. Gervasi became a memory specialist for companies including S3, Transmeta, Netlist, SimpleTech, and Nantero, and is now Principal Systems Architect for Wolley, developing CXL based memory solutions. Mr. Gervasi been involved in the definition of Double Data Rate SDRAM since its earliest inception. He has served on the JEDEC Board of Directors and chaired committees for DRAM parametrics and memory modules during the development of DDR1 through DDR6. He is currently the chairman of the JEDEC Alternative Memory committee. He received the JEDEC Technical Excellence award, their highest honor, in 2020.
Open BMKT-303-1: Data-Intensive Customer Solutions
GAMR 1 (Great America Meeting Room 1), Floor 2
Track: Business Strategies and Memory Markets
Organizer + Chairperson:
Jean Bozman, President, Cloud Architects Advisors
Paper Presenters:
  • Molly Presley, SVP Marketing, Hammerspace
  • Bill Basinas, Sr. Director Product Marketing, Infinidat
  • Davide Villa, CRO, Xinnor
  • Odie Killen, VP Hardware Engineering, Viking Enterprise Solutions
  • Manzur Rahman, Product Marketing Engineering Manager, Solidigm
  • Brian Dargel, Director of Technical Marketing, Solidigm
Session Description:
Customer use of Artificial Intelligence (AI) and GenAI in their businesses is leading to vast amounts of scalable AI data that must be managed, protected and secured. This is a formidable challenge for IT organizations – and for the business units that use AI analytics to drive higher levels of corporate revenue and profits. This informative session, based on actual customer results, discusses large data resources – with petabytes of data – and shows how customers are working with them, while preventing cyberattacks and ransomware from slowing or stopping business operations. Presentations include: the selection of a fast-cache solution for a 100PB tape library; an in-depth analysis of Total Cost of Ownership (TCO) for data centers; and a presentation about optimizing investments for efficiency and cost-effectiveness in the data center – and in the hybrid cloud.
About the Organizer + Chairperson:
Jean S. Bozman is President of Cloud Architects Advisors, a market research and consulting firm focused on hardware and software for enterprise and hybrid multi-cloud computing. She analyzes the markets for servers, storage, and software related to datacenters and cloud infrastructure. A highly-respected IT professional, she has spent many years covering the worldwide markets for operating environments, servers, and server workloads. She was a Research VP at IDC, where she focused on the worldwide markets for servers and server operating systems. She is a frequent conference participant as a speaker, chairperson, and organizer at such events as Flash Memory Summit, OpenStack, and Container World. She is often quoted in a variety of publications including BusinessWeek, Investor’s Business Daily, the Los Angeles Times, CNET, Bloomberg, and Reuters. Ms. Bozman has also been VP/Principal Analyst at Hurwitz and Associates and Sr Product Marketing Manager at Sandisk. She earned a master’s degree from Stanford.
PRO CLDS-303-1: Cloud Solution/Technology Innovations
Ballroom E, Floor 1
Track: Cloud Storage and Applications
Paper Presenters:
  • Jung Yoon, Distinguished Engineer and CTO, Supply Chain, IBM
  • Suresh Rajgopal, SENIOR TECHNOLOGIST, SYSTEMS ARCHITECT, Micron Technology
  • Nilesh Shah, VP, Business Development, ZeroPoint Technologies
  • Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft
Session Description:
Composable Memory Systems (CMS) are a game-changer for hyperscale environments, but adoption barriers exist. This session dives into using Compute Express Link (CXL) to overcome these hurdles, backed by Total Cost of Ownership (TCO) models. We explore demands in Hyperscale and AI workloads, driving the need for CMS. With CXL-attached Flash memory tiers and pools, along with transformative enablers like Optical CXL, NVMe over CXL, and OCP Hyperscale CXL Tiered Memory Expansion, the future of memory and storage is reshaped. Collaborative innovation within the CXL Community is key, with unresolved challenges in pooled deployment.
PRO DSEC-303-1: Addressing Device Exposures
Ballroom D, Floor 1
Track: Data Security/Ransomware Protection
Organizer + Chairperson:
Camberley Bates, VP and Practice Lead, Futurum Group
Paper Presenters:
  • Vishwas Saxena, Technologist, Firmware Engineering, Western Digital
  • Luis Freeman, Technical Project Manager, Technology and Strategy for Storage Devices, Supply Chain Engineering
  • Steve Chung, NYCU Chair Professor/UMC Chair Professor, National Yang Ming Chiao Tung University
Session Description:
Physical devices, memory, drives, USB’s all pose threats when introduced to systems, especially when the chain of custody may be cloudy. The speakers in this session will bring to light some of the latest threats and approaches to assure the devices are clean and non -threatening before they are introduced into the systems environment
About the Organizer + Chairperson:
Camberley serves as the VP and Practice Lead at The Futurum Group bringing over 25 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm. She joined The Futurum Group through their acquisition of Evaluator Group in 2023. As the Managing Director at Evaluator Group from 2009 until 2023 she built a highly respected team, known for its deep technical expertise delivering competitive and market knowledge backed by data based economic and hands-on experience with the technology and IT consulting services. Camberley began her career at IBM in sales and management. She holds a BS degree in International Business from California State University - Long Beach and executive certificates from Wellesley and Wharton School of Business.
PRO NETC-303-1: CXL and PCIe Memory Fabrics
Ballroom F, Floor 1
Track: Networks and Connections
Chairperson:
John Kim, Director of Storage Marketing, NVIDIA
Paper Presenters:
  • Steve Scargall, Senior Product Manager/Software Archtect, MemVerge
  • Phil Cayton, Principal Engineer, OpenFabrics Alliance
  • Brian Pan, General Manager, H3 Platform
  • Chris Blackburn, Director of Field Applications Engineering, Astera Labs
Session Description:
This session will discuss a variety of CXL and PCIe memory fabrics. Traditional HPC architectures can be inefficient, with underutilized resources leading to wasted energy. Composable Disaggregated Infrastructure (CDI) offers a solution by dynamically composing servers with shared hardware resources. The OpenFabrics Alliance is developing Sunfish, an open-source management framework to control and monitor computing resources across different fabric types. Scaling GPU clusters and low-latency memory fabrics is crucial for AI workloads. Active PCIe/CXL cabling solutions are needed to connect larger clusters efficiently. Attendees will learn about the limitations of passive PCIe DAC solutions and the benefits of active cabling for scalability and reliability.Lastly, we will explore PCIe Gen5 fabric implementation and the impact of Fabric Attached CXL Memory Systems on key industries..
About the Chairperson:
John KIm is Director of Storage Marketing at NVIDIA
PRO OPSW-303-1: Memory Management Ecosystem
Ballroom C, Floor 1
Track: Open Source Software
Paper Presenters:
  • Davidlohr Bueso, Principal Software Engineer, Samsung Electronics
  • Sergei Vinogradov, Middleware Architect, Intel
  • Javier Gonzalez, Principal Software Engineer, Samsung Electronics
  • Barrett Edwards, CEO, Jackrabbit Labs
Session Description:
In the world of computing, CXL technology is set to revolutionize the way we think about memory management. With the ability to share memory coherently across multiple compute nodes, the possibilities for software applications are endless. However, the lack of a comprehensive software development environment and industry standard tools has been holding back the widespread adoption of CXL technology. Thankfully, we have developed an open source solution to address these challenges. With tools like 'Jack' for fabric management and a software development environment that integrates virtual CXL switch capabilities, we are paving the way for a future where shared memory software is the norm. Join us as we dive into the current state of the Linux CXL ecosystem and explore the benefits of a Unified Memory Framework, providing a unified API for diverse memory technologies. The future of computing is bright, and with these innovations, we are ready to embrace it head on.
PRO SSDT-303-1: Power Optimization & Telemetry Features for SSDs
Ballroom G, Floor 1
Track: SSD Technology
Organizer + Chairperson:
Erich Haratsch, Senior Director Architecture, Marvell
Paper Presenters:
  • Karthik Balan, Associate Director, Samsung Electronics
  • Pitamber Shukla, Senior Technical Staff Engineer-Architect, Data Center Solutions
  • Ayberk Ozturk, Director, Microsoft
  • Jonmichael Hands, Sr Director Strategic Planning, Fadu
Session Description:
In this session we look at power optimization and telemetry features for SSD that have the potential to revolutionize the economics of data center operations. By optimizing the performance-to-power ratio through SSD controllers, data centers can achieve unparalleled levels of efficiency, resilience, and cost-effectiveness. Leveraging the latest advancements in controller design and NAND technology, data centers can unlock new levels of performance while minimizing their environmental footprint. This session will provide insights into the efficient design principles driving the next generation of storage solutions, and the pivotal role SSD controllers play in shaping the future of data center TCO.
About the Organizer + Chairperson:
Erich Haratsch is Senior Director Architecture at Marvell, where he leads the architecture definition for Bravera SSD controllers and other memory-based products. Prior to joining Marvell, he worked at Seagate and LSI, where he worked on Nytro and SandForce branded SSD controllers. Earlier in his career, he developed signal processing and error correction technologies for multiple generations of HDD controllers at LSI and Agere Systems. He started his career at AT&T and Lucent Bell Labs, where he worked on Gigabit Ethernet over copper, optical communications and the MPEG-4 video standard. He is the author of over 40 peer-reviewed journal and conference papers, and holds more than 200 U.S. patents. He also is a Senior Member of IEEE, and earned his MS and PhD degrees from the Technical University of Munich (Germany).
01:25 PM to 02:30 PM
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Open AIML-304-1: Emerging Technologies for AI Chip and Generative AI Optimization
Ballroom B, Floor 1
Track: AI and ML Applications
Organizer + Moderator:
Russ Fellows, Head of Futurum Labs, Futurum Group
Paper Presenters:
  • Gary Grider, HPC Division Leader, Los Alamos National Laboratory
  • Rohit Mittal, AI HW architect, Google
  • Trond Myklebust, CTO, Hammerspace
  • Raj Narasimhan, Senior VP and GM, Compute & Networking Business Unit, Micron
  • Andy Hsu, Founder & CEO, NEO Semiconductor
Session Description:
Modern AI Chips have found a ‘killer app’ in generative AI (GenAI) and large language models (LLMs). Yet, innovation continues with new and emerging technologies driving product roadmaps and introductions at an accelerating pace. There are new chip architectures and software data architectures with standards-based parallel file systems to accelerate performance for AI. Led by an industry analyst, join invited speakers from influential processor, memory, generative AI companies, along with customers focused on AI as they present and discuss the hardware and software technologies driving the future of AI Chips and Generative AI customer implementations.
About the Organizer + Moderator:
Russ brings over 25 years of diverse experience in the IT industry to his role at The Futurum Group. As a partner at Evaluator Group, he built the highly successful ;lab practice, including IOmark benchmarking. Prior to Evaluator Group he worked as a Technology Evangelist and Storage Marketing Manager at Sun Microsystems. He was previously a technologist at Solbourne Computers in their test department and later moved to Fujitsu Computer Products. He started his tenure at Fujitsu as an engineer and later transitioned into IT administration and management.
Open ACAD-304-1: Academic
GAMR 1 (Great America Meeting Room 1), Floor 2
Track: Academic
Organizer + Chairperson:
Joseph Wei, Director, IEEE
Paper Presenters:
  • Haocong Luo, PhD Student, SAFARI Research Group at ETH Zurich
  • Geraldo Francisco De Oliveira Junior, PhD Candidate, ETH Zurich
Session Description:
This session highlights academic work from graduate students at ETH Zurich. RowPress is a newly discovered read-disturb phenomenon that poses a significant threat to system safety and security by breaking memory isolation in DDR4 DRAM chips. This phenomenon keeps a DRAM row open for an extended period, causing bitflips in nearby victim cells. A summary of mechanisms to counteract the impact of RowPress will be discussed. Data movement between memory and processors is a major bottleneck in modern computing systems. The processing-in-memory (PIM) paradigm aims to alleviate this bottleneck by performing computation inside memory chips. Real PIM hardware (e.g., the UPMEM system) is now available and has demonstrated potential in many applications. However, as programming such as real PIM hardware remains challenging for many programmers, this session will discuss a new approach to programming real PIM systems.
About the Organizer + Chairperson:
Joseph Wei is a Board member, IEEE Region 6 Director-Elect (2023-2024) Entrepreneurship, IEEE Santa Clara Valley Section. Chair, IEEE EMBS-SCV Treasurer, IEEE SFBA CTSoc Chapter
PRO AUTO-304-1: Vehicle to Everything NEW
Ballroom A, Floor 1
Track: Automotive Applications
Organizer + Chairperson:
Bill Gervasi, Principal Systems Architect, Wolley Inc
Paper Presenters:
  • Darren Lin, Product Marketing Manager, Silicon Motion
  • Chris Lien, Senior Manager, ATP Electronics
  • Joe Ohare, Marketing Director, Everspin
  • Durlov Khan, Product Engineer, Cadence Design System
Session Description:
As we drive into the future of automotive technology, advancements in storage solutions are key to meeting the demands of autonomous and V2X vehicles. With the increasing amount of data being stored and transferred in vehicles, higher speed and capacity are essential. Security and safety of this data are also critical considerations in this connected environment. The industry is moving towards domain and centralized architectures, and the presentation will highlight the benefits of advanced SSD technology in enhancing efficiency and resource allocation. Additionally, the adoption of CXL in automotive applications presents new opportunities for next-generation car designs. Stay ahead of the curve with the latest trends in automotive storage implementation and verification challenges. Explore how MRAM is revolutionizing energy-efficient computing in automotive applications, providing new architectural choices and connectivity options for future vehicles.
About the Organizer + Chairperson:
Mr. Gervasi has over 45 years of experience in high speed memory subsystem definition, design, and product development. Career highlights include 19 years at Intel where he was systems hardware designer, software designer, and strategic accounts manager. Mr. Gervasi became a memory specialist for companies including S3, Transmeta, Netlist, SimpleTech, and Nantero, and is now Principal Systems Architect for Wolley, developing CXL based memory solutions. Mr. Gervasi been involved in the definition of Double Data Rate SDRAM since its earliest inception. He has served on the JEDEC Board of Directors and chaired committees for DRAM parametrics and memory modules during the development of DDR1 through DDR6. He is currently the chairman of the JEDEC Alternative Memory committee. He received the JEDEC Technical Excellence award, their highest honor, in 2020.
PRO DCTR-304-1: Enterprise Storage Part 2
Ballroom D, Floor 1
Track: Data Center Applications
Organizer + Chairperson:
Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft
Paper Presenters:
  • Sayali Shirode, Systems Performance Engineer, Micron Technology
  • Bill Gervasi, Principal Systems Architect, Wolley Inc
  • Krishna Kumar, Solutions Architect, Intel
Session Description:
In the world of NVMe Over CXL, the game-changing CXL protocol revolutionizes controller memory buffers. By overcoming the limitations of PCIe bus, CXL enables efficient memory accesses with CXL.mem protocol while maintaining legacy NVMe functionalities with CXL.io protocol. SSDs utilizing NVMe Over CXL offer significant advantages, particularly in resolving race conditions through storage and memory integration. Additionally, the merging of storage and memory in High availability flash architectures using CXL results in online high availability with minimal takeover time and synchronization. Power efficiency in SSDs is crucial for optimizing performance and reducing environmental impact, particularly in applications like RocksDB NoSQL database.
About the Organizer + Chairperson:
Jonathan Hinkle is Senior Director - Azure Memory and Storage Pathfinding at Microsoft. He previously was In Micron's Storage Business Unit, where he investigated new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.
PRO INVT-304-1: Invited Talk with David Flynn
Ballroom F, Floor 1
Track: Invited Talks
Organizer + Chairperson:
Leah Schoeb, Sr. Developer Relations Manager, AMD
Paper Presenters:
  • David Flynn, CEO, Hammerspace
Session Description:
In the landscape of artificial intelligence, architectural complexities of large-scale computing - spanning hundreds to thousands of processors and storage nodes, accessed by a myriad of researchers for debugging and code adjustments - present a formidable challenge. Yet, it is within these environments that the future of AI is being forged. Central to unlocking this potential is embracing open standards, which empower enterprises to harness specialized capabilities previously reserved for Hyperscaler and High-Performance Computing (HPC) environments. This session illuminates the pioneering advancements spearheaded by Meta and Hammerspace in revolutionizing the parallel network file system (NFS), a cornerstone for AI endeavors. Our focus zeroes in on contributions to the Linux NFS kernel, incorporating robust data protection mechanisms into the pNFS with the FlexFiles NFS client. These enhancements are not merely technical milestones; they represent a leap forward in enabling unparalleled data protection, alongside parallel and shared data access across any Linux client and storage node
About the Organizer + Chairperson:
Leah Schoeb is a Sr Developer Relations Manager in AMD's platform architecture team, where she engages with solid state storage vendors on storage technology futures. She has over 25 years of experience in the computer industry, and was previously Acting Director of Reference Architecture at Intel where she led a team of segment managers and architects managing cross functional teams for flash- and NVMe-based data solutions. Leah has held management and engineering positions at VMware, Dell, and Sun Microsystems, and was also a Senior Partner at the analyst firm Evaluator Group, where she focused on storage, virtualization, and cloud infrastructure. Leah has ten technical publications, and has presented at many technical conferences. Her MBA us from the Univ. of Phoenix, and heer BSEE is from the Univ. of Maryland, College Park.
PRO OPSW-304-1: AI Open-Ecosystem NEW
Ballroom C, Floor 1
Track: Open Source Software
Organizer + Chairperson:
Javier Gonzalez, Principal Software Engineer, Samsung Electronics
Paper Presenters:
  • Prasad Venkatachar, Solutions Director, Pliops
  • Lakshman Chari, Cloud and AI partnerships, Intel Corporation
  • Nilesh Shah, VP, Business Development, ZeroPoint Technologies
Session Description:
Join us as we explore the future of AI technology in this exciting session. We begin with an in-depth exploration of the impact of Open Source LLMs and Vector Databases on Generative AI. We dive into the world of building Gen AI applications from scratch, including prompt engineering and fine tuning and learn how to maximize performance and accuracy with open-source vector databases. We will discover the crucial design parameters for storage accelerators in AI clusters, and the role of open source solutions in driving innovation. Lastly we will look at open source ecosystems for GenAI.
About the Organizer + Chairperson:
Javier Gonzalez leads Samsung Memory Solutions' Global Open-Source Team (GOST), managing a distributed team of engineers who are focused on open-source software. He is the founder and site manager for Samsung Semiconductor Denmark Research (SSDR) -- which is Samsung’s Memory Solutions first R&D center in Europe and its fifth such center worldwide. Javier’s interests are centered in the hardware/software co-design space, where systems software, hardware architecture, and open-source meet. He contributes to a wide range of open- source projects, including the evolution of the Linux Kernel. He is a regular speaker at several top industry and academic conferences each year.
PRO QLCP-304-1: QLC and PLC
Ballroom E, Floor 1
Track: QLC and PLC
Organizer + Chairperson:
Brian Berg, President, Berg Software Design
Paper Presenters:
  • David Verburg, SSD/HDD Sr Technical Staff Member, IBM
  • Wei Min Lai, Project Deputy Manager, Silicon Motion
  • Bill Panos, Product Marketing Manager, Solidigm
  • Javier Gonzalez, Principal Software Engineer, Samsung Electronics
Session Description:
In the fast-evolving world of storage technology, the question of whether QLC SSDs will eventually displace Near-Line HDDs is a hot topic. This session will delve into the factors influencing this transition, such as retention, reliability, density, and cost. Industry trends and customer use cases will also be explored to determine when this shift may take place. We will highlight the innovations and challenges of QLC NAND Flash technology, including capacity optimization, performance enhancement, and data integrity. Lastly, the session will address how QLC SSDs are enabling new use cases in cloud and enterprise environments, as well as the strategic choices data center architects can make to leverage QLC technology effectively in their infrastructure.
About the Organizer + Chairperson:
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley Section, Director and past Chair of the Consultants Network of Silicon Valley, Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for Outstanding Service to the Consulting and Electrical Engineering profession, and the 2012 Outstanding Leadership and Professional Service Award for Region 6.
PRO SSDT-304-1: New Form Factors and Interfaces for SSDs
Ballroom G, Floor 1
Track: SSD Technology
Organizer + Chairperson:
Erich Haratsch, Senior Director Architecture, Marvell
Panel Members:
  • Kenichiro Yoshii, Staff Engineer, Hagiwara Solutions
  • Ilya Cherkasov, Sr. Product Manager, Enterprise SSD, KIOXIA America, Inc.
  • Carlos Franco, Principal Engineer, Micron
  • Tahmid Rahman, Product Marketing Director, Solidigm
Session Description:
This session discusses new form factors and interfaces for SSDs. As use cases evolve, the need for differentiated SSD solutions becomes apparent. From data centers to edge applications, SSDs must be tailored to meet specific demands, offering enhanced endurance and intelligent telemetry. The E3.S form factor is reshaping the landscape for NVMe applications, offering superior performance and density over traditional 2.5" drives. The advent of PCIe Gen6 brings new challenges for SSD deployment, requiring careful electrical validation and testing to ensure optimal performance at scale. CFexpress 4.0, utilizing PCIe 4.0 and NVMe 1.4, has revolutionized the high-end camera market with its impressive bandwidth capabilities. But its potential extends beyond photography, making waves in the industrial sector.
About the Organizer + Chairperson:
Erich Haratsch is Senior Director Architecture at Marvell, where he leads the architecture definition for Bravera SSD controllers and other memory-based products. Prior to joining Marvell, he worked at Seagate and LSI, where he worked on Nytro and SandForce branded SSD controllers. Earlier in his career, he developed signal processing and error correction technologies for multiple generations of HDD controllers at LSI and Agere Systems. He started his career at AT&T and Lucent Bell Labs, where he worked on Gigabit Ethernet over copper, optical communications and the MPEG-4 video standard. He is the author of over 40 peer-reviewed journal and conference papers, and holds more than 200 U.S. patents. He also is a Senior Member of IEEE, and earned his MS and PhD degrees from the Technical University of Munich (Germany).
02:40 PM to 03:40 PM
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Open SPEC-305-1: Memory-Intensive Storage Solutions for AI: Pushing the Limits !!!
Ballroom G, Floor 1
Track: AI and ML Applications
Organizer + Chairperson:
Jean Bozman, President, Cloud Architects Advisors
Session Description:
Description Not Available
About the Organizer + Chairperson:
Jean S. Bozman is President of Cloud Architects Advisors, a market research and consulting firm focused on hardware and software for enterprise and hybrid multi-cloud computing. She analyzes the markets for servers, storage, and software related to datacenters and cloud infrastructure. A highly-respected IT professional, she has spent many years covering the worldwide markets for operating environments, servers, and server workloads. She was a Research VP at IDC, where she focused on the worldwide markets for servers and server operating systems. She is a frequent conference participant as a speaker, chairperson, and organizer at such events as Flash Memory Summit, OpenStack, and Container World. She is often quoted in a variety of publications including BusinessWeek, Investor’s Business Daily, the Los Angeles Times, CNET, Bloomberg, and Reuters. Ms. Bozman has also been VP/Principal Analyst at Hurwitz and Associates and Sr Product Marketing Manager at Sandisk. She earned a master’s degree from Stanford.