2024 Program at a Glance - FMS: the Future of Memory and Storage

Program at a Glance

01:00 PM to 02:45 PM

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PRO PDSA1: Quantum Memory: Superconducting Qubits & Quantum Computer HW Design - Pt 1

Track: Professional Development Series (Pre-Conference)

Organizer + Presenter:

WeiTi Liu, General Partner, Quantum Technology

Wei-Ti Liu is a General Partner of Quantum Technology, LLC. He was previously Co-Founder/GM/VP Engineering at PLX Technology, a maker of PCI-based chipsets. At PLX, he oversaw operations, directly managed the engineering group, and managed the foundry interface. He was President/CEO of NetChip Technology (now Broadcom Inc), a USB controller maker, and a security device manufacturer. Wei-Ti has extensive experience in ASIC VLSI chip designs, and has also been a design engineer for IBM, AMD, and Intel. He earned an MSEE from the City College of New York and a BSEE from the National Taiwan University. He has presented at several Flash Memory Summits and holds twelve US patents in that area. Areas of Interest includes: Investing Quantum Technology, and Advising on Semiconductor related technology projects, MRAM design, 3D Die stacking, and Heterogeneous Integration Architecture Design. Quantum Computing Workshop Presenter, “The Fundamental of Quantum Computation and Quantum Information for Engineer— A Practical Approach”. Grove School of Engineering, The City College of The City University of New York. Tutorial Course Agenda: 1. Introduction to Quantum Computing and Application 2. Review of Linear Algebra—Basic 3. Qubits, Operators and Measurement 4. Quantum Gates 5. Complexity Theory—Introduction 6. Quantum Communication 7. Quantum Computing with IBM Quantum Experience (Hands-on experience) 8. Quantum Algorithms 9. Quantum Error Correction.

Pre-Con Seminar Description:

Unlike classical memory, quantum computing's "no-clone theorem" limited Quantum memory using classical memory's read/write operations; when we access or measure qubits, their information is inevitably destroyed. Therefore, we must rely on quantum operations, precisely entanglement, to access qubits. As quantum computers advance, they demand many digital and analog circuits to execute control and measurement functions. The proliferation of qubits in an array has led to a significant increase in control and measurement signals. This signal surge has created a scalability issue for quantum computers, posing a challenge in their design and operation. The number of digital and analog cryogenic CMOS circuits has also escalated, leading to power and scalability issues, necessitating innovative solutions for quantum memory hardware design. Quantum memory is essential to quantum computing applications like finance, quantum chemistry, cryptography, and scientific research. Quantum networks enable secure, faster, and longer-distance transfer of quantum information. Moreover, they require quantum repeaters and quantum memory. This Professional Development Session aims to motivate experienced hardware and software engineers to explore the quantum field. We are exploring the advantages of quantum computing in finance, cryptography, chemistry, and optimization. Furthermore, quantum networks enable faster, longer-distance quantum information transfer with a secure network. Quantum memory is a significant element of quantum computing, and we are gaining knowledge of quantum hardware design using superconducting qubits. Part 1: • Gain knowledge of quantum computing hardware elements and understand the technical knowledge needed to design quantum computers with quantum process units (QPU) interfaces with quantum control and measurements. • Gain the engineering knowledge for implementing quantum vs classical algorithms. • Gain knowledge of engineering requirements for quantum computing and understand the quantum advantage over classical computers. • We summarized the quantum computing hardware's requirements for quantum memory.

PRO PDSB1: CXL for Disaggregated Memory & Accelerators in Data Ctrs - Pt 1

Track: Professional Development Series (Pre-Conference)

Organizer + Moderator:

Dr. Pankaj Mehra, Founder, Elephance

Pankaj Mehra is President and CEO of Elephance Memory. A contributor to InfiniBand 1.0 spec and an inventor of the first RDMA persistent memory devices and filesystems, Pankaj is a systems and software practitioner who conducts his research at the intersection of infrastructure and intelligence. He is a co-author/co-editor/co-inventor on 3 books, and over 100 papers and patents, and a builder of systems that have won recognition from NASA, Sandia National Labs, and Samsung Electronics, among others. He was a VP of Storage Pathfinding at Samsung, Senior Fellow and VP at SanDisk and Western Digital, WW CTO of Fusion-io, and Distinguished Technologist at HP Labs. Pankaj has held faculty positions at IIT Delhi and UC Santa Cruz.

Speakers:

Samir Rajadnya, Principal Architect, Microsoft

Samir Rajadnya is a Principal Architect in Microsoft Azure Hardware Architecture team where he works on future memory systems. Prior to Microsoft, Samir spent many years innovating in memory, storage, and networking. Samir was key architect to productize 3DXP technology at Micron, architect, and designer at disruptive storage startup DSSD. He was an SOC architect and designer at Juniper Networks, Netronome and Intel. Samir has served as part of multiple industry standards bodies throughout his career, including CXL and CCIX. Samir received his master’s in electrical engineering from Indian Institute of Technology Bombay.

Manoj Wadekar, Hardware System Technologist, Meta

Manoj is the HW technologist and Mr. "Storage Guy" working at Meta. He is transforming hyper-scale infrastructure to drive performance and efficiency (proven for "ebay servers". He loves Technology Research and Innovation, Product and Technology Strategy, and defining Product Roadmaps/Business cases. He constantly drives Cross-industry initiatives and collaborations.

Siamak Tavallaei, Sr. Principal Engineer, Samsung

Siamak Tavallaei is Sr. Principal Engineer at Samsung. He joined the CXL effort as a founding member of the CXL Consortium and co-chair of the Technical Task Force (TTF) in 2019 to develop the CXL 2.0 specification. He has served on the CXL Board of Directors and as the CXL President. In 2016, he joined Open Compute Project (OCP) as a co-lead of Server Project. He later served as the Incubation Committee Representative for the Server Project and Steering Committee where he drives open-sourced modular design concepts for integrated hardware/software solutions. Previously, he has served as Distinguished Technologist at HP, Senior Principal Architect at Microsoft Azure, and Chief Systems Architect at Google.

Pre-Con Seminar Description:

The motivation for disaggregating memory is rooted in a desire to support and promote vast in-memory computing systems but without the issues of stranding and up-front provisioning. The speakers in this session will systematically comprehensively cover the topic of memory disaggregation leveraging the CXL standard from a software and hardware perspective, highlighting both challenges and opportunities. We will pay close attention to characteristics and use of memory at a distance. We conclude with our projections about the future of memory attachment in data centers. Topics: - CXL 3 and an update on standards covering P2P - Composable Memory Systems and OpenCompute Project - AI roadmap through 2030, the AI flywheel and data, and specific projections regarding memory and storage needs of AI - An updated analysis of memory expansion for AI, Database, and Virtual Machine workloads - Computational Memory and Storage Programming - Updated findings from architecture and operating systems for disaggregated memory

PRO PDSC1: DRAM in an Increasingly Diverse Platform

Track: Professional Development Series (Pre-Conference)

Pre-Con Seminar Description:

Long gone are the days where DRAM and storage were the only two options for computer architectures. Chiplets, fabrics, and switching tiers have all entered the equation, and hybrids of memory and storage contribute to a top to bottom rethinking of data flow. Artificial intelligence as a dominant emerging technology is also affecting the equation where memory capacity requirements force a blending of multiple memory approaches to feed the beast. These new requirements are also driving an energy crisis, so total cost of ownership analyses are required to make good tradeoffs. Takeaways from this session: • Understand the new memory tiers including HBM and CXL • Analyze the new hybrid memory concepts such as memory semantic storage • Impact of artificial intelligence and new automotive architectures • What trends are on the mobile client and edge fronts • Why data centers waste so much energy and what can be done about it

PRO PDSD1: Advanced HDD Technology for the Data Center

Track: Professional Development Series (Pre-Conference)

Organizer + Presenter:

Mohamad El-Batal, Sr. Director of Architecture, Seagate

Mohamad is on the Board of Directors of the Non-Volatile Memory Express (NVMe), Flash Memory Summit (FMS), and Open Compute Project (OCP). Mohamad is currently the chair of the NVMe-HDD working group and driving its requirements specification. He is also the chair of the OCP PCIe External Connectivity Workstream enabling PCIe to evolve with NVMe and Computer Express Link (CXL) into the Ultra-Low-Latency of optical fabric of choice. He was the author and chair of the Storage Bridge Bay (SBB) specification and was on the SBB board of directors for multiple years. Mohamad participated technically and influenced various industry groups including the FC, SAS, NVMe, CXL and GenZ consortiums. In his career, Mohamad worked at leading enterprise storage technology and cloud provider companies, including Tandem, EMC, Mylex, IBM, LSI, Engenio, NetApp and now Seagate. Mohamad has 30+ year history of enterprise and cloud storage architecture knowledge, experience, and innovation. Mohamad holds 50+ issued and 20+ pending patents, covering: High-Availability/Resiliency Storage and Memory solutions, SSD controller and Systems architecture focus areas.

Speakers:

Praveen Viraraghavan, Technologist, Seagate

Praveen Viraraghavan is the Technologist of the Product Line Management organization. In his role at Seagate, Praveen is given the opportunity to collaborate with other leaders to shape the portfolio across all parts of the Seagate product and research ecosystem. Praveen works closely with all customers to help align their storage strategy to Seagate’s product and technology roadmap. Praveen has a proven record owning hardware and software architecture strategy working with multiple levels of technical and corporate leadership. Praveen has a knowledge of the ecosystem related to data management, which allows advocacy for the customer’s requirements while still prioritizing the company’s business and technical options. Praveen holds a BS degree in Electrical Engineering and did some graduate work on VLSI design in 1997 from Purdue University at West Lafayette. During his storage career Praveen has worked from the lowest embedded layers, silicon development, product architecture and development up through to the software layer. Praveen led the architecture of many new first-pass success silicon developments and new HDD and SSD product lines at leading storage companies serving cloud and OEM customers. Praveen transitioned to a startup where is helped redefine the storage stack used in the cutting edge S3 on premise object storage software solution, the company was later acquired. Praveen has been a contributor to many industry standard bodies. In his career, Praveen worked at leading storage technology and cloud companies, including Western Digital, LSI Logic, Cleversafe (acquired by IBM) and now Seagate. Praveen has 25+ year history of enterprise and cloud storage architecture knowledge, experience, and innovation. Praveen holds 50+ issued and 25+ pending patents, covering: Silicon Control and Datapath, Command Handling, Distributed Object Storage, Filesystems, and Memory solutions. Praveen has won innovation awards from LSI and IBM and was an IBM Master Inventor. Praveen currently serves on 4 Seagate patent review boards in support of their continued innovation.

Pre-Con Seminar Description:

Greater than 88% of today's cloud storage is stored on Hard Disk Drive (HDD) media, and this majority percentage is expected to remain true for the near future. These storage track sessions will discuss why this is the case and will go deep into the incredibly complex but commoditized and simplified technologies that enabled this fact. We will present on the substantial technical breakthroughs that have enabled HDDs to continue their capacity growth rate, and then explain the difference between the major formatting technologies, CMR vs. SMR, then discuss in detail the PMR technical capabilities and limitations and then dive into HAMR media and recording technologies. We plan to discuss some of the myths surrounding HDD Near-Line storage capabilities and limitations and explain the justifications behind some of the current and future engineering innovations that enable HDDs to maintain their Total Cost of Ownership (TCO) supremacy over other leading storage solutions. Our intent is to inform and empower the audience of these sessions with key information and strategies that would help them understand the difference between the various available HDD technologies and enable them to best pick the right storage for the right usage model to optimize their storage TCO.

03:15 PM to 05:00 PM

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PRO PDSA2: Quantum Memory: Superconducting Qubits & Quantum Computer HW Design - Pt 2

Track: Professional Development Series (Pre-Conference)

Pre-Con Seminar Description:

Unlike classical memory, quantum computing's "no-clone theorem" limited Quantum memory using classical memory's read/write operations; when we access or measure qubits, their information is inevitably destroyed. Therefore, we must rely on quantum operations, precisely entanglement, to access qubits. As quantum computers advance, they demand many digital and analog circuits to execute control and measurement functions. The proliferation of qubits in an array has led to a significant increase in control and measurement signals. This signal surge has created a scalability issue for quantum computers, posing a challenge in their design and operation. The number of digital and analog cryogenic CMOS circuits has also escalated, leading to power and scalability issues, necessitating innovative solutions for quantum memory hardware design. Quantum memory is essential to quantum computing applications like finance, quantum chemistry, cryptography, and scientific research. Quantum networks enable secure, faster, and longer-distance transfer of quantum information. Moreover, they require quantum repeaters and quantum memory. This Professional Development Session aims to motivate experienced hardware and software engineers to explore the quantum field. We are exploring the advantages of quantum computing in finance, cryptography, chemistry, and optimization. Furthermore, quantum networks enable faster, longer-distance quantum information transfer with a secure network. Quantum memory is a significant element of quantum computing, and we are gaining knowledge of quantum hardware design using superconducting qubits. Part 2: • Understanding the quantum memory hardware design's challenges and qubit requirements • Understanding the critical difference between quantum memory vs classical memory array, Gaining knowledge of engineering requirements for quantum memory design • The hardware of a quantum computer-- system partition based on heat load • We summarize the technology requirements for quantum memory and quantum computers to scale up for sizeable quantum computing systems.

PRO PDSB2: CXL for Disaggregated Memory & Accelerators in Data Ctrs - Pt 2

Track: Professional Development Series (Pre-Conference)

Organizer + Chairperson:

Dr. Pankaj Mehra, Founder, Elephance

Speakers:

Siamak Tavallaei, Sr. Principal Engineer, Samsung

Samir Rajadnya, Principal Architect, Microsoft

Samir Rajadnya is Cloud Infrastructure, and Systems architect at Microsoft bridging the gap between computing and memory/storage. He is passionate about innovating in cloud infrastructure optimizations. Vertical integration between applications, software, systems, and silicon can bring tremendous benefits in large-scale cloud environments. He has led/worked on systems and chips (FPGAs and ASICs) from concept to silicon with several first pass silicon successes.

Manoj Wadekar, Hardware System Technologist, Meta

Manoj Wadekar is a Hardware Systems Technologist driving storage and memory technology and roadmaps at Meta. Manoj has been designing and building servers, storage, and network solutions for over 30 years. He is leading the Composable Memory Systems group in OCP. Manoj has evangelized Memory and Storage Disaggregation, NVMe over Fabric, Lossless Ethernet (DCB/CEE) in industry conferences. Before joining Meta, he held engineering positions at eBay, QLogic and Intel.

Pre-Con Seminar Description:

PRO PDSC2: Introduction to High Bandwidth Memory (HBM)

Track: Professional Development Series (Pre-Conference)

Organizer + Presenter:

Marc Greenberg, Principal Consultant and CEO, Marc Greenberg Consulting, LLC

Marc Greenberg is an independent consultant in memory, semiconductor and IP. Marc currently serves as VP of Product for Cassia.ai, an AI IP company, as vice-chair of an undisclosed task group at JEDEC, and as advisor to several other companies. Marc was responsible for product management of HBM and other memory and storage IP products at Denali, Cadence and Synopsys for 20 years out of a 30-year career in semiconductor and IP. Marc has a master's degree in Electronics from the University of Edinburgh in Scotland.

Pre-Con Seminar Description:

In this Professional Development Series session, you'll learn about key aspects of High Bandwidth Memory (HBM): What is HBM, a short history of HBM, why is HBM important right now, how Large Language Models (LLMs) and Generative AI are driving demand for HBM technology, comparison of HBM with other popular memory types (DDR, LPDDR and GDDR), a high level view of HBM architecture, PCB and package requirements to implement chips deploying HBM, a view of the market for HBM and the chips that use it, and a review of public information on the future development of high bandwidth memories.

PRO PDSD2: Optimizing HDD Performance in the Generative AI Data Center

Track: Professional Development Series (Pre-Conference)

Organizer + Presenter:

Mohamad El-Batal, Sr. Director of Architecture, Seagate

Speakers:

Praveen Viraraghavan, Technologist, Seagate

Pre-Con Seminar Description:

Citigroup inc. analysts quote "Enterprise data is expected to continue to grow at over 40% CAGR as AI becomes an incremental driver for data creation, storage, and data management" Today's AI ecosystem require fundamental shifts in the requirements of every datacenter infrastructure component. The predominant AI infrastructure strategy tends to currently focus on the most drastically impactful infrastructure components, as in GPUs, CPUs and Memory. Unfortunately, this leaves a major gap in the detailed understanding of the various AI Storage Infrastructure usage models with regards to the various TCO optimized storage tiers and their requirements from a Capacity, Workloads and Performance.

08:30 AM to 09:35 AM

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Open AIML-101-1: Storage for AI: Technology

Ballroom B, Floor 1

Track: AI and ML Applications

Organizer + Moderator:

David McIntyre, Director Product Planning, Samsung Electronics

David McIntyre focuses on computational storage acceleration solutions development and strategic business enablement for cloud to edge applications including AI inference/video analytics, database processing and blockchain networks. He has held senior management positions with IBM, Samsung, Xilinx, Intel (formerly Altera) and at Silicon Valley startups. He has consulted for institutional investors including Fidelity, Goldman Sachs and UBS. David is a frequent presenter and chairperson at the Flash Memory Summit and other technical conferences including SNIA.

Paper Presenters:

Tejas Chopra, Sr. Engineer, Netflix, Inc.

Paper Title:

Memory Optimizations in Machine Learning

Paper Abstract:

As Machine Learning continues to forge its way into diverse industries and applications, optimizing computational resources, particularly memory, has become a critical aspect of effective model deployment. This session, "Memory Optimizations for Machine Learning," aims to offer an exhaustive look into the specific memory requirements in Machine Learning tasks and the cutting-edge strategies to minimize memory consumption efficiently. We'll begin by demystifying the memory footprint of typical Machine Learning data structures and algorithms, elucidating the nuances of memory allocation and deallocation during model training phases. The talk will then focus on memory-saving techniques such as data quantization, model pruning, and efficient mini-batch selection. These techniques offer the advantage of conserving memory resources without significant degradation in model performance. Additional insights into how memory usage can be optimized across various hardware setups, from CPUs and GPUs to custom ML accelerators, will also be presented.

Author Bio:

Tejas Chopra is a Sr. Engineer at Netflix working on the Machine Learning Platform. Previously, he was a part of the Content Engineering organization working on building Storage Infrastructure for Netflix content. Tejas is also the Co-Founder of GoEB1 - a thought leadership platform for immigrants. Tejas is a Sr. IEEE Member, a BCS Fellow, a 2x TEDx speaker, and has spoken at several conferences on Cloud Computing, Blockchain, and Storage Infrastructure. His has worked at companies like Box, Datrium, Samsung, Cadence, and Apple in the past and holds a Master's degree in Electrical and Computer Engineering from Carnegie Mellon University, Pittsburgh.

Chanson Lin, Founder/CEO, Embestor Technology

Paper Title:

Multi-layered Data Storage Architecture for AI/ML Systems.

Paper Abstract:

The AI/ML systems need high bandwidth memory / storage as at ML learning and AI inferencing computational iterations process. On the other respect, the collected Big data which is waiting for analyzing, or the computed / categorized valuable data, those need relatively big capacity and well-organized data storage. As a result, a single-layered data storage device cannot satisfy the overall system performance requirements for AI/ML systems. By presenting a novel multi-layered data storage architecture with SRAM, DRAM, NAND Flash memory, to provide the functions of I/O accessing, Memory accessing, High speed accessing to the multi-layered data storing pools, to increase the performance and efficiency of AI/ML Computing systems. The connection between the multi-layered data storage and the AI/ML Computing engine can be on CXL or organized multiple bus channels.

Author Bio:

Dr. Chanson Lin is the Founder / Chairman & CEO of EmBestor Technology, a company specializing in industrial, niche application, and embedded storage applications. The company focuses on memory storage controller design and flash memory-based storage architectures. He has over 20 years’ experience designing NAND flash memory controllers and invented over 100 patents in the area. Before founding EmBestor, he was General Manager of the NAND flash memory controller business unit of ITE Technology, General Manager of USBest, and President / co-founder of RiCHIP. He has published several articles on embedded systems, industrial applications and has given many conference presentations, including several at previous Flash Memory Summits. He earned a PhD in electrical engineering from the National Chiao Tung University (Taiwan) and an MSEE from the National Taiwan University.

Molly Presley, SVP Marketing, Hammerspace

Paper Title:

Driving Business Outcomes: The Dual Impact of AI in High-Tech Organizations

Paper Abstract:

The integration of Artificial Intelligence (AI) is becoming a critical factor in determining business success and competitiveness. This presentation will explore the dual impact of AI on this sector, highlighting both the immediate benefits and the long-term business results. We will discuss how AI technologies optimize operational efficiencies, enhance product innovation, and enable more effective risk management. The positive implications such as increased productivity, cost efficiency, and market responsiveness will be analyzed. Concurrently, we will discuss potential challenges and considerations, including investment costs, integration complexities, and the need for skilled workforce adaptation. Attendees will gain a comprehensive understanding of how AI can not only transform but also scale businesses, preparing them for future challenges and opportunities.

Author Bio:

Molly brings over 15 years of product and growth marketing leadership experience to the Hammerspace team. She is also the host of the Data Unchained podcast and part of the Superwomen in Flash leadership team. Molly has led the marketing organization and strategy at fast growth, innovators such as Pantheon Platform, Qumulo, Quantum Corporation, DataDirect Networks (DDN), and SpectraLogic. In these companies she was responsible for the go-to-market strategy for SaaS, hybrid cloud, and data center solutions across a range of data intensive verticals and use cases. At Hammerspace, Molly will lead the marketing organization and be responsible for inspiring data creators and data users to take full advantage of a truly global data environment.

Paper Session Description:

As the demand for high-performance AI/ML systems continues to grow, the need for multi-layered data storage architecture has become crucial. Traditional single-layered devices are unable to meet the high bandwidth memory and storage requirements of AI inferencing and ML learning processes. A novel approach incorporating SRAM, DRAM, and NAND Flash memory pools has been developed to enhance I/O and memory access speeds, improving overall system performance. This advanced architecture, utilizing CXL or multiple bus channels, aims to boost the efficiency of AI/ML computing systems by providing high-speed access to data storage layers. Attendees will gain insights into how this innovative design can drive business outcomes by optimizing operational efficiencies, fostering innovation, and preparing organizations for future challenges.

Open BMKT-101-1: Market Analyst Panel

GAMR 1 (Great America Meeting Room 1), Floor 2

Track: Business Strategies and Memory Markets

Organizer + Moderator:

Jean Bozman, President, Cloud Architects Advisors

Jean S. Bozman is President of Cloud Architects Advisors, a market research and consulting firm focused on hardware and software for enterprise and hybrid multi-cloud computing. She analyzes the markets for servers, storage, and software related to datacenters and cloud infrastructure. A highly-respected IT professional, she has spent many years covering the worldwide markets for operating environments, servers, and server workloads. She was a Research VP at IDC, where she focused on the worldwide markets for servers and server operating systems. She is a frequent conference participant as a speaker, chairperson, and organizer at such events as Flash Memory Summit, OpenStack, and Container World. She is often quoted in a variety of publications including BusinessWeek, Investor’s Business Daily, the Los Angeles Times, CNET, Bloomberg, and Reuters. Ms. Bozman has also been VP/Principal Analyst at Hurwitz and Associates and Sr Product Marketing Manager at Sandisk. She earned a master’s degree from Stanford.

Panel Members:

Camberley Bates, VP and Practice Lead, Futurum Group

Camberley serves as the VP and Practice Lead at The Futurum Group bringing over 25 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm. She joined The Futurum Group through their acquisition of Evaluator Group in 2023. As the Managing Director at Evaluator Group from 2009 until 2023 she built a highly respected team, known for its deep technical expertise delivering competitive and market knowledge backed by data based economic and hands-on experience with the technology and IT consulting services. Camberley began her career at IBM in sales and management. She holds a BS degree in International Business from California State University - Long Beach and executive certificates from Wellesley and Wharton School of Business.

Simone Bertolazzi, Technology and Market Analyst, Yole Intelligence

Simone Bertolazzi, PhD, is Principal Analyst (Memory) at Yole Group. As member of the Yole Group’s Memory team, he contributes on a day-to-day basis to the analysis of markets and technologies, their related materials, device architectures and fabrication processes. Previously, Simone carried out experimental research in the field of nanoscience and nanotechnology, focusing on emerging semiconducting materials and their opto-electronic device applications. He (co-) authored more than 20 papers in high-impact scientific journals and was awarded the prestigious Marie Curie Intra-European Fellowship. Simone obtained a PhD in physics in 2015 from École Polytechnique Fédérale de Lausanne (Switzerland), where he developed novel flash memory cells based on heterostructures of two-dimensional materials and high-κ dielectrics. Simone earned a double M. A. Sc. degree from Polytechnique de Montréal (Canada) and Politecnico di Milano (Italy), graduating cum laude.”

Avril Wu, Senior Research Vice President, TrendForce Corp.

TrendForce Research Vice President Avril Wu has well over a decade of professional experience specializing in various aspects of memory product research. Prior to her 10-year tenure with TrendForce, Avril had worked with an established memory company for more than two years, also covering the same sector. Despite focusing on the DRAM market initially, Avril extended her expertise in 2019 to include NAND Flash as well, meaning she is currently more than qualified to cover the entire memory sector.

Jeff Janukowicz, Vice President, IDC

Jeff Janukowicz is a Research Vice President at IDC where he provides insight and analysis on the SSD market for the Client PC, Enterprise Data Center, and Cloud market segments. In this role, Jeff provides expert opinion, in-depth market research, and strategic analysis on the dynamics, trends, and opportunities facing the industry. His research includes market forecasts, market share reports, and technology trends of clients, investor, suppliers, and manufacturers. Mr. Janukowicz has an extensive background in storage, semiconductors, and solid state technologies. He brings more than 20 years of experience within the technology industry to IDC, including more than 15 years in storage and the semiconductor industry. Jeff has held various leadership positions in marketing and engineering during his career and before joining IDC he was responsible for strategic marketing and business planning activities for Agere Systems, which was acquired by LSI (now Avago).

Panel Session Description:

In a shifting landscape of the DRAM market, the emergence of AI applications brings both challenges and opportunities for stakeholders. DDR5 technology is set to lead the charge in driving innovation and market growth. Our in-depth analysis explores the intricate dynamics of supply and demand, forecasting how DRAM prices will react to market forces. As DDR5 advances towards 1anm and 1bnm processes, alongside the increasing focus on HBM, the intersection with AI becomes paramount. This strategic roadmap provides valuable insights into supply/demand dynamics, capacity adjustments, growth projections, and major supplier strategies in the evolving DRAM market of 2025 and beyond.

Open DRAM-101-1: DRAM Technology-Scaling Challenges & Future Directions

Ballroom C, Floor 1

Track: DRAM

Paper Presenters:

Ataberk Olgun, PhD Student, SAFARI Research Group at ETH Zurich

Paper Title:

Scalable and Low Overhead Read Disturbance Mitigation

Paper Abstract:

DRAM chips are increasingly more vulnerable to read disturbance phenomena (e.g., RowHammer and RowPress), where repeatedly accessing DRAM rows causes bitflips in nearby rows due to DRAM density scaling. Even though many prior works develop various RowHammer solutions, these solutions incur non-negligible and increasingly higher system performance, energy, and hardware area overheads as RowHammer vulnerability worsens. We present an overview of the state-of-the-art RowHammer solutions. We introduce two new RowHammer solutions, ABACuS and CoMeT, that can securely prevent RowHammer bitflips at low chip area, performance, and energy cost. We demonstrate how well the two solutions scale with worsening RowHammer vulnerability, typically quantified with the number of DRAM row activations needed to induce the first RowHammer bitflip (RowHammer threshold) in a DRAM chip. We describe the key insights that make ABACuS and CoMeT low-cost even at a very low, future RowHammer threshold of 125. At this RowHammer threshold, ABACuS and CoMeT incur small performance overheads of 1.45% and 4.01%, on average across 61 workloads from five widely used benchmark suites, respectively.

Author Bio:

Ataberk Olgun is a Computer Architecture researcher and a Ph.D. student in SAFARI Research Group at ETH Zurich, Switzerland, led by Prof. Onur Mutlu. His research interests lie in the intersection between computer architecture and memory system reliability and performance.

Abdullah Giray Yaglikci, Ph.D. Student, SAFARI Research Group at ETH Zurich

Paper Title:

Scalably Mitigating DRAM Read Disturbance via Experimental Insights into Chips

Paper Abstract:

DRAM is the prevalent main memory technology due to its high density and low latency characteristics. The increasing need for faster access rates and larger DRAM capacity motivates improving the DRAM chip density. Manufacturing technology node size shrinks over DRAM chip generations to provide higher DRAM chip density. This technology scaling causes DRAM cell size and cell-to-cell distance to reduce significantly. As a result, DRAM cells become more vulnerable to read disturbance, i.e., accessing a DRAM cell disturbs data stored in another physically nearby cell. To provide a deeper understanding of and solutions to DRAM read disturbance, we 1) conduct experimental studies on real DRAM chips where we investigate the effects of temperature, access patterns, intra-chip variations, and wordline voltage; and 2) propose architecture-level solutions to mitigate DRAM read disturbance while it is exacerbated by technology node scaling and existing mitigations face practicality challenges due to a fundamental need for exposing proprietary information. This talk will provide a summary of these works.

Author Bio:

Giray is a Ph.D. candidate in the Safari Research Group at ETH Zürich, working with Prof. Onur Mutlu. His current broader research interests are in computer architecture, systems, and hardware security with a special focus on DRAM robustness and performance. In particular, his PhD research focuses on understanding and solving DRAM read disturbance vulnerability. Giray has published several works on this topic in major venues such as HPCA, MICRO, ISCA, DSN, and SIGMETRICS. One of these works, BlockHammer, was named as a finalist by Intel in 2021 for the Intel Hardware Security Academic Award. Giray's research is in part supported by Google and the Microsoft Swiss Joint Research Center.

ByeongSoo Kang, ETCH ENGINEER, SK hynix

Paper Title:

Plasma Etching Behavior of Y2O3 coatings by SF6 Plasma Pre-Treatment

Paper Abstract:

As DRAM cell scaling reaches its limit, SK Hynix is conducting various studies to continue the advancement of DRAM technology. Engineers face several challenges in overcoming the limitations of technology. One of the most significant issues faced by the industry is the coating material of the inner chamber wall. because fluorine-based gas is more required as we are entering into a smaller DRAM technology node. In order to meet the requirements for future coating material of the inner chamber wall, it is therefore imperative to develop a coating material with higher erosion resistance, better chemical stability, and fewer contamination particles. The coating material of the inner chamber has been upgraded from SiO2 to Al2O3 to Y2O3. But, recently many engineers have focused on yttrium oxide coating parts to solve the issue of reducing the initial etching rate in semiconductor process chambers. In this study, it was studied how SF6 plasma pre-treatment affects the initial etching rate shift. After pre-treatment with SF6 plasma, the surface of the Y2O3 coating was fluorinated to form a chemically stable YOxFy film. Then, as a result of the SNC partition process, the variable etch time shift was reduced by 66.7% (3.69"â1.23"). The initial CD degradation was improved by 83% (4.41â0.48). These results indicate that the surface of the Y2O3 coating, which was pre-treated with SF6 plasma, is more erosion-resistant than the non-treated Y2O3 film. Therefore, YOxFy film minimizes the shift of the initial etching rate in SNC partition etch process.

Author Bio:

ByeongSoo.Kang is currently serving as the Storage Node Contact(SNC) Engineer at SK Hynix. He is responsible for leading SNC Process dedicated to the yield improvement and increased productivity.

Ju Jin An, STSM, IBM

Paper Title:

Enhancing Generative AI with 3D DRAM and Advanced Memory Architectures

Paper Abstract:

This paper explores the evolving landscape of memory architectures to meet the growing demands of Generative AI applications. With the increasing complexity of AI models and the need for high-capacity memory solutions, there is a pressing demand to efficiently load model parameters from memory to local caches or registers. To address this challenge, the adoption of a 3D stackable DRAM approach is deemed inevitable. The paper focuses on various technical approaches driving the memory industry towards enhanced memory capacity. These include innovative technologies such as High Bandwidth Memory (HBM) with Through-Silicon Via (TSV), Cell Over Peripheral (COP) DRAM architecture, and the pioneering 4F2 architecture. By discussing these advancements, the paper sheds light on the promising future of memory architectures in accelerating Generative AI applications.

Author Bio:

Ju Jin serves as a Senior Technical Staff Member at IBM's Infrastructure Supply Chain Organization, drawing upon more than twenty years of experience in the semiconductor industry. Her expertise lies in silicon fabrication processes and process integration, areas critical to her leadership in advancing the main memory system for IBM's Power and z Systems. She holds an MS/Ph.D. in Chemical Engineering from MIT, solidifying her academic foundation and enhancing her contributions to the field.

Paper Session Description:

In this session, we delve into the realm of enhancing Generative AI with cutting-edge memory architectures. Faced with the ever-increasing demands of AI applications, the shift towards 3D DRAM technology is deemed essential. We will discuss technical innovations such as HBM with TSV, COP DRAM architecture, and the groundbreaking 4F2 architecture, and the future for memory architectures in bolstering Generative AI applications. We will also examine challenges in DRAM technology and solutions to combat vulnerabilities in DRAM chips, ensuring optimal performance without incurring unnecessary overhead.

Open FARP-101-1: FDP and ZNS

Ballroom D, Floor 1

Track: Flash Architectures and Provisioning

Organizer + Moderator:

Brian Berg, President, Berg Software Design

Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley Section, Director and past Chair of the Consultants Network of Silicon Valley, Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for Outstanding Service to the Consulting and Electrical Engineering profession, and the 2012 Outstanding Leadership and Professional Service Award for Region 6.

Paper Presenters:

Mariusz Barczak, Principal Engineer - Storage Software Architect, Solidigm

Paper Title:

Cloud Storage Acceleration Layer: Leveraging Gen5 FDP NVMe Technologies

Paper Abstract:

Cloud Storage Acceleration Layer (CSAL) is a sophisticated software solution designed to provide a high-density and high-performance local disks for cloud storage, thereby reducing user costs associated with storage infrastructure. The forthcoming generation of CSAL is positioned to leverage emerging NVMe technologies, including NVMe Gen5 devices and Flexible Data Placement (FDP), to further drive down expenses. In the upcoming iteration of CSAL, TLC Gen5 NVMe devices are proposed as cache devices, offering a cost-effective alternative to traditional Storage Class Memory (SCM). Additionally, the integration of FDP technology enables CSAL to optimize both cache and backend capacity storage, effectively segregating user data streams between these components. This strategic segregation minimizes the system's WAF, resulting in enhanced overall efficiency. In summary, CSAL represents a pioneering approach to leveraging forthcoming NVMe technologies for the development of a high-performance, cost-effective storage solution. This talk will explore the integration of these technologies within CSAL, highlighting their potential to revolutionize cloud storage infrastructure.

Author Bio:

Mariusz is a Principal Engineer in Solidigm. His storage software and storage solutions experience is over 12 years. His work area is finding innovations for storage software. In particular caching solutions, software defined storage, virtualization, and storage analytics. This is confirmed by numerous patents and open source activity. His recent work is focused on leading the team of Cloud Storage Acceleration Layer (CSAL) which delivers mixed media solutions combining Solidigm SLC with other storage components like Soldigim QLC SSD drives, to deliver efficient and durable storage.

Jonmichael Hands, Sr Director Strategic Planning, Fadu

Paper Title:

FDP Performance in VMs with Multiple NVMe Namespaces: Case Studies

Paper Abstract:

Hyperscalers are looking to improve flash efficiency, workload performance, and TCO. Cloud-native workloads are dominant, and larger SSDs now host many different applications, virtual machines, and containers. Flexible Data Placement (FDP) allows multiple applications to run on the same SSD while optimizing performance and endurance by intelligently placing like-data together to improve garbage collection efficiency. FDP drives are fully backwards compatible, so end-users can mix legacy software applications and new FDP enabled applications on the same drives across a cluster or fleet of drives. We will explore which applications can benefit from FDP with proof points and case studies from hyperscale database, caching, multiple namespaces and VMs. We will look at what application benefits can be achieved without any custom FDP-aware development.

Author Bio:

Jonmichael (JM) is a storage market expert, blockchain supporter, and sustainability leader. Jonmichael spent ten years at Intel in the Non-Volatile Memory Solutions group working on product line management, strategic planning, and technical marketing for the Intel data center SSDs. In addition, he served as the chair for NVM Express (NVMe) marketing, co-chair of the SNIA (Storage Networking Industry Association) SSD special interest group, and is active in Open Compute Project storage and sustainability projects. He was VP of Storage at Chia Network and remains an advisor. Jonmichael is the treasurer and secretary of the Circular Drive Initiative, 501(c)(6) non-profit, promoting the secure reuse of drives and circular business models for the storage industry. Jonmichael started his storage career at Sun Microsystems designing storage arrays (JBODs) and holds an electrical engineering degree from the Colorado School of Mines.

William Cheng, Director, Enterprise Marketing, Silicon Motion

Paper Title:

Flexible Data Placement (FDP) Benefits in QLC Applications: A Case Study

Paper Abstract:

1. Demand for QLC adoption in the Enterprise storage market 2. Challenge of using QLC NAND 3. Introduction of Flexible Data Placement (FDP) Technology 4. An example of how FDP is used in a high-capacity QLC NAND application 5. Analysis to show the benefits of using FDP in QLC application

Author Bio:

William Cheng is Director of Marketing at Silicon Motion. He leads a focused team in defining and promoting Enterprise controllers and development platforms that accelerate High Performance, Data Center SSD development. William has over 25 years in developing and marketing innovative storage products and solutions for the enterprise market. He has held various engineering and marketing positions at Western Digital, Microchip, Toshiba, and Intel. He earned a BSEE and MSEE at Purdue University.

Matias Bjorling, Distinguished Engineer and Country Manager, R&D Engineering, Western Digital

Paper Title:

Zoned Storage: Past, Present, and Future

Paper Abstract:

Zoned storage is now widely available across various types of storage devices, such as host-managed SMR HDDs (ATA/SCSI), SSDs with Zoned Namespace support (NVMe), and embedded devices (Zoned UFS). It is being deployed from hyperscaler data centers to mobile phones, and is proving to be an effective way to reduce TCO and environmental impact on CO2 while improving overall system performance. Over the past decade, a standard software stack has been developed to support these devices, providing a robust and scalable implementation to support the broad ecosystem. This software stack now has general support across multiple file systems, such as f2fs, btrfs, and Ceph, and it allows zoned storage device benefits to be used without any software changes. This presentation will discuss zoned storage's past, present, and future. We will explore the forthcoming scalability benefits that support zoned storage, as well as recent advancements in XFS that aim to clear the remaining storage stack obstacles.

Author Bio:

Matias Bjorling is currently serving as a Distinguished Engineer at Western Digital, where he leads the Emerging System Architectures R&D group. His areas of expertise include hardware/software co-design, emerging memory and storage architectures, and industry-wide ecosystem enablement through standardization and software development. Matias has played a key role in co-chairing the NVMe Zoned Namespace Command Set specification and is leading Western Digital's efforts towards ecosystem enablement. Hans Holmberg is a senior research scientist at Western Digital. He is the author of ZenFS and a driving force behind zoned storage, and an active contributor to the Linux storage ecosystem.

Rory Bolt, Principal Architect, KIOXIA

Paper Title:

Flexible Data Placement (FDP): What Every Storage Architect Should Know!

Paper Abstract:

FDP is a powerful new standard that provides unprecedented control to application writers and storage system architects on how their data will be organized within a Solid State Disk (SSD). The primary benefit of the new functionality provided by FDP is the ability to reduce Write Amplification (WA), which affects device lifespan and performance. However, many factors about how SSDs work, how data is written, and how operating systems support FDP can affect the level of WA improvement that can be achieved. This presentation will provide (1) a brief overview of FDP functionality, (2) how required functionality within an SSD is affected by FDP, (3) what applications can do to maximize the benefits of FDP, (4) how FDP configurations can affect the solutions costs of FDP, (5) how the Linux operating system interacts with FDP, (6) the implications for applications and storage systems, and (7) aspects of utilizing FDP that can affect the results that your applications and storage systems will achieve.

Author Bio:

Rory joined KIOXIA America in 2017. He has founded, built teams, and delivered product at four storage startups which were acquired. Rory has more than twenty-five years of experience in data storage systems, data protection systems, and high performance computing with tenures as VP software Engineering at Samsung, Technical Director/CTO counsel at NetApp, CTO counsel at EMC, Vice President, Chief Storage Architect, and Distinguished Fellow at Quantum. Rory has been granted over 12 storage related patents and has several pending.

Paper Session Description:

The demand for QLC adoption in the Enterprise storage market continues to grow, but the challenge of using QLC NAND has been a hindrance. However, the introduction of Flexible Data Placement (FDP) Technology is changing the game. FDP is being utilized in high-capacity QLC NAND applications to optimize data placement, improving performance and reducing costs. The benefits of using FDP in QLC applications are evident, as seen in increased efficiency and lifespan of devices. In a similar manner, Cloud Storage Acceleration Layer (CSAL) is leveraging Gen5 FDP NVMe Technologies to provide a high-density and high-performance local disks for cloud storage, reducing user costs and driving down expenses. Furthermore, FDP is a powerful new standard that every storage architect should be aware of, allowing for unprecedented control over data organization within SSDs. By reducing Write Amplification, FDP enhances device performance and lifespan. Finally, FDP performance in VMs with multiple NVMe namespaces has been proven through case studies, showcasing the benefits for hyperscalers and cloud-native workloads. Zoned storage, on the other hand, has become widely available across various storage devices, proving to be an effective way to reduce TCO and improve system performance. The past, present, and future of zoned storage will be discussed, highlighting the scalability benefits and advancements in software support.

Open INVT-101-1: Invited Talk with Andrew Tomlin

Ballroom E, Floor 1

Track: Invited Talks

Organizer + Chairperson:

Leah Schoeb, Sr. Developer Relations Manager, AMD

Leah Schoeb is a Sr Developer Relations Manager in AMD's platform architecture team, where she engages with solid state storage vendors on storage technology futures. She has over 25 years of experience in the computer industry, and was previously Acting Director of Reference Architecture at Intel where she led a team of segment managers and architects managing cross functional teams for flash- and NVMe-based data solutions. Leah has held management and engineering positions at VMware, Dell, and Sun Microsystems, and was also a Senior Partner at the analyst firm Evaluator Group, where she focused on storage, virtualization, and cloud infrastructure. Leah has ten technical publications, and has presented at many technical conferences. Her MBA us from the Univ. of Phoenix, and heer BSEE is from the Univ. of Maryland, College Park.

Paper Presenters:

Andrew Tomlin, CEO, QiStor

Paper Title:

Hardware-Accelerated Key-Value Databases as a Service

Paper Abstract:

The advancements in storage acceleration technology have not kept pace with other technological domains, such as AI. Key-Value databases have emerged as the fastest-growing database technology, crucial for powering webscale applications and services. In this presentation, we delve into an NVMe Key-Value solution employing FPGAs within the data center, and its potential benefits for customers. It will offer insights into the workings of Key-Value databases with traditional flash devices, and will highlight how the device-level Key-Value interface revolutionizes the landscape by impacting both cost and performance. It will also explore the hurdles encountered in developing this technology, and will propose solutions that can be extrapolated to other hardware projects.

Author Bio:

Andy Tomlin is Founder, CEO and Principal Architect at QiStor, a startup developing a hardware-accelerated, flash-based, Key-Value-as-a-Service solution for data centers. He is a 30-year industry veteran with extensive experience in flash management and controller architecture, and has delivered many flash-based products to both the client and enterprise spaces. Andy has led multiple leading-edge controller and firmware development projects while holding executive and VP Engineering positions at multiple flash and controller vendors including SanDisk, SandForce, WD, Samsung, and KIOXIA. He has presented on these topics numerous times over the years at Flash Memory Summit, and he holds over 60 patents in these areas.

Paper Session Description:

In this Invited Talk, Andrew Tomlin, founder of QiStor, will discuss how advancements in storage acceleration technology have not kept pace with other technological domains, such as AI. Key-Value databases have emerged as the fastest-growing database technology, crucial for powering webscale applications and services. He will examine an NVMe Key-Value solution employing FPGAs within the data center, and its potential benefits for customers, and will offer insights into the workings of Key-Value databases with traditional flash devices, and how the device-level Key-Value interface revolutionizes the landscape by impacting both cost and performance. He will also explore the hurdles encountered in developing this technology, and will propose solutions that can be extrapolated to other hardware projects.

Open SPOS-101-1: Boost Memory Capacity & Performance For Modern Workloads with CXL

Ballroom A, Floor 1

Track: Sponsored Sessions

Sponsor:

CXL Consortium

Organizer + Moderator:

Kurtis Bowman, Director, Server System Performance, AMD

Kurtis Bowman is Director, Server System Performance at AMD and Marketing Workgroup Co-Chair of the CXL Consortium. With more than 25 years of experience in the architecture, development, and business justification of server, storage, commercial, and consumer computing products, his current areas of interest include converged and hyperconverged systems, heterogeneous compute elements for HPC & machine learning, and data analytics. He has built teams and managed firmware and hardware development through entire lifecycles in both startups and mature companies. Mr. Bowman earned a BSEE from New Mexico State University, holds multiple patents, and has written articles in the technical and trade press.

Panel Members:

Su Wei Lim, , Micron

Hoshik Kim, , SK hynix

Chris Petersen, Fellow, Technology and Ecosystems, Astera Labs

Chris Petersen is a Fellow at Astera Labs. Chris has been designing and building servers, storage, and datacenter solutions for over 14 years. He is a board member of the NVM Express Standards Organization. He has spoken on NVMe at many conferences, including the Open Compute Summit and the Non-Volatile Memory Workshop. He has earned six patents and has held engineering positions at Dell and HP. He earned MS and BS degrees in electrical and computer engineering from Cornell.

Kapil Sethi, Director, New Business Planning Team, Samsung Seminconductor Inc

Kapil is currently Director in the New Business Planning team at Samsung Semiconductor where he leads technical product planning for Samsung’s CXL® technology based products. He has been at Samsung Semiconductor for 3 years. Previously, Kapil has worked as Product Manager leading multi-million dollar product lines.

Panel Session Description:

Compute Express Link (CXL) is a cache-coherent interface that enables memory expansion and heterogeneous memory for disaggregated systems. CXL technology helps reduce storage latency, boost system performance and efficiency, and break through the limitations of current memory interface technology. This panel will share data points from CXL technology implementations to show how CXL meets the memory capacity and bandwidth needs for AI, HPC, and in-memory database applications. Attendees will gain insights into the solutions that are readily available within the market.

Open SSDT-101-1: Flash & Memory Controller Technologies for AI

Ballroom F, Floor 1

Track: SSD Technology

Organizer:

Erich Haratsch, Senior Director Architecture, Marvell

Erich Haratsch is Senior Director Architecture at Marvell, where he leads the architecture definition for Bravera SSD controllers and other memory-based products. Prior to joining Marvell, he worked at Seagate and LSI, where he worked on Nytro and SandForce branded SSD controllers. Earlier in his career, he developed signal processing and error correction technologies for multiple generations of HDD controllers at LSI and Agere Systems. He started his career at AT&T and Lucent Bell Labs, where he worked on Gigabit Ethernet over copper, optical communications and the MPEG-4 video standard. He is the author of over 40 peer-reviewed journal and conference papers, and holds more than 200 U.S. patents. He also is a Senior Member of IEEE, and earned his MS and PhD degrees from the Technical University of Munich (Germany).

Paper Presenters:

Dr. Tao Lu, Research Manager, DapuStor

Paper Title:

CXL2P: Addressing DRAM Shortages in Large-Capacity SSDs and Reducing Cost

Paper Abstract:

The traditional best practice of utilizing 4KB page granularity for SSD address translation is being challenged due to shortages in onboard DRAM, especially as enterprise-level SSDs approach 100TB and PB-level SSDs emerge. The limited DRAM cannot accommodate the entire page mapping table. Existing solutions propose larger mapping granularity (e.g., 16KB) and learned indexes to reduce memory footprint, but these approaches suffer from suboptimal random write performance and limited applicability. The advent of the CXL protocol presents new opportunities for large capacity SSDs to retain optimal 4KB page mapping granularity. We have investigated the feasibility and advantages of leveraging CXL.cache to supplement SSD memory for page indexing and introduced an innovative CXL-based tiered memory and index architecture, cxL2P. This architecture is designed to fundamentally address the onboard DRAM shortage issue and support fine-grained page mapping for large-capacity SSDs without compromising performance.

Author Bio:

Dr. Tao Lu is a seasoned researcher in the storage domain. Dr. Lu currently serving as the R&D Manager at DapuStor, a leading enterprise specializing in SSD controller chip design and customized intelligent SSD solutions. With expertise in SSDs and data compression, Dr. Lu has been instrumental in driving storage innovation at DapuStor. As the technical lead, he spearheaded the development and mass production of the company's first-generation computational storage drives.

Licheng Xue, ASIC digital design manager, Starblaze

Paper Title:

Dynamic data loading from Flash to DRAM for LLM inference

Paper Abstract:

Large language models (LLMs) cost too much DRAM to store all the model parameters for inference. To perform inference using the Llama2-13B model, you’ll need to store approximately 26GB model parameters in DRAM, which is challenging to provide, especially for edge LLM inference platforms, such as AI PCs and AI phones. While DRAM cannot provide sufficient capacity to store parameters, Flash can offer it but cannot provide the required read latency and throughput. We propose to keep part of model parameters in DRAM and all model parameters in Flash devices, dynamically exchange the new parameters with the old useless ones during LLM inference. Two key issues are addressed: “which parameters should be loaded?” and “How to improve the loading latency and throughput?”. Our methods enable efficient inference for devices with insufficient DRAM.

Author Bio:

Obtained doctoral degree from Beijing Institute of Technology. Occupied in Starblaze, specializing in the architecture design of SSD controllers and AI chips. Participated in the tape-out process of four SSD controller controllers. Presenter of FMS19.

Vasanthi Jagatha, Senior Manager, Product Marketing, Marvell

Paper Title:

Flash Controllers for the AI Era

Paper Abstract:

Gen AI has a wide range of applications. Depending on the application, data management, workload for the memory / storage varies significantly. Every stage (Data Ingestion, Training, Inference, RAG, etc.) has nuanced flash SSD storage requirements needing the right mix of SSD controller features like high random performance and host management capability. In addition to solving storage challenges, the right SSD controller can innovatively alleviate the significant memory constraints placed by the ever-increasing volume of raw and ephemeral data that is generated by Gen AI applications. In this presentation, we will walk through the storage and memory needs of the Gen AI data pipeline and craft the optimal storage controller for Gen AI workloads.

Author Bio:

Vasanthi Jagatha is Senior Manager of Product Marketing, Flash SSD team in the Custom, Compute & Storage Group at Marvell. In this role, Vasanthi is responsible for custom flash controller initiatives. Vasanthi has also managed cloud and enterprise flash controller product lines. Vasanthi joined Marvell from Intel where she held product management, business development and research engineering roles for Storage and FPGA products. Vasanthi earned a master’s degree in Electrical Engineering and a bachelor’s degree in Computer Systems Engineering from Arizona State University.

Yuyang Sun, Product Marketing Engineer, Solidigm

Paper Title:

Flash Storage in the AI Era

Paper Abstract:

In recent years, the advent of artificial intelligence (AI) has ushered in a transformative era in computing, where data processing speed and efficiency have become paramount. The existing datacenter infrastructure and edge devices have encountered challenges in keeping up with the escalating demands imposed by AI applications. Rapid demand growth in the fields such as compute, memory, and networking has revealed the growth potentials and underscored the urgency of addressing the limitations to better accommodate the new requirements of the new AI era. As AI technology continues to advance, it is important to understand how flash storage is likely to evolve as part of the AI hardware infrastructure. This presentation aims to comprehensively examine the hardware infrastructure requirements for AI with a focus on storage. We will evaluate the existing technologies and identify those essential to fortify support for the ongoing AI revolution. Furthermore, our discussion will delve into the pivotal role that flash storage can play in shaping a more efficient and potent future for AI by optimizing data-intensive tasks and enhancing overall system performance and power efficiency.

Author Bio:

Yuyang Sun, Senior Manager of Product Marketing at Solidigm, has over a decade of experience in SSD storage design, business planning, marketing, and strategy. Her day-to-day interactions with major industry players have allowed her to gain invaluable insights into the world of data center storage solutions, and she has been actively involved in managing data center QLC SSD products since their inception. Yuyang holds a Bachelor's and Master's degree in Electrical Engineering from University of British Columbia and an MBA from the Wharton School of Business. In her leisure time, she enjoys playing badminton and even co-founded a local badminton club with hundreds of active members.

Paper Session Description:

In the ever-evolving landscape of artificial intelligence (AI), the demand for faster and more efficient data processing is at an all-time high. Flash storage technology has emerged as a pivotal player in the AI hardware infrastructure, offering the potential to optimize data-intensive tasks and enhance system performance. However, challenges such as dynamic data loading from Flash to DRAM for LLM inference and finding the right flash controllers for Gen AI applications have arisen. Additionally, the innovative CXL2P protocol has been introduced to address DRAM shortages in large-capacity SSDs and reduce costs, ensuring optimal performance without compromising efficiency. Join us as we explore the exciting possibilities of flash storage in the AI era.

Open UCIC-101-1: UCIe Solution Technology Innovations NEW

Ballroom G, Floor 1

Track: UCIe and Chiplets

Organizer:

Brian Rea, Technology Initiative and Ecosystem Enablement Manager, Intel

Brian Rea has served as a marketing work group co-chair of UCIe since 2022 and is a Technology Initiative and Ecosystem Enablement Manager at Intel. Rea holds a MBA from the University of Washington and a B.S. in Electrical Engineering from the University of Texas at Austin.

Paper Presenters:

David Kulansky, Director of Product Marketing, Alphawave Semi

Paper Title:

High Performance Disaggregated Systems through UCIe Interconnects and Chiplets

Paper Abstract:

The rapid advancement of semiconductor fabrication processes and the increasing demand for high-performance computing have necessitated the development of disaggregated systems, which offer enhanced flexibility, scalability, and resource utilization. By leveraging UCIe Die-to-Die interconnects, these systems enable efficient communication between different components leading to improved performance and reduced power consumption. In this session, we will delve into the core principles of UCIe, including their low latency, low power consumption, and interoperability. We will discuss how UCIe enables a unified interconnect ecosystem for IO, memory, and accelerator based chiplets which can revolutionize diverse domains such as data centers, edge computing, artificial intelligence, autonomous systems, and high-performance computing. We will also touch on how chiplets enable both common and new connectivity use cases like IO/memory disaggregation and 2.5D co-packaged optics.

Author Bio:

Dave Kulansky is Director of Product Marketing at Alphawave Semi focused on High-Speed IO. Dave has 20+ years of semiconductor experience, focused on mastering best fit solutions to streamline new product development. Before joining Alphawave, Dave held positions in AMS, RF & SerDes design, but he most recently focused on PCIe & Ethernet solutions.

Randy White, Memory Solutions Program Manager, Keysight

Paper Title:

UCIe and how to enable an open chiplet ecosystem

Paper Abstract:

The demand for high performance, power efficient computing solutions to address next-generation workloads has caused the industry to shift from monolithic designs to Systems in Package (SiP). While modular architectures allow design teams to re-use individual components and replace only those that have the largest impact to the end product, the standardization of die-to-die interfaces is crucial to achieve it at scale. Universal Chiplet Interconnect Expressâ¢, an emerging die to die interconnect standard, will revolutionize the industry due to its compliance and intercompatibility program which enable a truly open chiplet ecosystem. In order to realize that vision, the right set of test and validation tools pre- and post-packaging must be available, such that designers are ensured the interconnected chiplets will function as desired. This presentation will explore the test and validation challenges involved with die-to-die interconnects, and discuss some proposals to overcome these challenges.

Author Bio:

Randy White is the Memory Solutions Program Manager for Keysight Technologies. He is focused on test methodologies for emerging memory technologies in server, mobile and embedded applications. Randy has spent the last 20 years investigating signal integrity measurement techniques including de-embedding algorithms, measurement/model correlation and high speed measurements for real-time & sampling oscilloscopes as well as BERTs & AWGs. He has participated on many standards committees including UCIe, PCI-SIG, USB-IF, SATA-IO, and JEDEC to help define new test methodologies and is currently the chair of the JEDEC JC40.5 Logic Validation subcommittee. He graduated with a BSEE from Oregon State University.

Nilesh Shah, VP, Business Development, ZeroPoint Technologies

Paper Title:

Chiplet-Based Compressed LLC Cache & Memory Expansion

Paper Abstract:

HBM, Non-volatile, DDR memory chiplets, and LLC cache chiplets play a pivotal role in overcoming memory and SRAM scaling challenges in data centers and smart devices. However, the Total Cost of Ownership (TCO) associated with chiplet-based memory and cache presents a hurdle for hyperscale deployment. Introducing a cutting-edge hardware-accelerated chiplet IP that achieves real-time memory compression (2-4X) at CACHE LINE granularity, with sub 10ns latency. This IP seamlessly integrates with SRAM (xRAM) LLC, Nonvolatile, and UCIe/CXL-connected memory chiplets, enhancing TCO cost-effectiveness ($$/GB) while preserving performance. When paired with a high-speed coherent mesh network and protocol within an SoC, substantial return-on-investment is realized. This configuration offers unmatched flexibility and efficiency in resource management. The presentation elucidates the architectural components that seamlessly integrate with existing chiplet ecosystem elements. The overarching goal is to present viable options for mitigating adoption barriers associated with memory and LLC cache chiplets, particularly in large memory applications across Cloud, Hyperscale, and Automotive segments.

Author Bio:

Nilesh currently leads Business Development at ZeroPoint Technologies where he is responsible for engaging Hyperscalers, Memory Module , controller and processor/accelerator manufacturers to develop Data Center and Smart Device solutions . He's an active member of the CXL Consortium, JEDEC, SNIA, represents the company at OCP. Previously, Nilesh developed Data Center SSD products and Computational Storage initiatives at Intel and holds several patents in this area. Nilesh runs several Meet Up Communities with upwards of 5000 active members and serves as an Advisor to several other companies in the Emerging Memory Technology IP and SoC space.

Prashant Dixit, Senior Engineering Manager, Siemens EDA

Paper Title:

Verification Challenges and Solutions for Multi-Die Systems

Paper Abstract:

Multi-die systems accelerate the scaling of system functionality and facilitate the creation of new product variants but with new challenges in functional verification. Verifying a UCIe design includes sideband training, arbitration, lane repair and reversal, validate various requests and responses, scoreboarding across power cycles and reset types and all components in the dies from a system-level perspective. We will discuss the verification solutions for chiplet designs - full stack, d2d adapter, logphy, from planning to closure. Access to various flit types, sideband packet types, LTSM states, and other data structures will be done using UVM features like callbacks and analysis components, common APIs for PCIe, CXL, and streaming modes make the solution highly adaptable for high-level stimulus. We will see strategies to make the die-level testbench reusable and synchronized to ensure that data arrives with the expected throughput and latency with a case study that demonstrates how these techniques, along with a flexible and open architecture, exhaustive compliance test suite and efficient debug mechanism, help UCIe customers verify designs and achieve less time to market.

Author Bio:

Prashant Dixit is currently working on the development of verification solutions for UCIe-based designs at Siemens EDA. With a strong background in the storage domain, he also manages the Storage Verification IPs team, focusing on the development and testing of NVMe and NVMe over Fabrics testing solutions. Prior to his role at Siemens EDA, Prashant gained valuable experience at Samsung, where he contributed in the design and verification of IPs and SoC of networking and storage domains. Prashant holds a Master of Engineering degree in Microelectronics from BITS Pilani, which he completed in 2006. He also earned a Bachelor of Technology in Electronics and Communication from Uttar Pradesh Technical University in 2004.

Paper Session Description:

In this session, we will first examine how chiplet-based dompressed LLC cache and memory expansion utilizes cutting-edge hardware-accelerated chiplet IP to overcome memory and SRAM scaling challenges in data centers and smart devices. This IP achieves real-time memory compression with sub 10ns latency, seamlessly integrating with various memory chiplets while enhancing cost-effectiveness and preserving performance. We will then discuss how to address the challenges in functional verification for UCIe designs, offering strategies for die-level testbench reuse and synchronization. We will then explore how UCIe enables efficient communication between components for improved performance and reduced power consumption. UCIe and how to enable an open chiplet ecosystem discuss the standardization of die-to-die interfaces and the importance of test and validation tools for an interconnected chiplet ecosystem.

09:45 AM to 10:50 AM

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PRO AIML-102-1: Storage for AI: Applications

Ballroom B, Floor 1

Track: AI and ML Applications

Organizer:

David McIntyre, Director Product Planning, Samsung Electronics

Paper Presenters:

Swapna Yasarapu, Azure Storage Architecture, Microsoft

Paper Title:

Storage Media & Architecture for AI Workloads

Paper Abstract:

AI workloads bring uniqueness associated with how they generate and store data while leveraging existing storage infrastructure. Lifecycle of Storage in AI involves local caching and persistent storage, while the data is acquired, processed, modeled, trained, refined, and stored. AI workloads are generating some interesting storage patterns, that could influence the direction of future Storage Media and Architectures, to make them more AI workload specific, which will be the focus of this talk.

Author Bio:

Swapna Yasarapu has over 25yrs in the storage industry spanning responsibilities ranging from ASIC design, systems engineering, product management and P&L management. Swapna has been a key player in the flash industry - in the definition and productization of new flash form factors (SFF8639, EDSFF) as well as her multi-year tenure as NVMe board member contributing to bringing NVMe as the mainstream interface for the industry.

John Mazzie, Senior Solutions Engineer, Micron Technology

Paper Title:

Analyzing workloads using storage as memory replacement for large model training

Paper Abstract:

Dataset training sizes continue to grow, and larger models may not fit into system memory. In this situation, data loaders need to access models located on flash storage. One such method is a memory mapped file stored on SSDs, though this process can slow training down significantly. New methods that take advantage of the parallelism provided by modern NVMe devices, can make a huge difference in training these large models. We will dive into the analysis of workloads for large training models, showing how they take advantage of modern devices and what kinds of workloads that these devices are experiencing.

Author Bio:

John is a Member of Technical Staff, Systems Performance Engineer at Micron Technology, working on application tracing and data analysis for SSD development since 2016. Previously, he worked in the storage group at Dell Technologies and has a M.S. in Electrical Engineering from West Virginia University.

Surendar Saini, Engineering Manager, Solidigm

Paper Title:

Performance of Solidigm SSDs with NVIDIA GPUDirect Storage for AI Configuration

Paper Abstract:

NVIDIA GPUDirect® Storage (GDS) enables a path for direct memory access (DMA) transfers between the GPU and storage device in a system, allowing data to be moved without any intermediate copies in the CPUs memory. This leads to increased system bandwidth while decreasing latency and CPU utilization. The proposed presentation will share the configuration that was used for the testing (this GDS configuration is also supported on the DGX A100 system, the world's first 5-petaFLOP AI system built with a new generation of GPUs). We will share results of our testing which shows a 2.2x increase in GPU operations, Throughput and Latency in this configuration compared to when CPU is involved in the data transfer from storage device. The data also will show that CPU utilization is lower with GDS configuration since a lot of the transfer overhead is handled by the GPU/SSD.

Author Bio:

I am currently an Eco-System engineering manger at Solidigm. In my position I am responsible for validating our Solid State Drives with eco-system partners that provide next generation enterprise systems (x86 and arm based CPU and GPU vendors) as well as system components (retimers, redrivers, RAID card and Switch vendors). I have spent >25 years at Intel working in various capacities including component design engineer, system validation manager and FW engineering manager. After transitioning to Solidigm I have started leading the eco-system validation team, we are responsible for all certification and eco-system compatibility validation activities at Solidigm

Paper Session Description:

This session examines a variety of approaches and applications used in storage for artificial intelligence, including direct memory access transfers between the GPU and storage device, eliminating the need for intermediate copies in CPU memory. We will also discuss RAG optimized SSD solutions for the Generative AI era, and explore how storage media and architecture are evolving to cater to AI workloads. Join us in analyzing workloads using storage as memory replacement for large model training.

Open BMKT-102-1: Memory Markets

GAMR 1 (Great America Meeting Room 1), Floor 2

Track: Business Strategies and Memory Markets

Organizer + Chairperson:

Jean Bozman, President, Cloud Architects Advisors

Paper Presenters:

James Pan, Senior Principal Engineer Project Manager, Northrop Grumman

Paper Title:

Techniques to Fabricate Ultra-Fast Sub-1nm Photonic SRAMs

Paper Abstract:

Traditionally, CMOS is not considered a light emitting device. Photonic CMOS – which includes a tunnel LED or threshold-less ultra-low resistance laser in the drain region, and photon sensors (avalanche photo diode) in the drain / well regions as one integral transistor – is a light emitting device, similar to laser and LED. CMOS can also be a microwave generating device. In this paper, we will look into ways of how to design a CMOS inverter, and ultra-highspeed SRAM (Static Random Access Memory), using the Photonic Millimeter Wave CMOS technology, for Optical Computing. Inverter and SRAM (in cache memories) are critical components in ULSI processors or RF ASICs. The Photonic CMOS Inverter and Photonic SRAM are 100% compatible to existing CMOS manufacturing and circuit designs. Nonlinear optical materials, as well as optical processes, such as optical filtering and polarization, can be used to further improve the Photonic SRAM speeds.

Author Bio:

James Pan is a Senior Principal Engineer and Project Manager in Northrop Grumman Corporation. He received his Ph.D. from Purdue University, MSEE from University of Texas at Austin, and BSEE from National Taiwan University. He worked for IBM (T. J. Watson Lab. and E. Fishkill), AMD, Micron Technology, Atmel Corporation, Fairchild Semiconductor, and Semicoa Corporation. Dr. Pan started American Enterprise and License Company in 2009.

Ronen Hyatt, Founder and CEO, Unifabrix

Paper Title:

Breaking the Memory Wall - here and now!

Paper Abstract:

Do you have a memory-bound cluster? Would you like to overcome the Memory Wall today? this presentation will show the technologies implemented in current and future Memory Pool technologies including real use cases, performance numbers, and TCO model. After this presentation, you will know the Pros and Cons of Memory Pooling.

Author Bio:

Ronen is an expert in system architectures with over 25 years of experience leading and delivering silicon designs running Compute acceleration cores, DSAs, CXL and Ethernet connectivity, RDMA networking and programmable switches. Ronen has served as CTO and lead architect in multiple leading silicon companies, including Intel, where he co-founded the IPU (Infrastructure Processing Unit) and initiated the programmable Ethernet connectivity development. Ronen is Founder and CEO at UnifabriX, a system and silicon startup targeting the Memory Wall with CXL-based Software-Defined Memory Pools and CXL Fabrics. Ronen holds more than 40 patents (some pending), an MSc and BSc in Computer Engineering from Technion Institute of Technology, and MA in Law from Bar-Ilan University.

John Lorenz, Senior Analyst, Yole Group

Paper Title:

Memory market recovery and focus on datacenter and CXL demand

Paper Abstract:

The DRAM and NAND markets are rebounding from their worse levels of profitability in over a decade. Where are the green shoots for the ongoing recovery? Which aspects of the forecast contain upside and downside risk? Can we expect to see another cyclical downturn in the coming years? As a general market overview, this presentation will discuss Yole's perspective on memory supply and demand, pricing and margins, and memory industry capex through 2029. As datacenter is the most important piece of DRAM demand, there will be an additional examination of how the implementation of CXL can simultaneously boost the overall DRAM demand while reducing the cost per accessible bit for datacenter architects.

Author Bio:

John Lorenz is a Sr Technology and Market Analyst at Yole Group, a leading analyst firm based in France. At Yole, John covers processors, accelerators, and DRAM, with keen attention to manufacturing topics and applications. He has spoken at many events, including EETimes' AI Everywhere forum and Chiplet Summit. He has also been quoted in many media outlets, including Le Figaro and the Ojo Yoshida Report. Before joining Yole Group, John was a senior manager in strategic finance for Micron Technology, where he analyzed technology investments and forecasted memory industry trends. He earned a BSME from the University of Illinois at Urbana-Champaign.

Jim Handy, General Director, Objective Analysis

Paper Title:

Annual Memory Update: Market Outlook in a Time of Great Change

Paper Abstract:

2024 opened with strong growth, largely fueled by enormous adoption of heavyweight AI systems. What changes does this bring to semiconductor consumption? Is the year’s early growth sustainable? What is the impact of the US/China trade war, high interest rates & inflation, and wars in Ukraine and Israel/Gaza? What changes will come from new technologies like CXL, HBM, and chiplets? In this session respected semiconductor industry analyst Jim Handy of Objective Analysis will show how all of these factors will combine to create a changing market, and will provide attendees with a deep understanding of the aspects that are predictable and those that must be dealt with cautiously.

Author Bio:

Jim Handy, Objective Analysis, is a leading semiconductor analyst. After positions at Intel, National Semi, and Infineon he is respected for his tech depth, accurate forecasts, and numerous reports. See http://Objective-Analysis.com, http://TheMemoryGuy.com, and http://TheSSDguy.com.

Nilesh Shah, VP, Business Development, ZeroPoint Technologies

Paper Title:

Unveiling the dynamics of IP Licensing Economics: Memory & Storage SoC/Chiplets

Paper Abstract:

This panel/presentation explores the complex economic landscape of Intellectual Property (IP) licensing within the semiconductor industry, with a specific focus on Storage and Memory System-on-Chip (SoC) and chiplet development for hyperscale computing. The discussion covers key aspects: 1. **Market Dynamics:** Analysis of evolving trends and demands in hyperscale computing, and their impact on decision-making for IP licensing models. 2. **Leveraging IP Ecosystems:** Exploration of the role of IP ecosystems in supporting SoC and chiplet development, assessing economic viability for collaborative innovation. 3. **Cost-Benefit Analysis:** In-depth examination of economic implications related to various IP licensing structures, including upfront fees, royalties, and revenue-sharing models, considering scale and volume effects. 4. **Risk Management:** Addressing inherent risks in IP licensing, including conflicts, legal considerations, and strategic implications at different development stages. 5. **Technological Advancements:** Assessment of the influence of advanced fabrication processes and AI integration on the economics of IP licensing in SoC and chiplet development.

Author Bio:

Paper Session Description:

This session provides insight into the market outlook amidst great changes in semiconductor consumption due to factors like AI system adoption, trade wars, and new technologies. We will discuss the foreseeable impacts and challenges in the evolving memory landscape. The dynamics of IP licensing economics in memory and storage SoC/chiplets development will be explored in-depth, covering market trends, leveraging IP ecosystems, cost-benefit analysis, risk management, and technological advancements. We will aim to shed light on the complex economic landscape of IP licensing within the semiconductor industry. We will also explore the use of nonlinear optical materials and processes, and the revolution in optical computing. Additionally, the memory market recovery and focus on datacenter and CXL demand will be analyzed, highlighting the rebound of DRAM and NAND markets and the factors contributing to their recovery.

PRO COMP-102-1: CS Solution/Technology Innovations NEW

Ballroom C, Floor 1

Track: Computational Storage

Organizer:

Scott Shadley, Strategic Planner, Solidigm

Scott Shadley has spent over 25 years in the semiconductor and storage space. He has time in Production, Engineering, R&D, Customer focused roles including Marketing and Strategy. His current focus is in efforts to drive adoption of new storage technology as a Director of Strategic Planning at Solidigm. He has been a key figure in promoting SNIA as a second term Board member and leading the computational storage efforts as a co-chair of the SNIA Technical Working Group. He participates in several industry efforts like Open Compute, NVM Express and is seen as a subject matter expert in SSD technology and semiconductor design. He has and still speaks on the subject at events like the Open Compute Summit, Flash Memory Summit, SDC, and many other events, press interviews, blogs, and webinars. While at NGD Systems, Scott developed and managed the Computational Storage products and ecosystem. Scott previously managed the Product Marketing team at Micron, was the Business Line Manager for the SATA SSD portfolio, and was the Principal Technologist for the SSD and emerging memory portfolio. He launched four successful innovative SSDs for Micron and two for STEC, all of which were billion dollar programs. Scott earned a BSEE in Device Physics from Boise State University and an MBA in marketing from University of Phoenix.

Paper Presenters:

Qing Zheng, Scientist, Los Alamos National Laboratory

Nika Mansouri Ghiasi, PhD Student, SAFARI Research Group at ETH Zurich

Paper Title:

Storage-Centric Computing for Genomics and Metagenomics

Paper Abstract:

Genomics and metagenomics have enabled significant advancements in many critical areas. The exponential growth of genomic data poses unprecedented challenges in genomics and metagenomic applications. These applications suffer from significant data movement overheads from the storage system. To fundamentally address these overheads, we make a case for storage-centric computing. First, we propose MetaStore, the first in-storage processing system designed to significantly reduce the data movement overhead of end-to-end metagenomics. MetaStore is enabled by our lightweight and cooperative design that orchestrates processing inside and outside storage. MetaStore outperforms the performance- and accuracy-optimized software baselines by 2.7-37.2Ã and 6.9-100.2Ã, respectively, while matching the accuracy of the accuracy-optimized tool. MetaStore achieves 1.5-5.1Ã speedup compared to the hardware baseline, while achieving significantly higher accuracy. Second, we propose GenStore, the first in-storage processing system designed for genome sequence analysis. GenStore significantly improves the read mapping performance of the software (hardware) baselines by 1.5-33.6Ã (1.5-19.2Ã).

Author Bio:

Nika Mansouri Ghiasi is a PhD student in the SAFARI Research Group at ETH Zurich. During her PhD, she has also been a visiting researcher at Stanford University in the Robust Systems Group. She has worked on near-data processing approaches in the storage and main memory systems, and efficient design of NAND flash-based storage systems and main memory systems to enhance their performance, fairness, energy efficiency, and reliability. She earned her master’s degree in Information Technology and Electrical Engineering from ETH Zurich in 2019, and her bachelor's degree in Electrical Engineering from the University of Tehran in 2016. Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is also a faculty member at Carnegie Mellon University, where he previously held the Strecker Early Career Professorship. His current broader research interests are in computer architecture, systems, hardware security, and bioinformatics. A variety of techniques he, along with his group and collaborators, has invented over the years have influenced industry and have been employed in commercial microprocessors and memory/storage systems. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held various product and research positions at Intel Corporation, Advanced Micro Devices, VMware, and Google. He received the IEEE Computer Society Edward J. McCluskey Technical Achievement Award, the ACM SIGARCH Maurice Wilkes Award, the inaugural IEEE Computer Society Young Computer Architect Award, the inaugural Intel Early Career Faculty Award, US National Science Foundation CAREER Award, Carnegie Mellon University Ladd Research Award, faculty partnership awards from various companies, and a healthy number of best paper or "Top Pick" paper recognitions at various computer systems, architecture, and hardware security venues. He is an ACM Fellow "for contributions to computer architecture research, especially in memory systems", IEEE Fellow for "contributions to computer architecture research and practice", and an elected member of the Academy of Europe (Academia Europaea). His computer architecture and digital logic design course lectures and materials are freely available on YouTube, and his research group makes a wide variety of software and hardware artifacts freely available online. For more information, please see his webpage at https://people.inf.ethz.ch/omutlu/.

Woosuk Chung, Storage Software Team Lead, SK hynix

Paper Title:

Toward Open Standardized Object-Based Computational Storage for Big Data Analyti

Paper Abstract:

Open standards facilitate interoperability, community support, and vendor neutrality. Just as NFS sets the protocol for NAS and ANSI T10 defines SCSI’s Object-based Storage Device (OSD) command set, this talk pushes for standardizing object-based computational storage amid rising object storage use, the increasing bottleneck caused by excessive data movement, a lack of standardized methods for integrating data reduction functions within storage, and a shift towards NVMe as a modern replacement for the old SCSI interface. As a collaborative effort among SK hynix, Los Alamos National Laboratory, Versity, Neuroblade, and Airmettle, we envision a standardized Object-based Computational Storage (OCS) stack as an open computational storage platform for data analytics. This stack comprises a high-level Object-based Computational Storage (OCS) interface for object management and query pushdown and a low-level Object-based Computational Storage Device (OCSD) command set for device-level object storage and query processing. A typical setup would consist of a pool of gateway servers implementing the high-level interface and a pool of NVMe devices or arrays implementing the low-level interface. This talk will focus on the rationale behind such an open storage stack design, its integration with existing storage services, and its current prototype implementation along with early analysis acceleration results using real-world dataset and workflows.

Author Bio:

Woosuk Chung is currently serving as the Storage Team Leader at SK Hynix. He is responsible for leading a team dedicated to the research and development of next-generation storage systems and future enterprise SSDs for enhancing the system performance

Ujjwal Negi, Member Technical Staff, Siemens EDA

Paper Title:

Accelerating Verification of Computational Storage Designs

Paper Abstract:

Computational Storage and Subsystem Local Memory (SLM) command sets leverages low latency, high bandwidth, efficient command handling, and direct CPU access which makes it ideal for computational storage designs. However, these features add various challenges in their functional verification. To ensure thorough verification, validation of command operations from these command sets and data transfers to and from various regions, memory score boarding across power cycles should be included. These challenges require the solution to be agile and adaptable. We will discuss the important characteristics of verification solution from planning to closure. We will see how by using common APIs, different kinds of access to commands, data structures, SLM ranges using UVM features like callbacks and analysis components will make the solution highly adaptable for various types of device-defined or vendor specific programs keeping the high-level stimulus similar. We will see a case study on how the above techniques along with exhaustive compliance test suite, and efficient debug mechanism helped our NVMe customer verify computational storage design thoroughly and achieve lesser time to market.

Author Bio:

Ujjwal is currently working on the development of verification solutions for NVMe and NVMe over Fabrics testing solutions in storage domain focusing on the Computational Storage. Ujjwal holds a Bachelor of Technology in Electronics and Communication from Guru Govind Singh Indraprastha University in 2023.

Paper Session Description:

In this session, we dive into the world of object-based computational storage for data analytics, which is revolutionizing the way data analytics systems process and transfer data. Verification of computational storage designs, crucial for ensuring the functionality and reliability of computational storage systems, uses APIs, UVM features, and efficient testing techniques to reduce time to market. Lastly, storage-centric computing for genomics and metagenomics is reshaping the field by addressing data movement overheads and improving performance in genomic applications with innovative in-storage processing system. Let's continue pushing the boundaries of computational storage for a brighter future in data analytics and genomics.

PRO CXLT-102-1: CXL Fabric Management

Ballroom E, Floor 1

Track: CXL

Organizer + Chairperson:

Anil Godbole, Xeon CXL Strategy & Marketing Manager at Intel Corporation, Intel

Anil is Xeon CXL Strategy & Marketing Manager at Intel Corporation.

Paper Presenters:

Bhushan Chitlur, Sr Principal Engineer, Datacenter & AI Group, Intel

Paper Title:

Improving SW-HW processing pipeline for storage stack/service workflows w CXL

Paper Abstract:

Storage services & workflows are adopting disaggregated storage architecture enabled by newer ethernet standards: 400/800GE. This also necessitates need for HW accelerators for operations like compression, encryption, erasure coding, deduplication etc with some usages requiring operations at storage initiator. These operations require data context to be translated from memory into storage context right at the Storage initiator (typically, CPU) before transmission over 400/800GE to the destination media block/object/file storage. The storage stack thus is a blend of protocol processing & multiple translations enforcing data segmentation using SW-based execution or through accelerator usage (e.g., TLS encrypt / decrypt, NVMe data digest, etc.). Almost always, requires multiple data movement between cpu memory domain and lookaside accelerator memory domains with PCIe link becoming the bottleneck. This paper proposes a CXL based implementation to preserve memory context of data as long as possible, chaining storage and network functions to deliver higher performance for both local & disaggregated storage accesses: block, object, file across varied storage media: volatile, ephemeral, non-volatile. The solution will enumerate CXL concepts to enhance current IO paths and show how adopting CXL dataflow (Type1 / Type2 / Type3) allows for data plane in only one memory domain with control plane straddling between cpu and accelerator memory domains. This delivers higher throughput, more IOPs per node & also reduces deployment cost by enabling solution upgrades requiring slower hardware refresh cadence.

Author Bio:

Bhushan Chitlur is a Sr Principal Engineer, Datacenter & AI Group at Intel Corporation

Grant Mackey, CTO, Jackrabbit Labs

Paper Title:

You Don't Know 'Jack': CXL Fabric Orchestration and Management Best Practices

Paper Abstract:

The CXL consortium has published a fabric management API in their latest specification which codifies how switches and devices should pass information to each other in a standardized way for configuration and management. However this API is just a set of commands, not a framework for accomplishing tasks at a system or infrastructure configuration level. To date, the CXL community, both creators and consumers, have not discussed how fabric orchestration should function for CXL. Jackrabbit Labs has written a CXL FM API compliant set of open source tools which function as a fabric management and orchestration layer for CXL devices and switches. In this presentation we introduce 'Jack,' and talk about best practices for integrating CXL fabrics into familiar platform management tools. Further, we'll demonstrate how CXL fabrics and orchestration integrate into a Kubernetes deployment.

Author Bio:

Grant Mackey, Distinguished engineer focused on datacenter enablement. Inventor/researcher of storage and HPC systems for Western Digital and Los Alamos National Labs. A published author and patent holder with nearly two decades of experience in research and development of datacenter architectures, workloads, infrastructure, and emerging technologies.

Sudhir Balasubramanian, Sr Staff Solution Architect - Oracle, VMware by Broadcom

Paper Title:

VMware Memory Vision for Real World Applications

Paper Abstract:

VMware has been on an evolving journey on memory innovations mainly first with persistent memory, then with memory tiering, and is now extending that with CXL. CXL provides an opportunity for VMware (by Broadcom) to further improve on performance, and provide further customer benefits such as TCO reduction, server consolidation, and even disaggregation, with increased capacity and bandwidth to run workloads like Mission critical databases, AI/ML and analytics. Use of accelerators increases the number of use-cases that can be supported with a larger variety of workloads with minimum configuration changes. This session aims to provide real-world application examples using memory tiering.

Author Bio:

27 + years Oracle hands on experience - Principal Oracle DBA / Architect, Oracle RAC/Data Guard Expert, Experienced in EMC SAN Technologies Principal Oracle DBA/Oracle Architect [1995 – 2011] Senior Staff Solution Architect & Global Oracle Practice Lead [2012-] - VMware / VMware by Broadcom VMware VCA – Cloud ,VMware vBCA Specialist, VMware vExpert Member of the Office of the Chief Technical Ambassador VMware (Alumni) Oracle ACE Leading Author - “Virtualizing Oracle Business Critical Databases on VMware SDDC” Recognized Speaker@ VMware Explore, Oracle Cloud World, Oracle User Groups, Quest IOUG, Dell EMC World, SNIA and Webinars Industry recognized expert in Oracle Virtualization technologies Blogs http://vracdba.com/ https://blogs.vmware.com/apps/author/sudhirbalasubramanian/ Twitter : @vracdba LinkedIn : https://www.linkedin.com/in/sudhirbalasubramanian/

Navneet Rao, Engineer, Intel

Navneet Rao is a Solutions Architect at Intel Corporation

Yong Tian, Field CTO, MemVerge

Paper Title:

The Case for CXL Memory Expansion

Paper Abstract:

With support for CXL 1.1, servers now offer a new architectural model with the capability for memory expansion through CXL Memory Add-in Cards (AICs) and E3.S memory modules. This presentation addresses the critical considerations faced by sellers and buyers regarding the cost, capacity, and performance implications of integrating mixed DIMM and CXL memory in their server environments. Yong Tian will guide the audience through an insightful exploration of the innovative memory expansion architecture options presented by CXL and its 1.1 specifications. An in-depth analysis will be presented, unveiling strategies to slash memory costs by half while concurrently elevating a single server's capacity to an impressive 32TB. The focal point of the presentation will be test results illustrating how servers equipped with mixed memory can sustain optimal application performance. This will be achieved through the utilization of automated tiering software, driven by fine-grained latency and bandwidth policies. Attendees will gain valuable insights into the nuanced dynamics of mixed memory configurations, understanding when and how servers can seamlessly adapt to varying workloads.

Author Bio:

Yong Tian is VP of Products for MemVerge. He heads the product strategy for the company’s Memory Machine software. Previously Yong was Co-Founder and COO of UltraSee Corp, a pioneer in software-defined ultrasound imaging. He holds a Master of Management from Stanford Graduate School of Business, Masters of Electrical Engineering from the University of Illinois, and B.E. in Electrical Engineering from the Cooper Union.

Paper Session Description:

This session discusses how memory innovations are leveraging technologies like persistent memory, memory tiering, and the latest addition of CXL. Open source fabric management and orchestration layers for CXL devices and switches can offer best practices for seamless integration with familiar platform management tools. Additionally, with CXL 1.1, servers now supporting memory expansion through CXL Memory Add-in Cards and E3.S memory modules, sellers and buyers can now integrate cost-effective and high-capacity solutions. Attendees will gain valuable insights into the benefits and strategies of incorporating mixed memory configurations in server environments, ultimately optimizing application performance.

PRO DCTR-102-1 Hyperscale Applications Part 1

Ballroom D, Floor 1

Track: Data Center Applications

Organizer:

Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft

Jonathan Hinkle is Senior Director - Azure Memory and Storage Pathfinding at Microsoft. He previously was In Micron's Storage Business Unit, where he investigated new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.

Paper Presenters:

Vineet Parekh, Hardware Systems Engineer, Meta

Paper Title:

SSDs in Meta Datacenters

Paper Abstract:

In this presentation we will cover how flash is used in the Meta datacenter fleet. What are the challenges we observe in designing and sustaining storage in fleet. At end we will talk about how the ecosystem is changing for storage and how is Meta contributing here.

Author Bio:

Vineet Parekh has been working in the hyperscale industry for more than a decade. He is a Hardware Engineer at Meta where he is responsible for design, testing and reliability of the Meta server fleet.

Lee Prewitt, Principal Hardware Program Manager, Microsoft

Lee Prewitt is a Principal Hardware Program Manager with 25 years of storage industry experience ranging from Magneto-Optical to spinning rust to Flash. His former work at Microsoft has included working in the Windows and Devices Group where he was responsible for many of the components in the storage stack including File Systems, Spaces, Storport and Microsoft’s inbox miniport drivers. His responsibilities included storage devices ranging from SD and UFS in mobile to NVMe in Enterprise and Data Centers. He currently works in the Azure CSI team where he is responsible for future Data Center storage initiatives, specifications and evangelization.

Bill Gervasi, Principal Systems Architect, Wolley Inc

Paper Title:

NVMe Over CXL: How CXL Lets Us Do Controller Memory Buffers the Right Way

Paper Abstract:

NVMe has supported controller memory buffers since version 1.2 of the specification, however CMB performance advantages were limited by the PCIe bus itself which does not support a lightweight memory protocol. CXL fixes this fundamental limitation of CMBs by allowing efficient memory accesses with the CXL.mem protocol over that same PCIe physical interface while the CXL.io protocol supports all the legacy functionality of NVMe without requiring applications to be rewritten. Race conditions in resource allocation are resolved by having storage and memory on the same device. Advantages of SSDs using NVMe Over CXL are detailed and compared to memory semantic SSDs. The merging of storage and memory has another side benefit: DRAM persistence ala NVDIMM-N.

Author Bio:

Mr. Gervasi has over 45 years of experience in high speed memory subsystem definition, design, and product development. Career highlights include 19 years at Intel where he was systems hardware designer, software designer, and strategic accounts manager. Mr. Gervasi became a memory specialist for companies including S3, Transmeta, Netlist, SimpleTech, and Nantero, and is now Principal Systems Architect for Wolley, developing CXL based memory solutions. Mr. Gervasi been involved in the definition of Double Data Rate SDRAM since its earliest inception. He has served on the JEDEC Board of Directors and chaired committees for DRAM parametrics and memory modules during the development of DDR1 through DDR6. He is currently the chairman of the JEDEC Alternative Memory committee. He received the JEDEC Technical Excellence award, their highest honor, in 2020.

Ross Stenfort, Hardware Systems Engineer, Storage, Meta

Paper Title:

Storage Industry Update

Paper Abstract:

Ross Stenfort (Meta) and Lee Prewitt (MSFT) will provide an update on the storage from a hyperscale perspective.

Author Bio:

Ross Stenfort is a Hardware System Engineer at Meta delivering scalable storage solutions. He has been involved in the development of storage systems, SSDs, ROCs, HBAs and HDDs with many successful products and over 40 patents.

Paper Session Description:

This session will share the latest updates on storage from a hyperscale perspective in the storage industry. We will delve into the use of SSDs in Meta datacenters, exploring the challenges faced in designing and maintaining storage in the Meta fleet. We’ll also shed light on the changing landscape of the storage ecosystem and Meta's role in shaping it. Additionally, the discussion on Flexible Data Placement (FDP) in the real world will highlight the advantages of FDP at scale, offering insights into its practical applications and benefits.

Open SPOS-102-1: SNIA: Data and Storage Standards to Accelerate Implementations NEW

Ballroom A, Floor 1

Track: Sponsored Sessions

Sponsor:

SNIA

Organizer + Chairperson:

Bill Martin, Principal Engineer SSD I/O Standards, Samsung Electronics

Bill has been involved in the storage industry for over 30 years, starting in 1983 with the development of a proprietary optical storage interface for HP, architecting the HP Tachyon interface chip for Fibre Channel, serving on industry consortiums and standards bodies for storage including SNIA, INCITS T11, INCITS T10, INCITS T13, SATA-IO, and NVMe. He currently represents Samsung SSD technologies in the standards community as co-chair SNIA technical council, Vice Chair INCITS T10, Board member NVMe board, Secretary INCITS T13, Co-Chair SNIA Object Drive TWG, and active contributor to the technical work of these organizations.

Paper Presenters:

Anthony Constantine, SFF Co-Chair and SNIA Technical Council, SNIA

Paper Title:

SFF: Connecting Everything Together

Paper Abstract:

SNIA's SFF group is prolific, putting out hundreds of specifications. But what do they do, and who is involved? The SFF specifications for connectors, transceivers, and form factors are used pervasively throughout the computer industry, providing standardized interconnects for systems, devices, and fabrics. Learn about the broad-reaching scope of current and future work the SFF is undertaking.

Author Bio:

Anthony Constantine is the author for several EDSFF specifications and contributes to other SFF TA specifications within SNIA. He also serves as co-chair for the SFF TA. In addition, Anthony contributes to PCI-SIG, JEDEC, Open Compute Platform (OCP), and the Open NAND Flash Interface (ONFI). Anthony has over 23 years of experience in the technology industry with an expertise in memory, storage, physical interfaces, low power technologies, and form factors. He earned a BS in Electrical Engineering from UC Davis.

Richelle Ahlvers, Storage Technology Enablement Architect, Intel

Paper Title:

Manageability

Paper Abstract:

SNIA has been the source for storage management standards for over 20 years, and continues to lead with standards-based management interfaces for key use cases and configurations, from enterprise, to NVMe, to cloud, enabling infrastructure for applications from traditional to bleeding edge. Learn how SNIA works with partners to rapidly adapt manageability strategies for standards with technologies like SNIA Swordfish(tm).

Author Bio:

Richelle Ahlvers is a Storage Technology Enablement Architect at Intel, where she promotes and drives enablement of new technologies and standards strategies. Richelle has spent over 25 years in Enterprise Storage R&D teams in a variety of technical roles, enabling new technology ecosystems, leading the architecture, design and development of storage array software, storage management software user experience projects including mobility, developing new storage industry categories including SAN management, storage grid and cloud, and storage technology portfolio solutions. Richelle has been engaged with industry standards initiatives with SNIA and DMTF for many years. She serves on the SNIA Board of Directors, the Chair of the Storage Management Initiative, and has led the SSM Technical Work Group developing the Swordfish Scalable Storage Management API from the group’s inception; she is the alliance liaison between SNIA and DMTF, as well as the alliance liaison for OFA, OCP, and the SODA Foundation. She has also served as the SNIA Technical Council Chair and been engaged across a breadth of technologies ranging from storage management, to solid state storage, cloud, and green storage. Richelle has also initiated and led both site and corporate level women's diversity forums, and presents regularly at diversity conferences

Shyam Iyer, Distinguished Engineer, Dell

Paper Title:

Accelerators: SDXI, DPUs, and Storage

Paper Abstract:

Shyam Iyer, Chair of the SNIA Smart Data Accelerator Interface (SDXI) Technical Work Group, provides an update on this SNIA standard for a memory-to-memory data movement and acceleration interface

Author Bio:

Shyam Iyer is a Distinguished Engineer in Dell's Chief Technology and Innovation Office experienced in Researching, Designing, Developing, Debugging, Validating, Leading, and Driving System and Software solutions that have an industry-wide impact. With 50+ granted patents and several patent pending applications, Shyam has wide experience with Kernel, Device Drivers, Operating Systems, Virtualization, FPGA/Hardware device definitions, system architecture, performance tuning, Simulation, characterization, Storage Networking protocol stacks, OS/BIOS interfaces, Systems management, CPU micro-architecture, security architectures, etc. He works on a variety of forward-looking concepts and strategies in Dell’s technical leadership community. He regularly presents/reviews solutions internally and externally with C-level execs, customers, and developer-oriented audiences. Shyam writes code/reviews them for relief and enjoys a healthy smattering of technical and business-oriented discussions. Among his SNIA activities, Shyam is the Chair for SDXI (Smart Data Accelerator Interface), a SNIA Technical Working Group(TWG) that aims to develop, extend, and drive an extensible, virtualizable, forward-compatible, memory to memory data movement and acceleration interface standard. He is the co-chair for the SDXI + Computational Storage Subgroup that envisions SDXI devices in a Computational Storage architecture and works to propose Computational Storage features to the SDXI standard. Shyam was recognized with the “Excellence in Leadership” award by SNIA membership in 2022. Under his leadership, SDXI TWG won the “SNIA TWG of the Year” award in 2021 and the “Most Innovative Memory Technology” award at Flash Memory Summit(FMS) 2023 for SDXI specification v1.0.

Paper Session Description:

SNIA develops standards across a wide range of data and storage technologies today. This session will provide a brief overview of the organization’s scope, and dive into three of SNIA’s key standards that affect the future of memory and storage. SNIA has led the development of standards-based management standards and conformance programs for over 20 years. Get an update on the latest work from SNIA and its alliance partners to provide integrated manageability standards across technologies. SNIA’s SFF specifications provide the necessary connectors and form factors to deliver interoperable systems. Recent demand for offload-based data processing is driving increased demand for accelerators, and in turn, for standardization of accelerator usage

PRO SSDT-102-1: SSD Technologies for Compute Use Cases

Ballroom F, Floor 1

Track: SSD Technology

Organizer:

Erich Haratsch, Senior Director Architecture, Marvell

Erich Haratsch is Senior Director Architecture at Marvell, where he leads the architecture definition for Bravera™ SSD controllers and other memory-based products. Prior to joining Marvell, he worked at Seagate and LSI, where he worked on Nytro® and SandForce® branded SSD controllers. Earlier in his career, he developed signal processing and error correction technologies for multiple generations of HDD controllers at LSI and Agere Systems. He started his career at AT&T and Lucent Bell Labs, where he worked on Gigabit Ethernet over copper, optical communications and the MPEG-4 video standard. He is the author of over 40 peer-reviewed journal and conference papers, and holds more than 200 U.S. patents. He also is a Senior Member of IEEE, and earned his MS and PhD degrees from the Technical University of Munich (Germany).

Paper Presenters:

Trent Johnson, SSD Hardware Architect, IBM

Paper Title:

FlashCore Module (FCM): Meet the Engine Behind IBM's Flash Systems

Paper Abstract:

The 4th generation IBM FlashCore Module delivers enterprise level storage to clients using inexpensive QLC flash memory technology. It offers many optimizations through its computational storage architecture. How do we do it? We will go through some of the hardware implementation details and features to demonstrate how FlashCore Modules can save money on capacity, and power as well as improve RAID performance and keep data safe from ransomware attacks.

Author Bio:

Trent Johnson is a Hardware Architect at IBM, with a focus on the IBM FlashCore Module. He joined IBM as part of the Cleversafe Acquisition where he was also the System Hardware Architect of exabyte-scale object storage. Prior to Cleversafe, he developed system-level manufacturing and test solutions for AMD CPUs and GPUs where he was awarded the AMD Corporate Technical Achievement Award. He has 24 years of industry experience, holds 7 US patents and has published at the Burn-in and Test Socket Workshop as well as the Conference for Consumer Electronics. He earned BSEE and MSEE degrees from The University of Texas at Austin in Electrical Engineering with a focus on Manufacturing System Engineering.

Nick Snow, Product Manager, Enterprise SSDs, KIOXIA America, Inc

Paper Title:

PCIe 6.0 SSDs: Powering the Future of Compute and Storage.

Paper Abstract:

In January 2022, the PCIe 6.0 specification was officially ratified. Among many new features, most notable is it’s doubling of performance compared to the PCIe 5.0 specification to an incredible 128GB/s for an x16 link. With this new massive speed comes new considerations for NVMe solid state drives. As performance and power requirements increase, we will discuss what form factors are best to take advantage of PCIe 6.0. We will also consider signal integrity, thermal constraints, and other aspects that need to be at the forefront of any new PCIe 6.0 NVMe SSD designs.

Author Bio:

Nick Snow has held device and system design engineer and product line manager positions within in the data storage industry for over 10 years.

Nikhil Garg, Senior Engineer, Micron Technology

Paper Title:

Knowledge Aware SSDs Rebuilding Failed RAID Drive

Paper Abstract:

Data redundancy is a crucial aspect of RAID because it enhances fault tolerance, reducing the risk of data loss due to drive failures. Failed RAID drives need to copy significant amount of data without using parity computation. This reduces the host system’s overall performance, by utilizing host CPU and memory resources to send read and write operations and stage the data in host memory. The proposed solution involves a novel method of leveraging the failed NVMe drive firmware using CMB (Controller Memory Buffer) to offload the host system resources (Space and Input/Output Bandwidth) being used to rebuild the good data. CMB buffer can be used to stage good data to be copied to spare drive. This helps offload the host memory resources which can be used for other system operations. Failed drive FW can be leveraged to be knowledge aware about host data structures, thus assisting in drive rebuild without using host I/O bandwidth. Thus, saving the entire host space and IO bandwidth being used in rebuilding of good data. This improves overall system performance, allowing for more concurrent tasks.

Author Bio:

Nikhil Garg has a Bachelor of Technology in Electrical and Electronics Engineering (2018) from Delhi Technological University (Delhi College of Engineering), Delhi, India. He joined Firmware Engineering in Flash Products ESSD Group at Western Digital in 2018 and subsequently joined Micron Technology Inc. in 2021. Over the years, he has led NVMe-SSDs and MNAND products. His work is primarily focused on NVMe Streams, ZNS, CMB, DST, QLC Program and Read sequences implementation, along with strong knowledge of Front End, Flash Translation Layer, and Back End features development, giving him a deep understanding of storage controller architecture. Nikhil Garg is a Senior Firmware Engineer at Micron and has authored 3 approved SSTS papers in Micron, and 1 approved technical paper in Western Digital.

Devesh Rai, Sr. Staff Strategic Marketing Manager, KIOXIA America, Inc

Paper Title:

Review of RAID Offload Concept and Its Adoptability in Different Applications.

Paper Abstract:

Data redundancy solutions by nature are compute intensive and pose challenges on system resources. NVMe SSDs equipped with RAID offload technology can be used in reducing RAID application usages of compute, DRAM usages and cache thrashing. KIOXIA proposes a scale out RAID offload technology can be adopted in following areas; attaining sustainability goals in data scrubbing; reducing network traffic in RAID volumes spread across multiple canisters; rebuilding data on drives within RAID setups; data center applications like VMWare’s VSAN 8.0; mixed drive setups like high performance computing nodes; and conventional hardware and software RAID applications.

Author Bio:

Devesh Rai has held senior software engineer positions over the past 20 years. Devesh’s extensive experience includes designing and developing host I/O stack, distributed file system, DRaaS, and firmware for NVMe SSDs.

Chandra Nelogal, Distinguished Member of Technical Staff, Trusted Computing Group

Paper Title:

Review of RAID Offload Concept and Its Adoptability in Different Applications.

Paper Abstract:

Author Bio:

Chandra Nelogal is an Engineering Technologist working in the area of data storage and security in the Dell’s Infrastructure Solutions Group. Chandra represents Dell in the Trusted Computing group, co-chairing the Storage Work group. Chandra also contributes to the DICE work group in TCG as well as to other work groups in other Industry standards organizations that focus on platform infrastructure (DMTF PMCI) and security (DMTF SPDM). Chandra is a prolific inventor with 70 granted patents from USPTO. Chandra has a B.S. in Computer Science from Bangalore University in India, and an M.S. in Engineering from the University of Texas at Austin in the US. Chandra has presented on security topics at conferences such as SNIA SDC, SNIA Security Summit and Flash Memory Summit.

Paper Session Description:

In this session, we look at SSD technologies for compute use cases. PCIe 6.0 SSDs are revolutionizing the future of compute and storage with their incredible speed and performance, doubling that of the previous generation. As NVMe solid state drives continue to evolve, new considerations such as signal integrity and thermal constraints must be taken into account to fully leverage the power of PCIe 6.0. RAID offload technology offers a promising solution to reduce compute and DRAM usage in data redundancy applications, making it adaptable in various areas such as data scrubbing, network traffic reduction, and data center applications. The FlashCore Module from IBM is the engine behind their Flash Systems, providing enterprise-level storage with cost-saving features and improved performance. Knowledge Aware SSDs are introducing a novel method to rebuild failed RAID drives, leveraging firmware to offload host system resources and optimize overall system performance.

PRO UCIC-102-1: UCIe Technology Opportunities & Benefits NEW

Ballroom G, Floor 1

Track: UCIe and Chiplets

Organizer:

Brian Rea, Technology Initiative and Ecosystem Enablement Manager, Intel

Paper Presenters:

Mayank Bhatnagar, Product Marketing Director, Cadence Design Systems

Paper Title:

How UCIe Reduces the Barrier to Entry in Chiplet Design

Paper Abstract:

The design of systems-in-package (SIP) or System-on-chip is a process with an excessive cost in terms of resources and time. However, there are designers with differentiated ideas big enough for chiplets, and users that want to buy these prefabricated chiplets to reduce their time and design costs. A widely adopted open standard such as UCIe enables that, without which all chiplets must be designed and consumed internally. We discuss the possibilities that UCIe technology opens by reducing the barrier to entry for boutique chiplet designers. We also present illustrative examples of how it helps chiplet users by fostering innovation and competition by enabling a chiplet marketplace.

Author Bio:

Mayank Bhatnagar is a product marketing director with Cadence Design Systems, where he focuses on die-to-die interface IP, including UCIe. His goal is to align Cadence's IP strategy to the overall market direction and enable IP solution tuned to customer needs. Prior to this, he has worked on fabrication technology, device design, foundational IP, SOC and block level digital implementation,and interface IPs such as DDR, LPDDR, HBM, AIB, HBI, and UCIe. He holds a master's degree in electrical engineering, and a master's degree in business administration.

Paper Session Description:

UCIe (Universal Chiplet Interconnect Express) is revolutionizing the field of SoC construction by providing an open industry standard that allows for more customizable package-level integration. Founded by key players in the semiconductor industry, UCIe 1.1 Specification was introduced at FMS 2023, bringing significant improvements to the chiplet ecosystem. This session will highlight the enhancements made in the UCIe 1.1 specification, as well as how it simplifies system setups and compliance testing for device interoperability. By reducing the barrier to entry for boutique chiplet designers and enabling a "chiplet marketplace," UCIe is paving the way for a more innovative and competitive future in chiplet design.

10:50 AM to 11:00 AM

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Open Chairman's Welcome

Mission City Ballroom, Floor 1

Track: FMS 2024 Special Sessions

Organizer + Moderator:

Charles Sobey, Chief Scientist, ChannelScience

Chuck Sobey is Conference Chair of FMS. Under his leadership, FMS has increased its size, scope, and influence worldwide, while navigating the unprecedented effects the pandemic has had on the global events industry. Chuck is a respected memory and storage technology strategist, researcher, and lecturer. As Chief Scientist of ChannelScience, he guides clients in evaluating emerging memory and storage technologies and in maximizing their reliability and performance. He uses probability analysis to match a technology's projected capabilities to an application's requirements. His team has won SBIR awards from the US Department of Energy to advance the field of magnetic tape recording, on which practically all of the hyperscale and cloud services rely. Chuck's clarity of explanation and extensive experience and industry network make him a sought-after technical and business development consultant. He has taught storage/memory technology seminars around the world. Chuck is also General Chair of SmartNICs Summit, which he is co-developing to support the hyperscale and cloud data center ecosystem. He earned an MS ECE from the University of California, Santa Barbara and a BS ECE from Carnegie Mellon University. He holds 7 US patents.

Special Presentation Description:

FMS Conference Chair Chuck Sobey welcomes all to FMS24 - the Future of Memory and Storage, and provides an overview of the three day event.

11:00 AM to 11:30 AM

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Open Keynote 1: KIOXIA: Memory Innovations Fueling the New Currency of Our Digital World

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Sponsor:

KIOXIA

Keynote Speakers:

Atsushi Inoue, VP and Technology Executive, KIOXIA

Mr. Atsushi Inoue is seasoned Vice President and Technology Executive in the Memory Division at KIOXIA Corporation. With over 30 years of experience in the flash memory industry, he plays a crucial role in product planning, technical marketing, and customer support for the latest 3D flash memory BiCS FLASH™. His responsibilities also include application engineering and development support for NAND components and applications. In his recent activities, one remarkable accomplishment is the launch of BiCS FLASH™ generation 8, which utilizes a groundbreaking technology of bonding the CMOS wafer and Cell Array wafer together, aiming for further capacity and density enhancement of flash memory. Mr. Inoue graduated from the Department of Materials Science and Engineering, Faculty of Science and Engineering, Waseda University in 1993. In the same year, he joined Toshiba, contributing to the evaluation of early-stage 4Mbit and 32Mbit NAND flash memory in the Memory Evaluation Engineering Department. In 1999, he moved to Toshiba America Electronic Components, where he supported the initial expansion of NAND technology. Upon returning to Japan in 2003, he worked in the Memory Evaluation Engineering Department, focusing on new technologies such as 70nm QLC and 56nm TLC. From 2009, he worked in the Memory Application Engineering Department, where he was involved in planning NAND products for the enterprise and data center markets. Subsequently, he served as Senior Director in the Memory Technical Marketing Managing Department before assuming his current position. Mr. Inoue is currently based at the KIOXIA Corporation headquarters in Tamachi, Tokyo, Japan.

Neville Ichhaporia, Sr. VP & General Manager, KIOXIA America, Inc

Mr. Ichhaporia holds the position of Senior Vice President and General Manager of the SSD Business Unit at KIOXIA America, Inc. In this role, he is responsible for the company’s marketing, business management, product planning, and engineering teams, overseeing the SSD product portfolio aimed at cloud, data-center, enterprise, and client computing market segments. Neville has over 20 years of extensive industry experience across a variety of responsibilities and disciplines, including product management, strategic marketing, new product development, hardware engineering, and R&D. Prior to joining KIOXIA in 2016, Neville held diverse roles in business, product management, and engineering development at Toshiba Memory America, SanDisk, Western Digital Corporation, and Microchip. Mr. Ichhaporia holds an MBA from the Santa Clara University Leavey School of Business, an MS in Electrical Engineering and VLSI Design from the University of Ohio, Toledo, and a BS in Instrumentation and Control Systems from the University of Mumbai. He is based at KIOXIA America’s headquarters in San Jose, CA.

Keynote Description:

With continued pursuit of innovation for more than 35 years, NAND flash memory has become an indispensable technology to capture data – the “new currency” of our digital world – fueling emerging paradigms in the world of AI, Cloud, and Edge Computing. Looking toward the future, KIOXIA’s BiCS FLASH™ 3D generations will continue to scale, enabling higher density and performance along with cost and power improvements. KIOXIA will lead the way and present cutting edge memory and SSD technologies, as well as highlight advanced developments to address the memory and storage needs for next-generation applications with innovations and optimizations rooted in flash-memory based technologies and approaches. No matter what your application, get there with KIOXIA.

11:30 AM to 11:40 AM

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Open 2024 Lifetime Achievement Award

Mission City Ballroom, Floor 1

Track: FMS 2024 Special Sessions

Organizer + Moderator:

Brian Berg, President, Berg Software Design

Organizer + Moderator:

Jim Handy, General Director, Objective Analysis

Jim Handy is President of Objective Analysis, a strategic marketing and market research firm for the semiconductor industry. He has over 30 years of electronic industry experience, including 14 years as an industry analyst with Dataquest and Semico Research. A frequent presenter at trade shows, Mr. Handy has also written hundreds of articles and is frequently interviewed and quoted in the electronics trade press and other media. Mr. Handy writes the Chip Talk blog for Forbes online and contributes to two Objective Analysis blogs: The SSD Guy and The Memory Guy. He is the author of “The Cache Memory Book” and a patent holder in cache memory design. He holds a BSEE from Georgia Tech and an MBA from the University of Phoenix.

Special Presentation Description:

The FMS Lifetime Achievement Award recognizes individuals who have shown outstanding leadership in promoting the development and use of memory, storage, and/or associated or related technologies, including one or more of the following: - Creating or promoting an important memory or storage technology, or a related technology, - Leadership of a major memory or storage company, business effort, or academic program, - Bringing memory or storage technology to a new and important application Lifetime Achievement Award winners may be for a single person, or for a small team or group of individuals with an important connection. By bestowing this award, FMS hopes to help foster further advances in the memory and storage industries.

11:40 AM to 11:45 AM

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Open 2024 Special Award

Mission City Ballroom, Floor 1

Track: FMS 2024 Special Sessions

Special Presentation Description:

Description Not Available

11:45 AM to 12:15 AM

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Open Keynote 2: NEO Semiconductor

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Sponsor:

NEO Semiconductor

Keynote Speakers:

Andy Hsu, CEO, NEO Semiconductor

Andy Hsu is the Founder and CEO of NEO Semiconductor, a company focused on the development of innovative architectures for NAND flash and DRAM memory. Andy is responsible for the overall company strategy, execution, and technology innovation that fuels the company's growth. He has more than 25 years of experience in the semiconductor industry including positions as VP of Engineering and leader of R&D and Engineering Teams. This resulted in the development of more than 60 products in various non-volatile memories. Andy is an accomplished technology visionary and inventor of more than 120 granted U.S. patents. He performed research in the fields of Neural Networks and Artificial Intelligence (AI) while earning a master's degree in Electrical, Computer, and System Engineering (ECSE) from Rensselaer Polytechnic Institute (RPI) in New York. He earned a bachelor's degree from the National Cheng-Kung University in Taiwan.

Keynote Description:

The demand to accelerate artificial intelligence applications (AI apps) continues growing, especially for emerging workloads involving artificial neural networks like generative AI. Current AI Chips simulate neural networks for AI apps using a processor (GPU), memory (HBM), and software, but architectural inefficiencies waste significant amounts of performance and power. Next-generation AI Chips will use totally new AI Chip technology to perform neural network operations inside 3D DRAM, enabling 100x higher performance and 99% lower power consumption. New 3D architectures have the potential to enable the next wave of AI applications with more innovative memory and storage solutions.

01:00 PM to 01:30 PM

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Open Keynote 3: SK hynix: AI Memory & Storage Solution Leadership and Vision for AI Era

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Sponsor:

SK hynix

Keynote Speakers:

Unoh Kwon, VP, Head of HBM PI, SK hynix

Unoh Kwon is vice president of the HBM process integration group at SK hynix, leading the development and enablement of next generation HBM process technologies. Unoh Kwon has also served as fellow in various technology and product development roles in DRAM development group. Prior to joining SK hynix, he managed product integration group at GlobalFoundries and held logic technology process integration positions at IBM. Unoh Kwon holds Ph.D degree in materials science and engineering from Stanford University.

Chunsung Kim, Head of WW SSD PMO, SK hynix

Chunsung Kim, head of WW SSD PMO, is leading SK hynix world-wide SSD Program Management Office and also leading world-wide SSD SoC development efforts for both SK hynix and Solidigm. A 15-year veteran of S.LSI development, Chunsung started and built-up SK hynix in-house NAND Flash controller teams and capabilities. He also contributed in stabilizing SK hynix WW RnD operation & management and now is participating in managing Solidigm as part of management staff. With balanced knowledge and expertise of SSD engineering and business, he is playing a key role in oversea SSD RnD management and collaboration with Solidigm. Chunsung Kim earned his Master degree of Control and Instrumentation engineering from Chung And University in South Korea.

Keynote Description:

Generative AI, which is currently a hot topic, is evolving into GPT4, multilingual reasoning, and coding capabilities, and is expected to ultimately bring about transformations such as the "Industrial Revolution." SK hynix AI memory plays a pivotal role in AI chips, which is the core background of Generative AI, by providing differentiated values in the AI era. With the rise of Generative AI, customer pain-points are becoming more specific such as ① To maximize the learning/inferencing amount per hour; ② To minimize power consumption for learning/inferencing; ③ To minimize floor space and power utilization for storing data, which is increased for Gen AI use. As memory & storage plays a pivotal role in AI technology, SK hynix is committed to continuous innovation and technological breakthroughs to solve customer pain-points in AI memory & storage development and aims to contribute to the advancement of the ICT industry by providing world-best AI memory products and strengthening collaboration with global partners.

01:30 PM to 02:00 PM

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Open Keynote 4: Samsung: The AI Revolution: Fueling New Demands for Memory and Storage

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Sponsor:

Samsung Semiconductor

Keynote Speakers:

Taeksang Song, Vice President, Samsung Seminconductor Inc

Taeksang serves as Corporate Vice President at Samsung Electronics, where he leads a team dedicated to advancing cutting-edge technologies, including CXL memory expanders, fabric-attached memory solutions, and processing near memory to meet the demands of next-generation data-centric AI architectures. With nearly two decades of expertise in memory and sub-system architecture, interconnect protocols, system-on-chip design, and collaboration with cloud service providers to enable heterogeneous computing infrastructures, Taeksang is a recognized leader in the field. Prior to joining Samsung, he held leading architect positions at Rambus Inc., SK Hynix, and Micron Technology, focusing on emerging memory controllers and systems. Taeksang earned his Ph.D. from KAIST in South Korea in 2006. Dr. Song has authored and co-authored over 20 technical papers and holds more than 50 U.S. patents.

Hwaseok Oh, EVP of Solution Product Engineering, Samsung Seminconductor Inc

Hwaseok Oh leads the Solution Product Engineering team at Samsung, where he oversees the commercialization of flash storage products that include mobile memory devices like eMMC and UFS, as well as client-, server-, and enterprise-class SSDs. Hwaseok joined Samsung Electronics in 1997 as a SoC design engineer, focusing on the development of network and storage controllers. While working on flash storage products, he pioneered the world’s first UFS products. He also spearheaded the creation of high-performance NVMe SSD controllers for datacenters. More recently, he has been at the forefront of developing new flash storage technologies, contributing to innovations such as Samsung’s SmartSSD and Flash Memory-based CXL Memory Module. Hwaseok holds a Bachelor’s and a Master’s degree in Computer Science from Sogang University, earned in 1995 and 1997, respectively.

Jim Elliott, , Samsung Electronics

Jim Elliott serves as Corporate Executive Vice President of Memory Sales at Samsung Semiconductor, Inc., responsible for a multi-billion-dollar revenue organization that spans Samsung’s entire memory portfolio in the Americas region. Jim is recognized as a market visionary, championing Samsung’s memory transition and market evolution to provide a synergistic product portfolio covering the server, data center, AI, PC, tablet, phone, wearable device, and automotive markets. He joined Samsung in 2001 and has held leadership positions in both marketing and sales departments. Jim holds a Bachelor of Arts degree from the University of California, Davis and received a Master’s degree in Business Administration from Cal Poly University in San Luis Obispo, CA.

Keynote Description:

As we enter a new phase of the AI revolution, significant technological advancements are reshaping the way we think about computation and data processing. The rapid growth in data generation and complex workload requirements has led to increased computational power, enabling the development of sophisticated, large-scale AI models. This shift necessitates advanced GPUs and enhanced memory and storage solutions for learning and inference. These solutions must provide substantial bandwidth, power-efficiency, and durability to maintain checkpoints and support proliferated multimodal AI models. Concurrently, there is a need to address sustainability challenges, such as increased power and cooling demands within data centers. In this keynote, we will explore cutting-edge memory products and technologies essential for various AI applications, highlighting how NAND solutions and CXL memory modules can be tailored to optimize performance across each application. We will discuss how these technologies meet and drive the demand for high-capacity storage in AI computing, aiming to improve Total Cost of Ownership (TCO) through enhanced power efficiency and effective space management. Some of the main technologies we will cover include cutting-edge DRAM technologies such as 256GB RDIMM/512GB MRDIMM and CXL 3.1 memory modules. We will also discuss high-bandwidth PCIe Gen6, enabling high-speed data access and reliability to enhance GPU efficiency.

02:00 PM to 02:30 PM

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Open Keynote 5: FADU: Navigating AI: Hyperscale Flash Standards and eSSD innovation

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Sponsor:

FADU

Keynote Speakers:

Eric Spanneut, VP of Marketing, Western Digital

Eric Spanneut is Vice President of Flash Global Product Management at Western Digital. In this role, he is responsible for the company’s enterprise SSDs, client SSDs, eMMC and UFS product portfolio. Prior to Western Digital, Eric had management roles at Honeywell, Micron and Samsung Electronics. Eric earned his Master EE from Telecom Paris Institute of Technology and MBA from INSEAD.

Ross Stenford, Hardware Storage Engineer, Meta

Ross is a member of Meta’s Storage Hardware team. He has over 20 years of experience developing and bringing leading edge storage products to market. Ross works closely industry partners and standards organizations including NVM Express, SNIA/EDSFF, and Open Compute Project (OCP). With experience including ASIC design, he has an appreciation for the design challenges facing SSD providers to deliver performance and QoS within a shrinking power envelop. Ross holds over 40 patents.

Jiyho Lee, CEO and Co-Founder, FADU

Jihyo Lee is the CEO and co-founder of FADU Technologies. He is a former partner at Bain & Company and a successful serial entrepreneur involved in multiple businesses in technology, telecom and energy. As CEO of FADU, he has established FADU as a fabless semiconductor innovator, uniting exceptional industry talent to create a revolution in data center and storage for next generation computing architectures.

Keynote Description:

Today Hyperscale’s wield significant influence over flash storage consumption, with a handful of vendors commanding much of the market. Amidst this dominance, the surge of AI applications stands as a pivotal force, reshaping infrastructure demands at an unprecedented pace. This keynote presentation delves into the intersection of hyperscale growth, AI expansion, and flash storage evolution. Exploring the symbiotic relationship between infrastructure advancements and flash storage requirements, we dissect the implications for standardization efforts, particularly through initiatives like the Open Compute Project (OCP). Moreover, we unravel the novel features essential for flash storage to meet the soaring demands of hyperscale environments, offering insights crucial for navigating the future of storage technology.

02:30 PM to 03:00 PM

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Open Keynote 6: Microchip: Quantum-Proofing AI: Next-Gen Security for Protecting the World’s Data

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Sponsor:

Microchip Technology Inc.

Keynote Speakers:

Rob Reed, Senior Director of Product Development, Microchip Technology

Rob Reed is Senior Director of Product Development Engineering, Data Center Solutions Group for Microchip Technology. He is responsible for managing and designing storage silicon. Prior to this role, Rob was VP of Data Center SSD Engineering at Kioxia, responsible for the design and launch of Kioxia’s first Datacenter Gen4 PCIe / BICS4 SSD. Rob also worked at Intel as Product Development Manager for Solid State Drive products. Rob has expertise in engineering management, silicon architecture, product development, strategic planning and applications engineering. He holds 6 patents in the US on SSD storage. Rob holds a Batchelor's Honors Degree in Electronics and Communication engineering from the University of Huddersfield University.

Kyle Gaede, Associate Director, Microchip Technology

Kyle Gaede has been with Microchip Technology for nearly 25 years and is currently an Associate Director for the company’s segment group with a focus on data centers. Gaede holds a Bachelor of Science in Electrical Engineering from the University of Texas Austin.

Keynote Description:

In the rapidly evolving landscape of artificial intelligence (AI), data has become the new gold. The need to protect the data and the underlying infrastructure from a myriad of threats has never been more pressing. We will look at the challenges that organizations face, the complexities of security from the ground up and provide key strategies to mitigate risk in a post-quantum world. We will examine the unique vulnerabilities inherent in AI infrastructure, from data pipelines and machine learning models to the compute resources that power them. The discussion will highlight how these vulnerabilities can be exploited by adversaries to compromise the integrity, confidentiality and availability of AI systems. We will highlight real-world scenarios where security breaches have led to significant consequences, underscoring the importance of a proactive and comprehensive security strategy. We will introduce a multi-layered approach that encompasses the latest in cybersecurity best practices, tailored specifically for the nuances of AI systems. We’ll look at security for data at rest and in transit and protecting model integrity. We will also consider the implications of quantum computing and what is needed to address those challenges. Attendees will gain an understanding of the key issues and strategies to secure their AI infrastructure effectively and how Microchip is working across our portfolio and within the industry to create a complete security solution for protecting the world’s data.

03:00 PM to 03:30 PM

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Open Keynote 7: Western Digital

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Sponsor:

Western Digital

Keynote Speakers:

Robert Soderbery, Executive Vice President & General Manager, Western Digital

Keynote Description:

With the new era of NAND being driven by new industry dynamics Western Digital Executive Vice President & General Manager, Flash Business, Robert Soderbery, will discuss how the focus has shifted towards optimizing supply and demand, ensuring products meet customer needs, and navigating a market that is increasingly complex and segmented. He will share important insights on the critical role of storage in the AI data center all the way to the edge. Finally, Robert will reveal next-generation products and technologies fueling growth across the entire data cycle.

03:30 PM to 07:00 PM

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Open Grand Opening Reception

Exhibit Hall, Floor 1

Track: Exhibits

General Event Description:

FMS24 welcomes all attendees to their Grand Opening Reception in the Santa Clara Convention Center Exhibit Hall. Join fellow attendees and FMS24 sponsors to celebrate the Future of Memory and Storage!

03:40 PM to 04:45 PM

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PRO AIML-103-1: Memory to Data Center: Architectures and Interconnect Technologies

Ballroom B, Floor 1

Track: AI and ML Applications

Organizer:

David McIntyre, Director Product Planning, Samsung Electronics

Panel Members:

Kurtis Bowman, Director, Server System Performance, AMD

Kurtis Bowman is Director, Server System Performance at AMD. With more than 25 years of experience in the architecture, development, and business justification of server, storage, commercial, and consumer computing products, his current areas of interest include converged and hyperconverged systems, heterogeneous compute elements for HPC & machine learning, and data analytics. He has built teams and managed firmware and hardware development through entire lifecycles in both startups and mature companies. Mr. Bowman earned a BSEE from New Mexico State University, holds multiple patents, and has written articles in the technical and trade press.

Siamak Tavallaei, Sr. Principal Engineer, Samsung

Siamak Tavallaei joined the CXL effort as a founding member of the CXL Consortium and co-chair of the Technical Task Force (TTF) in 2019 to develop the CXL 2.0 specification. He has served on the CXL Board of Directors and as the CXL President. In 2016, he joined Open Compute Project (OCP) as a co-lead of Server Project. He is currently the Incubation Committee Representative for the Server Project where he drives open-sourced modular design concepts for integrated hardware/software solutions. He has served as Chief Systems Architect at Google Cloud Platforms where he led the architecture and productization of CXL-enabled solutions. His recent focus has been the optimization of large-scale, mega-datacenters for general-purpose and tightly-connected accelerated machines built on co-designed hardware, software, security, and management. His experiences as Chief Systems Architect at Google Cloud, Senior Principal Architect at Microsoft Azure’s Hardware Architecture team, a Distinguished Technologist at HP, a Principal Member Technical Staff at Compaq, and his contributions to industry collaborations such as CXL, OCP, EISA, PCI, InfiniBand, and PCIe give Siamak a broad understanding of requirements for the Enterprise, Hyperscale, and Edge datacenters for industry-wide initiatives.

Panel Session Description:

This exciting new session at FMS24 will discuss interconnect architecture considerations and provide an Ultra Architecture Link (UALink) and Ultra Ethernet Consortium (UEC) overview, A panel discussion will follow.

PRO AOSD-103-1: Aerospace and Outer Space Data NEW

Ballroom E, Floor 1

Track: Aerospace to Outer Space Data (AOSD)

Organizer + Chairperson:

TInh Ngo, VP Business and Technology Development, VIRTIUM

Tinh Ngo is Vice President at Virtium LLC. At Virtium, he leads business and technology development in the telecommunications and networking marketplace with a concentration around memory and storage solutions.

Paper Presenters:

Crystal Chang, Senior Manager, ATP Electronics

Paper Title:

Investigating NAND Storage Susceptibility to Single-Event Effects

Paper Abstract:

This study explores the susceptibilities of NAND Flash storage to both destructive and nondestructive single-event effects (SEE) induced by proton and heavy ion irradiation. The focus is on understanding how these memories respond to radiation exposure and the possible solutions based on experimental findings.

Author Bio:

Crystal Chang is an accomplished professional with a master’s degree in business administration from the University of Newcastle Upon Tyne, UK. With 15 years of experience at ATP Electronics, Crystal has demonstrated exceptional leadership in various domains. Her expertise extends to managing ATP Automotive, Thermal, and LEO satellite projects, where she drives continuous innovation and ensures successful design-ins.

George Williams, , Armijo Innovations

Paper Title:

The Next Frontier of Scaling Memory is Space

Paper Abstract:

The demand for higher density, lower latency, and more robust memory is greater than ever, and this global need is driving innovation up and down the technology stack - from new material substrates, to advanced interconnect photonics, to novel chip and datacenter architectures. Unfortunately even these measures may not be enough! Applications fueled by ever growing AI models and the burgeoning 6G internet are surpassing existing memory capacity both at the edge and at the datacenter. Pushing beyond the limitations of earth-bound commercial tech into space may just be the answer we need. The current terrestrial path of building more datacenters and installing more GPUs is not sustainable. Space, on the other hand offers infinite scaling potential for datacenters, with its nearly inexhaustible source of solar energy combined with relatively few regulations on expansion and growth. But how close are we to realizing this vision? We will talk about the R&D that is already underway to address many of the technical challenges of scaling memory and data storage into space- from advances in space-grade microelectronics, to photonic/quantum communication enabling satellite-based datacenter constellations. Along the way, disruption will occur at many levels - from a new supply chain that might require manufacturing chips in space, to new attack surfaces necessitating novel cybersecurity strategies, to the need for international collaboration beyond anything we've forged on earth.

Author Bio:

George Williams is Chief AI Officer at Armijo Innovations. He has held senior leadership roles in data science and artificial intelligence in industry at GSI Technology, Smile Identity, Capsule8, and Apple's New Product Architecture Group, as well as in academia at New York University's Courant Institute. He can talk on a broad range of topics at the intersection of e-commerce, machine learning, cybersecurity, computer hardware, computer science, and artificial intelligence. He is an author of several research papers in computer vision and deep learning, published at NeurIPS, CVPR, ICASSP, ICCV, and SIGGRAPH. George is regularly invited to present at meetups and technology conferences, including recent talks at Zilliz Unstructured Meetup, Open Compute Project, Storage Developer’s Conference, SEEMAPLD, Blackhat, Open Data Science Conference, Apache Spark Summit, JupyterCon, AnacondaCon, and Caltech’s Space Computing. He served as organizer and track chair for the Valleyml.ai conference and as a workshop program manager for the Vector Search Challenge at NeurIPS

Paul Armijo, , Armijo Innovations

Paper Title:

The Next Frontier of Scaling Memory is Space

Paper Abstract:

Author Bio:

Paul Armijo is the President & CEO at Armijo Innovations. He has senior leadership in roles including CTO in space and technology development industry at General Dynamics Mission Systems, Northrop Grumman, BAE Systems Space & Mission Systems, Frontgrade Technologies, GSI Technology, Secure Quantum Services, and Avalanche Technology. He has had the privilege of leading numerous flagship programs and technology development efforts over his career to further enable the space community. He has served various technical and session chairs as well as presented at various conferences in the space, memory, and AI community like SEE/MAPLD, ODSC, SPWG, HEART, NSREC, Space Computing, RHET, among many others. Paul received his B.S. in electrical engineering from Arizona State University.

Sebastien Jean, CTO, Phison Electronics

Sebastien Jean is the Chief Technology Officer at Phison Electronics, where he focuses on developing technology strategy and building alliances with other innovative companies. He also works closely with engineering teams to help integrate new concepts into products. With 26 years of experience and over 30 filed patents, he has established himself as a thought leader in the storage industry. Before joining Phison, he held senior technology positions at Micron, SanDisk, and Western Digital. At Phison, he helped devise an iterative technology roadmap that advances Security, AI, Computational Storage and Space Storage Solutions. He earned a BS in Computer Science at the University of Ottawa (Canada).

Dr Erik Nilsen, Chief Technology Strategist, Flexxon

Paper Title:

RAD-HARD NAND Storage for Aerospace and Outer Space Data (AOSD)

Paper Abstract:

The development of radiation-hardened NAND storage systems presents a critical advancement. By creating robust NAND storage solutions specifically designed to withstand the harsh radiation environments of space, a significant improvement in data reliability and longevity can be achieved. RAD-HARD NAND storage can withstand significantly higher levels of radiation than traditional NAND storage. RAD-HARD NAND storage is made from special materials and processes that make it resistant to radiation damage. This presentation will delve into the challenges faced in storing data in aerospace and outer space contexts, the unique requirements for radiation-hardened NAND storage, and the potential impact of such technology on enhancing data integrity and resilience in extreme environments.

Author Bio:

Dr Erik Nilsen is Flexxon’s Chief Technology Strategist, he works closely with the company’s executive management and R&D team to design and deploy technological roadmaps for its value-driven cybersecurity innovations. He also advises on the company’s ongoing work with its partners and customers to synthesize their needs and pain points with tailored solutions. Erik is a strong advocate for the decentralized Internet and espouses the advancement of digital methods and innovation to address the rising threat of cyberthreats. He is passionate about defining, developing, and launching new high-tech hardware & software products to meet the needs of digital citizens for the safe and secure navigation of today’s hyperconnected world. In addition to his role at Flexxon, Erik is a serial entrepreneur who co-founded TauTuk in 2021. As CTO, he led R&D efforts in next-generation cybersecurity and developed a pioneering product for out-of-band (analog) cybersecurity in industrial control systems and critical infrastructure. With advanced degrees in physics, electrical engineering, and mathematics, Erik's expertise spans signal processing and hardware & software development.

Paper Session Description:

In the realm of aerospace and outer space data storage, the development of radiation-hardened NAND storage systems is crucial. These robust solutions are specially crafted to withstand the intense radiation environments beyond Earth, ensuring enhanced data reliability and longevity. RAD-HARD NAND storage is equipped to endure high levels of radiation, thanks to its unique materials and manufacturing processes. This session will address the challenges of storing data in space, the specific requirements for radiation-hardened NAND storage, and the potential impact of this technology on fortifying data integrity in extreme conditions. It's a groundbreaking leap in data storage capabilities for the aerospace industry.

Open BMKT-103-1: CMO Panel

GAMR 1 (Great America Meeting Room 1), Floor 2

Track: Business Strategies and Memory Markets

Panel Session Description:

Description Not Available

PRO DCTR-103-1: Hyperscale Applications Part 2

Ballroom D, Floor 1

Track: Data Center Applications

Organizer:

Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft

Paper Presenters:

Hyung Kim, Technical Sourcing Manager, SSD/NAND, Meta

Paper Title:

What Hyperscale Cares About

Paper Abstract:

This talk will cover hyperscale's view on storage challenges and needs.

Author Bio:

Hyung is a Technical Sourcing Manager at Meta focused on meeting Meta's storage needs with deep experience in memory.

Venkatraghavan Ramesh, Hardware Systems Engineer, Meta

Paper Title:

TestDrive: Diagnostic for accelerated life testing

Paper Abstract:

Presenting ocp-diag-testdrive (under active development, planned deployment in ocp-diag repo in March) which uses ML techniques to extrapolate workloads captured on live production systems to provide more representative stress for SSD/HDD testing, and linux kernel probes to capture failure state.

Author Bio:

Venkat Ramesh is a Hardware Systems Engineer working in Meta's Infrastructure Org. Venkat leads various initiatives on diagnostics and telemetry development for SSDs and AI accelerators, and has led several programs to manage the lifecycle of Meta's database and cache hardware. In his past life, he worked on SMART telemetry software, as well as performance engineering teams at a couple of Flash vendors.

Vidhya Arvind, Staff Engineer, Netflix Inc

Paper Title:

Decoupling Services from Storage Engines Through Data Abstractions at Netflix

Paper Abstract:

At Netflix, the Data Access Team is innovating data management, decoupling services from storage engines using Data abstractions. The goal of abstraction is to expose a clean, stable interface, tailored to a wide array of use cases. The cornerstone of our approach is a sophisticated capacity planner, which analyzes users' access patterns to output the most suitable storage engine for the specific use case. For Example, Key-Value abstractions can be backed by a multitude of storage engines, including Cassandra, DynamoDB, and in-memory partitioned data using RocksDB SSTables. This decoupling process enables continuous evaluation and modification of storage solutions corresponding to a use case, all executed transparently with zero impact on our customers. Key to this approach is the "dual writes" methodology, enabling early issue detection and prompt rectification, thereby ensuring safe and seamless data migration between storage engines and allowing Netflix to optimize costs. We demonstrate a new standard in data storage and management and show the effectiveness of Data abstraction in enhancing storage efficiency.

Author Bio:

Vidhya Arvind is a Senior Software Engineer for Netflix building abstractions. She is a founding member of Netflix’s data abstraction platform, which supports common patterns including KeyValue, Tree, TimeSeries, Table Metadata, and more. She loves learning, debugging, scaling systems, and solving hard problems. Vidhya currently spends most of her time providing scalable abstractions for thousands of developers at Netflix. Rajasekhar Ummadisetty is a distinguished software engineer with a deep-seated interest in solving complex problems in distributed systems. He brings a wealth of experience in designing, building, and maintaining software solutions that can scale and perform in distributed environments. His passion for continuous learning and staying abreast of the latest industry trends enables him to consistently drive innovation and efficiency in his work. His expertise extends to data management, where he has made significant contributions to decoupling services from storage engines using data abstractions.

Paper Session Description:

Hyperscale is focused on tackling storage challenges head-on, addressing the needs of massive data management in today's digital landscape. This session will delve into the innovative solutions and strategies that are being implementing to optimize storage efficiency and enhance performance, including using data abstractions to create a clean and stable interface for a variety of use cases, and a diagnostic for accelerated life testing.

PRO DRAM-103-1: Influence of AI on Memory Technology NEW

Ballroom C, Floor 1

Track: DRAM

Organizer:

Ju Jin An, STSM, IBM

Paper Presenters:

Taekwon Jee, Principal Engineer, SK hynix

Paper Title:

A study of device yield optimization through human-AI collaboration

Paper Abstract:

Advanced generative AI technology developments such as LLM are having a significant impact on the entire semiconductor industry. Various semiconductor devices that can compute AI technology faster and more efficiently are emerging, but due to the diversity of designs, securing robustness in the various processes to actually manufacture them is becoming a major obstacle. To solve this problem, we developed a technology that can accurately predict process yield by combining the latest inline monitoring technology and vision machine learning. In this paper, the yield can be accurately predicted through experiments to secure machine learning-based process pattern fidelity in the latest N+2 DRAM node using the EPE (Edge Placement Error)-based all-in-one system, which represents process robustness. As a result, it can be seen that with the help of the latest machine learning and AI technologies, it is possible to lay a strategic foundation for securing extreme yields in various semiconductor processes.

Author Bio:

Taekwon Jee is currently working as a principal engineer at SK hynix since 2018. He is a semiconductor patterning and data analytics expert specializing in co-optimization of unit-module processes such as optical proximity correction, photolithography and dry etching. He is Interested in defect prediction, process optimization and control algorithms based on machine learning approaches and manufacturing domain knowledge. Before he join SK hynix, he has been working for the various sectors of semiconductor industry such as ASML, Samsung, Lam Research, and Intel. He got his PhD in mechanical engineering at University of California, Berkeley.

Bill Gervasi, Principal Systems Architect, Wolley Inc

Paper Title:

CXL Native Memory: Do We Really Need DDR?

Paper Abstract:

CXL memory modules enable memory expansion, enabling larger capacities to support emerging applications such as large language models where the LLMs demand 140GB or more of local capacity. HBM can't enable these large memory capacities, and CXL is a logical method to expand memory, but at significant cost in terms of power consumed and bandwidth wasted. Is DDR doing us any favors, and can we imagine a memory world without DDR? CXL Native Memory proposes to replace the inefficient DDR interface with a CXL direct physical interface that drives memory cores from the CXL FLIT without protocol retranslation. CXL Native Memory reduces memory latency overhead while saving power.

Author Bio:

Jim Handy, General Director, Objective Analysis

Paper Title:

Is HBM Headed to New Heights, or Is This Just Hype?

Paper Abstract:

AI is taking off like a rocket. The world is both charmed and alarmed by Generative AI and the ability of models like ChatGPT to replicate a lot of processes normally performed by humans. With that, the market for GPUs has exploded, and with it demand for High Bandwidth Memory (HBM) has suddenly seen phenomenal growth. Is this sustainable, or will it fizzle in the near term? Join this session to hear what seasoned analysts Mark Webb and Jim Handy expect for HBM going forward. The session will present not only two different HBM forecasts and cost models, but will also detail the technology and the challenges that it presents for DRAM makers, their customers, and the industry as a whole.

Author Bio:

Mark Webb, Analyst, MKW Ventures

Mark Webb is Principal/Consultant at MKW Ventures Consulting where he provides consulting services in SSDs, NAND, NVM, and semiconductor technology and competitive analysis. With over 25 years experience in semiconductor and system engineering and manufacturing, Mark consults with SSD OEM and ODM companies, memory manufacturers, and investment firms. Before founding MKW Ventures, Mark was Director of Manufacturing for the NVM Solutions Group at Intel, where he was responsible for SSD system and NAND component manufacturing. He also has been Corporate Product Quality and Reliability Manager for IM Flash Technologies, the widely publicized joint venture between Intel and Micron that became an industry leader in NAND technology. Mark is a frequent presenter at Flash Memory Summit and other key venues, and his analysis of technology adoption and product costs are often referenced by investment firms, analysts, technology training firms and major OEMs. He earned a BSEE at California State University, Chico.

Paper Session Description:

CXL Native Memory challenges the need for DDR by proposing a more efficient memory interface that directly connects memory cores to the CXL FLIT, reducing latency overhead and power consumption. With applications like large language models demanding over 140GB of local capacity, CXL memory modules offer a solution for memory expansion that HBM cannot match. Meanwhile, the increasing demand for High Bandwidth Memory (HBM) driven by the AI boom raises questions about its sustainability. This session will discuss the future of HBM, its cost models, and the challenges it poses for DRAM makers and the industry as a whole. Advanced AI technology is also revolutionizing semiconductor device yield optimization, with the development of machine learning-based process pattern fidelity to secure extreme yields in various semiconductor processes.

Open SPOS-103-1: CXL Member Implementations NEW

Ballroom A, Floor 1

Track: Sponsored Sessions

Sponsor:

CXL Consortium

Paper Presenters:

Jim Kao, SW Director, Xconn Technologies

Paper Title:

CXL 2.0 Fabric Deployment for a Composable Memory System

Paper Abstract:

Jim Kao will present CXL 2.0 Fabric Deployment for a Composable Memory System as part of the CXL implementations discussion.

Author Bio:

JIm Kao is Software Director at Xconn Technologies and a member of the CXL Consortium.

Sandeep Dattaprasad, Senior Product Manager, Astera Labs

Paper Title:

Importance of Pre-boot Environment for CXL Type 3 Devices

Paper Abstract:

This presentation on the importance of pre-boot environment for CXL Type 3 Devices is part of the CXL implementations session at FMS 2024.

Author Bio:

Sandeep Dattaprasad is a Senior Product Manager at Astera Labs with 15+ years of experience in semiconductor, software diagnostic tools, developing security strategies and firmware development for complex SoC product lines including Compute Express Link™.

Geof Findley, VP Business Development, Montage Technology

Paper Title:

CXL 2.0 Use Case

Paper Abstract:

Geof will speak on CXL 2.0 Use Case – Using both DDR4 and DDR5 on the same server to allow memory and bandwidth scaling .

Author Bio:

Geof Findley is WWVP of Business Development/Sales at Montage Technologies

Paper Session Description:

This session, sponsored by CXL Consortium, will feature presentations from three of its Member companies on their CXL implementations. • Importance of Pre-boot Environment for CXL Type 3 Devices (Astera Labs) • CXL 2.0 Use Case – Using both DDR4 and DDR5 on the same server to allow memory and bandwidth scaling (Montage Technologies) • CXL 2.0 Fabric Deployment for a Composable Memory System (Xconn Technologies)

PRO SSDT-103-1: Technologies for Improving the Endurance & Reliability of SSDs

Ballroom F, Floor 1

Track: SSD Technology

Organizer:

Erich Haratsch, Senior Director Architecture, Marvell

Paper Presenters:

Niles Yang, Flashtec Architect, Microchip Technology Inc.

Paper Title:

Flexible and Futureproof SSD Controller Archi\tecture for Next Gen NAND Memories

Paper Abstract:

Next generation NAND devices keep proliferating from multiple vendors with unique features and capabilities and corresponding standards. NAND devices that are obsolete or restricted prompts the use of alternative, second source devices to minimize supply chain disruptions and optimize the cost of SSDs. There are emerging needs for the versatile datacenter SSD controllers. Support for newer command sets, sequences and stringent waveform timing of the physical layer are some examples of such rising requirements for the SSD controller. Obviously, it is difficult to create an ASIC in advance of the new technologies that will match specifications that have not yet been developed. This can result in inefficiency, as well as reduced longevity of ASIC development. We will present a modern SSD controller architecture using a software controlled, high speed physical layer that allows us to specify every cycle to match any arbitrary interface waveform. This provides the required flexibility and efficiency to interoperate with the diverse high speed next generation NAND technologies and enable nimbler turnaround of SSDs with newer NAND devices.

Author Bio:

Niles Yang is an architect of the FlashtecTM® NVMe® SSD controller in the data center solutions business unit at Microchip Technology Inc. He has over 20 years of R&D experience in the field of non-volatile memory technology, design and system architecture. His current focus is on the development and optimization of the overall SSD architecture for data center applications. He holds 223 granted U.S. patents, and a Ph.D in semiconductor physics and CMOS process.

Maoruei Li, Project Deputy Manager, Silicon Motion

Paper Title:

Maximizing Cost Efficiency with True 16K LDPC for Advanced 3D NAND

Paper Abstract:

This presentation explores the transition from 4K to True 16K LDPC engines, addressing limitations of current 4K LDPC engines for next-gen NAND. We analyze power consumption and complexity in relation to correction capability, highlighting the need for flexible IU sizes in both 4K and 16K LDPC. Furthermore, we delve into overcoming performance constraints in 4K random reads with 16K LDPC codes. Additionally, we demonstrate how 16K codes offer significant benefits for advanced 3D NAND, particularly QLC, enhancing correction capability while managing power consumption effectively. Finally, we present 16K LDPC as a feasible solution, optimizing correction capability and power efficiency.

Author Bio:

Mao-Ruei Li is a Project Deputy Manager of Storage Research Department II at Silicon Motion. Prior to this role, he focused on a VLSI architecture of SERDES. He received the M.S. and Ph.D. Degrees in electrical engineering from Nation Tsing Hua University. His research in high speed SERDES and error correcting codes, including encoding/decoding algorithms, VLSI architectures. Currently, he is dedicated to developing an efficient VLSI architecture for LDPC codecs tailored for NAND applications.

Vic Ye, Manager, YeeStor Microelectronics

Paper Title:

Dynamic Read Retry Method

Paper Abstract:

As flash storage devices undergo wear and tear through program/erase cycles, they increasingly need more read retries for error correction, which slows down their read operations. The way read-retry methods are designed is crucial for maintaining the speed of these operations. Presently, flash chips use static read retry tables that don’t account for the specific read patterns or error characteristics. Our research involved analyzing various real flash chips to create models that identify the optimal read voltages for each page. With these insights, we've created a custom read retry table for each type of flash memory. This includes a dynamic process for selecting the right read voltages and a fine-tuning method to adjust them accurately. Testing with actual flash chips demonstrates that our approach significantly reduces the need for read retries, cutting the average down to less than 0.003 after 8K program/erase cycles with long-term data retention, compared to over 3 read retries for other current methods at just 3K cycles.

Author Bio:

Vic Ye holds the position of Flash Analysis Team Manager at YeeStor, a company specializing in the development of memory chips and storage controller technology. He and his team have pioneered a suite of analytical techniques for NAND flash memory, with a particular emphasis on innovating characteristics for 3D NAND technology. Previously, Vic served as an SSD Product Manager at SiliconGo and worked as an IC Design Engineer at Huawei. His academic credentials include a Ph.D. in Computer Science from the City University of Hong Kong and a Master's degree in Microelectronics from Tianjing University in China.

Doug Dumitru, CT0, EasyCo LLC dba WildFire Storage

Paper Title:

Maximizing Flash Storage Value with a Host FTL

Paper Abstract:

It has long been understood that NAND Flash performance and endurance is more a function of the logic of the controller than the NAND itself. The FTL (Flash Translation Layer) is the controller layer that maps logical blocks to NAND blocks. This layer is necessary for Flash to act like a standard block device instead of something closer to tape. By off-loading the FTL from the target SSDs to host software, we can better control performance, latency, redundancy, and wear. We will look at several approaches to FTL âoff-loadsâ including host software and co-processors boards. Using simulators and an FTL visualization, we can see how RAID, free space, over-provisioning, and compression impact performance and wear. In the end, users can optimize performance, redundancy, and operating costs without having to compromise one against the other.

Author Bio:

Doug Dumitru is CTO of Wildfire Storage. Doug has spent several decades improving the i/o performance and durability of Flash SSDs and Hard Disks through the creation and improvement of software based Flash Translation Layers.

Paper Session Description:

This session discusses technologies for improving the Endurance and reliability of SSDs, Flash storage devices require more read retries for error correction as they undergo wear and tear from program/erase cycles, slowing down operations. We will discuss various methods to analyze real flash chips, improve correction capability for advanced 3D NAND, and how to achieve better performance control and wear management, ensure longevity, and increase efficiency.

PRO UCIC-103-1: UCIe and Chiplets: A Panel NEW

Ballroom G, Floor 1

Track: UCIe and Chiplets

Organizer + Presenter:

Brian Rea, Technology Initiative and Ecosystem Enablement Manager, Intel

Panel Session Description:

Description Not Available

05:45 PM to 07:00 PM

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Open FMS 2024 Best of Show Awards

FMS Theatre, Floor 2

Track: FMS 2024 Special Sessions

Organizer + Moderator:

Jay Kramer, President, Network Storage Advisors

Jay Kramer, founder at Network Storage Advisors, is a dynamic results-oriented strategic marketing leader and creator of world-class marketing teams with a proven track record of building company brand and demand generation initiatives that accelerate sales. He has over 25 years of repeated marketing success with industry leading Fortune 500 companies (Unisys, Seagate) as well as early and late stage emerging companies. His industry knowledge spans cloud, virtualization, software defined storage (SDS), hyper convergence, data protection, SAN, NAS, and object storage solutions plus network storage technologies including Fibre Channel, iSCSI, VTL, dedup, backup, and replication. He has served as board member to technology industry associations and event development/professional conference companies.

Special Presentation Description:

The FMS24 Best of Show Awards recognize high-performance memory and storage innovations in eight distinct categories. These industry-recognized awards give winners the opportunity to effectively build their brand and image as an innovative leader in the marketplacThere are eight distinct award categories which address the wide range of high-performance memory and storage innovations in the market.

08:30 AM to 09:35 AM

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Open ASIA-201-1: Asia Memory and Storage Markets Part 1

Ballroom F, Floor 1

Track: Asia Memory and Storage Markets

Organizer:

Janet Liu, Project Manager, Sage Micro

Janet Liu is a project manager at Sage Microelectronics.

Paper Presenters:

Bryan Ao, Research Manager, TrendForce Corp.

Paper Title:

NAND market update- projection into 2025

Paper Abstract:

The NAND market has recently recovered from the server oversupply of 2023. TrendForce will provide a retrospective analysis of the NAND industry's capex and operating margin records over the past decade. We'll examine supply and demand dynamics to forecast future NAND price responses to market pressures. This presentation offers a strategic roadmap of NAND supply/demand, sufficiency ratios, and ASP trends. It will also explore major supplier strategies, capacity adjustments, and growth projections for the 2025 NAND market and beyond, outlining strategic implications for future trends.

Author Bio:

Analyst in NAND for over 5 years. Before I became an analyst, I was in sales across foundry, SSD controller and eletronic components for tier 1 OE/ODM factory in Asia

Alex Xie, Engineering Director, Suzhou OKN Technology Co., LTD.

Paper Title:

Testing technology energize high-quality development of the storage industry

Paper Abstract:

With high grow of semiconductor storage products, testing technology becomes one of the key factors to ensure products' quality and cost. OKN's storage test systems are designed for SSD and DDR, which help manufacturers to achieve best quality and reduce testing cost significantly from beginning design to volume production. OKN's GA300 SSD testers support NVME PCIe 5.0 and SATA/SAS with an integrated adjustable thermal and power conditions; OKN's SW400 DDR tester support DDR5, which is fully automatic with providing ATE/SLT testing functions

Author Bio:

18+years engineerring experience in storage industry, mainly be responsible for products strategy development

Paper Session Description:

Emerging trends in automotive technology are driving efficiency and innovation through the integration of Dynamic Random Access Memory (DRAM) in automotive systems. DRAM like HBM3 and GDDR6 enable faster data processing, improved real-time decision-making, and enhanced safety features in modern vehicles. This comprehensive analysis explores the impact of DRAM integration in areas such as advanced driver assistance systems, autonomous driving platforms, and vehicle-to-everything communication networks. Furthermore, we examine the convergence of high-bandwidth and low power consuming DRAM technology in automotive innovation, highlighting the transformative potential for smarter, safer, and more efficient vehicles.

Open CLDS-201-1: Cloud Architectures

Ballroom B, Floor 1

Track: Cloud Storage and Applications

Organizer:

Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft

Paper Presenters:

Nick Kriczky, Vice President, Teledyne LeCroy - Austin Labs

Paper Title:

The Benefits of OCP Compliance for NVMe SSD drives

Paper Abstract:

Hyperscale compute environments continue to push the requirements for NVMe SSD's with new versions of the OCP specification. With the additional features of the specification there is a need to go beyond traditional NVMe testing. Contributor companies to the OCP specification work together to drive new test requirements and an approved test specification. Learn about the tests that are being defined and the benefits those tests provide for NVMe and OCP Datacenter SSD's. Potential additional presenters would come from Microsoft and Meta.

Author Bio:

Nick Kriczky is Vice President of Products and Services for Teledyne LeCroy. With 30 years in the test and measurement industry Nick brings a long history of developing new products for validating cutting edge technologies. Additionally, Nick Manages Teledyne LeCroy's Austin Labs which is the premier third-party test facility. We help our customers overcome testing challenges in their products including Data Integrity, Performance Analysis, Protocol Analysis and compliance, Error Injection, Signal Integrity, Electrical Compliance, Interoperability, Design and Feasibility.

Chunmei Liu, Senior Engineer, Intel

Paper Title:

Performance Analysis and Optimization for Multicore Crimson

Paper Abstract:

Ceph is a distributed cloud storage solution. Crimson is a project to refactor ceph osd based on the shared-nothing seastar framework. We have already implemented multicore and multithreaded architecture for crimson. The main effort now is focused on performance analysis and improvement. This presentation will introduce the goal we need to meet in crimson and the problem we brought into by the implementation and the method for finding the problem and final solution for them. This presentation will show how we do the performance analysis and how to track workflow for crimson multicore/threads architecture and based on the discovery what kind of solution will be provided for improving performance. For example, how to guarantee the IO request sequence, how to avoid cross-core copy etc.

Author Bio:

Chunmei Liu has about 20 years work experience on network security, virtualization, and cloud storage. She is working on Cloud storage about 10 years, and she is one of the main and original developers of crimson which is a project for refactoring ceph osd. She is mainly focus on Ceph RBD workflow and implement some features for crimson.

Douglas Arens, Technical Staff, Applications Engineer, DCS, Microchip Technology

Paper Title:

Achieving scalability with newer Virtualization in Cloud Computing SSDs

Paper Abstract:

SR-IOV is a primary virtualization technology to scaleÂ HW resources in the data centers and cloud storage to improve Total Cost of Ownership (TCO), CPU utilization, reducing latency. Continuing with the development in the virtualization technologies and the underlying controller architecture for NVMe SSDs need to adapt and align with the evolving technology as the virtualization is transitioning from SR-IOV to SIOV (Scalable IO Virtualization) Â to push the boundaries of virtualization. This presentation will discuss the structure and resource limitations of SR-IOV, and how SIOV can step beyond those limitations. As well as what is needed in the solution across software, controller, and firmware to achieve the increased scale and efficiency of SIOV.

Author Bio:

Douglas Arens is Technical Staff, Applications Engineering for FlashtecTM NVMe SSD Controllers in the Data Center Solutions Business Unit of Microchip Technology Inc. Doug has contributed to the product development activities for Enterprise Storage products for the last 15 years. Doug presented regarding Virtualization at FMS last year. He graduated with BSCS from Iowa State University and has two patents awarded.

Paper Session Description:

In this presentation, we will delve into the world of virtualization in cloud computing and how newer technologies such as Scalable IO Virtualization (SIOV) are revolutionizing the way we handle hardware resources in data centers and cloud storage. We will explore the transition from SR-IOV to SIOV, and how this shift is pushing the boundaries of virtualization to achieve greater scalability and efficiency. Additionally, we will discuss the performance analysis and optimization for multicore Crimson Ceph, highlighting the benefits of refactoring ceph osd based on the shared-nothing seastar framework. We will dive into the challenges faced during implementation and the solutions found to improve performance. Finally, we will explore the importance of OCP compliance for NVMe SSD drives in hyperscale compute environments, showcasing the new test requirements and benefits provided by the OCP specification. Join us to learn from industry experts and discover the future of virtualization, storage, and performance optimization.

Open COMP-201-1: Computational Storage Use Cases - a Panel

Ballroom G, Floor 1

Track: Computational Storage

Organizer:

Scott Shadley, Strategic Planner, Solidigm

Paper Presenters:

JB Baker, VP Marketing, ScaleFlux

Paper Title:

Computational Storage Case Studies & Applications

Paper Abstract:

As computational storage advances from a futuristic concept to mainstream deployment, how has the vision changed? What functions are truly being deployed now and to what benefits for the users? What functions are in development and lining up for deployment in the coming quarters? Join us to hear from several of the vendors shipping and developing computational storage solutions to get grounded on what's really going on and how you can utilize computational storage to improve your power efficiency, infrastructure performance, and overall TCO. NOTE: I intend for this to be a panel discussion & pull in representatives from other vendors in the CS space to highlight case studies and CS functions.

Author Bio:

Currently VP of Product Management and Marketing at ScaleFlux, focusing on innovative SSD technologies and computational storage. JB has led product management and marketing teams in the storage industry for 20+ years across Intel, LSI, and Seagate before joining ScaleFlux.

Pan Zicheng, IC Application, staff engineer, Beijing Starblaze Technology

Paper Title:

Distributed Software Architecture in SSD

Paper Abstract:

With the advent of PCIe, SSDs have witnessed a significant surge in speed in recent years. This advancement has revolutionized storage technology, enabling SSD controllers to boast intricate architectures comprising multiple CPUs and numerous hardware accelerators. The integration of these components has not only enhanced the speed of SSDs but also expanded their capabilities, allowing them to execute software applications akin to traditional computers. This paradigm shift in SSD architecture opens up new possibilities for optimizing computational workflows and offloading tasks from the host system. In this context, we present a distributed software architecture tailored specifically for SSDs aimed at offloading computational burdens from the host system. By harnessing the power of SSDs' advanced architecture, we have developed a novel approach to distribute computing tasks across SSDs, thereby optimizing performance and efficiency. For instance, we leverage "File System in SSD" and "Database in SSD" as exemplary implementations of this approach, demonstrating significant improvements in computational throughput and reduced latency.

Author Bio:

Graduated from Shanghai Jiao Tong University. IC application staff engineer in Beijing Starblaze Technology. Participate in SSD controller STAR2000 and STAR1500 projects, both chip design and firmware development.

Tim Fisher, Flash Controller HW Lead, IBM

Paper Title:

Computational Storage: Deduplication aided by Compression

Paper Abstract:

Computational storage is a hot topic, however, it needs definition and compelling use cases. In enterprise storage appliances, data reduction is essential for customers to realize better storage utilization, performance, reliability, and cost. Compression done at the SSD or storage level is still one of the best use cases for computational storage, but deduplication is seen by many to be better performing at the appliance level, where there is more visibility to the entire data set. However, the SSD can provide valuable acceleration for deduplication to reduce CPU cycles at the appliance and use less system bandwidth. Furthermore, this presentation will cover how an SSD that has hardware compression can make deduplication even more efficient for the appliance.

Author Bio:

Tim Fisher is the Chief Architect and Design Lead for the for IBM FlashCore Module (FCM). Tim started his career in storage at Texas Memory Systems in 2007 where he was a flash controller designer for one of the first ever Enterprise All Flash Arrays, the RamSan-500. Tim has continued his career in flash controller design to the present date with IBM through the acquisition of Texas Memory Systems, and has lead enterprise SSD designs for SLC, MLC, TLC, and QLC NAND Flash technology. He is an STSM and master inventor at IBM, with over 50 patents related to storage innovation.

Paper Session Description:

With the rise of PCIe and advanced architecture in SSDs, distributed software architecture is transforming the way computational tasks are handled. By offloading tasks from the host system to SSDs, significant improvements in performance and efficiency can be achieved. For example, utilizing "File System in SSD" and "Database in SSD" showcases enhanced computational throughput and reduced latency. Furthermore, combining deduplication and compression at the SSD level can optimize storage utilization, performance, and cost in enterprise storage appliances. Join us for a panel discussion with industry experts to explore real-world case studies and applications of computational storage, highlighting the tangible benefits and future developments in this space.

Open CXLT-201-1: CXL Form Factors

Ballroom E, Floor 1

Track: CXL

Organizer + Chairperson:

Arthur Sainio, Director, Product Marketing, SMART Modular Technologies

Arthur Sainio is Director of Product Marketing at SMART Modular Technologies, where he leads efforts in new technologies such as persistent memory including MRAM and NVDIMMs. He has been a major promoter of persistent memory and NVDIMMs since they were first introduced. He has organized and presented sessions at Flash Memory Summit, Storage Developer Conference, and the SNIA Compute, Memory, and Storage Summit and has participated in many webinars and blogs. He is the co-chair of the Persistent Memory Special Interest Group within SNIA, which is focused on accelerating the awareness and adoption of persistent memory and creating new standards. Arthur was honored with the SNIA Exceptional Leadership Award in 2022. Before joining SMART Modular, Arthur was a product marketing manager at Hitachi Semiconductor. Arthur earned an MBA from San Francisco State University and an MS from Arizona State University.

Paper Presenters:

Andrew Mills, Snr Director Advanced Product Development, Smart Modular Technologies

Paper Title:

Non-Volatile and Large Memory Applications and Trends utilizing CXL

Paper Abstract:

Introduction to CXL memory expansion options and formfactors, both volatile and non-volatile, for industry standard X86 servers. Address near term options and what to expect over the next 2-3 years, including optical connectivity options currently being researched. Cover 1-2 example applications, including example of one architecture for a petabyte class CXL compute-memory environment for AI/ML. Short recap and introduction to non-volatile persistent memory requirements, addressing need for high availability over the next few years as CXL starts to mature into a mainstream option for all classes of servers.

Author Bio:

Andy Mills is the Snr Director of Advanced Product Development at SMART Modular Technologies, where he leads the development of next generation CXL memory and data center storage solutions. Prior to joining SMART, Andy was CEO/co-founder of Enmotus, Inc where he co-developed and led the development of intelligent storage and memory tiering solutions for data center and high end PCs utilizing advanced learning algorithms driven by real time intelligent workload analysis. He has more than 30 years industry experience in software development, systems architecture, networking, storage and semiconductor development, plus held various management and technical lead positions at DotHill Systems, NetCell Corporation, TDK Semi, AMD. Andy graduated with an MEng and BEng with Honors from Bangor University in the UK.

Ron Swartzentruber, Director of Engineering, Lightelligence

Paper Title:

Optical CXL advantages for memory pooling applications

Paper Abstract:

Optical CXL will fundamentally change the way datacenters are architected for AI and confront the memory bandwidth needs of LLM processing. Memory pools containing models with hundreds of billions of parameters need to be coherently connected to large arrays of processors in a disaggregated compute architecture. CXL-capable processors, accelerators, switches, and memories are being developed along with sophisticated fabric management software, allowing massive systems to be built to connect compute arrays to large amounts of memory. Due to the sheer size of these systems, resources must span across multiple racks in the datacenter. Memory bandwidth and latency are critical factors impacting the time to train large AI models. CXL over optics solves the bandwidth, latency, and distance challenges demanded by LLM applications used in disaggregated memory pooling applications. This presentation will illustrate the latency and performance improvements that can be achieved with an optical CXL fabric and the benefits of memory pooling. The distance advantages and decode throughput results will be examined from a LLM inference application.

Author Bio:

Ron Swartzentruber is Director of Product Management at Lightelligence and manages CXL-over-optics products used for inter-connecting CPUs, GPUs and memory over an optical fabric. Ron has extensive experience in compute architecture for the cloud networking and network communication industries and holds 21 patents for inventions conceived throughout his career.

Bill Gervasi, Principal Systems Architect, Wolley Inc

Paper Title:

FleCXL: Bringing CXL to the Motherboard

Paper Abstract:

CXL integration into big iron is well underway with focus on large and high power form factors such as E3.S, however less is said about bringing CXL to embedded environments like motherboards. Proposed here are smaller implementations of CXL in an M.2-style module with PCIe x8 interface. Called FleCXL, this socketed module enables new classes of innovation for next generation systems by exploiting CXLs generalizing of interfaces to memory, storage, and accelerators.

Author Bio:

Paper Session Description:

As CXL integration expands into large systems, the focus shifts to bringing CXL to embedded environments like motherboards. We’ll discuss how next-gen systems are using CXL's versatile interfaces for memory, storage, and accelerators. The session will also discuss the latest options for CXL memory expansion in X86 servers, both volatile and non-volatile, with a glimpse into future trends and optical connectivity advancements, with real-world examples. We will also take a look at the impact of optical CXL on datacenter architecture for AI and LLM processing, offering bandwidth and latency solutions for massive memory pooling applications.

Open DCTR-201-1: Enterprise Storage Part 1

Ballroom D, Floor 1

Track: Data Center Applications

Organizer:

Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft

Paper Presenters:

Paul McLeod, Product Director, Storage, Supermicro

Paper Title:

Next Generation Storage Form Factors for Storage Systems

Paper Abstract:

The recent adoption of EDSFF E1 and E3 form factors for SSDs as well as the adoption of CXL interfaces for memory and storage have added new features and tradeoffs to the existing 3.5 LFF SAS, 2.5 U.2 SAS and PCIe, and M.2 storage form factors. In this session, we discuss the system level design tradeoffs for storage servers and the future direction of storage servers using industry standard form factors.

Author Bio:

Paul McLeod has over 20 years of experience in the storage and server industry including 12 years Supermicro where he is currently a product director. He was previously a Sr. Field Applications Engineer at Supermicro and a Product Marketing Engineer at Promise Technology. Paul was an early advocate of software defined storage using industry standards and has worked with numerous customers on designing large scale server and storage implementations.

Tim Fisher, Flash Controller HW Lead, IBM

Paper Title:

Enterprise QLC - Reliability, Performance, and Workloads

Paper Abstract:

Enterprise Storage Appliances that use QLC based NAND Flash SSDs are starting to become more prevalent in the market. However, there are still a lot of unknowns as it relates to the number of drive writes per day that are required and other reliability factors as it relates to the individual drives that make up the array. Furthermore, do the proof of concept (POC) workloads and performance at a drive level really reflect what an SSD can experience in an appliance. This presentation will talk about some of these details and concepts that may help to drive future specifications for Enterprise QLC NAND Flash SSDs used in All Flash Arrays. This can help lead to drives that are designed to fit properly in these environments and help reduce cost associated with developing for un-realistic requirements.

Author Bio:

Odie Killen, VP Hardware Engineering, Viking Technologies

Paper Title:

High Perf Array Optimization for PCIe Gen5 Data Rates

Paper Abstract:

Design and architecture considerations to optimizing of BW capabilities presented by PCIe Gen5 data rates. Includes trade offs of CPU performance versus SSD performance. PCIe lane topology and general topology considerations

Author Bio:

Odie Killen is an accomplished Global Engineering leader with over 30 years of experience in high technology, working in Defense, Design, Manufacturing, Cloud, Hyper-converged (HCI), Data Center, Enterprise Server, Storage, and IT markets. He has worked extensively in the architecture, design and implementation of flash based and rotating media storage systems, as well as storage networking hardware. Granted 14 US patents with others pending. Odie holds a Master’s of Science degree in electrical Engineering from the University of Colorado.

Paper Session Description:

Open INVT-201-1: Invited Talk with Andrew Walls

GAMR 1 (Great America Meeting Room 1), Floor 2

Track: Invited Talks

Organizer + Chairperson:

Leah Schoeb, Sr. Developer Relations Manager, AMD

Paper Presenters:

Andrew Walls, IBM Fellow, CTO FlashSystem, IBM

Paper Title:

QLC Advances Will Eliminate Nearline HDDs in Enterprise Storage

Paper Abstract:

QLC advances in layer count and therefore density will allow for large increases in SSD capacities in the near future. IBM has developed computational storage capabilities to provide data reduction on large capacities without huge controller and memory costs. Having this computational storage capability combined with large capacities will challenge the need and complexity for Nearline drives in all in enterprise storage. In this talk, Andy Walls will explain how this can truly reduce the TCO to the point where simple and extremely dense and power-efficient SSD arrays will eliminate the need to have a tier of Nearline HDDs.

Author Bio:

Andy Walls is Chief Architect and CTO for IBM’s Flash Systems. He is also an IBM Fellow, IBM’s most prestigious Honor. Andy is a pioneer in enabling flash into the enterprise and has shaped the IBM storage portfolio to be highly differentiated and popular. He is well known in the industry for his storage and flash expertise. He leads the architecture and definition of the Entire FlashSystems NVMe product portfolio as well as the FlashCore Module. He is on the leading edge of computational storage by incorporating data reduction and Ransomware Detection capabilities directly in the FCM.

Paper Session Description:

QLC advances in layer count and therefore density will allow for large increases in SSD capacities in the near future. IBM has developed computational storage capabilities to provide data reduction on large capacities without huge controller and memory costs. Having this computational storage capability combined with large capacities will challenge the need and complexity for Nearline drives in all in enterprise storage. In this talk, Andy Walls will explain how this can truly reduce the TCO to the point where simple and extremely dense and power-efficient SSD arrays will eliminate the need to have a tier of Nearline HDDs.

Open OMEM-201-1: Emerging Memories

Ballroom C, Floor 1

Track: Other Memory Technologies

Organizer + Chairperson:

Dave Eggleston, Sr Business Development Manager, Microchip Technology

Dave Eggleston is Sr. Business Development Manager at Microchip. Dave's extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at SanDisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.

Paper Presenters:

Tom Coughlin, President, Coughlin Associates

Paper Title:

Life Beyond Flash: Will Emerging Memories Take Over?

Paper Abstract:

Flash memory has scaled beyond what was thought possible 20 years ago. Can this continue, or will an emerging memory technology like MRAM, ReRAM, PCM, or FRAM move in to replace it? Are there other memory technologies threatened with similar fates? What will the memory market look like in another 20 years? This talk will explain emerging memory technologies, the applications that have already adopted them in the marketplace, their impact on computer architectures and AI, the outlook for important near-term changes, and how economics dictate success or failure. Noted Analyst Jim Handy, and IEEE President Tom Coughlin will present the findings of their latest report as they discuss where emerging memories complement CXL, Chiplets, Processing In Memory, Endpoint AI, and wearables, and they explain the inevitability of a conversion from established technologies to new memory types.

Author Bio:

Tom Coughlin, President, Coughlin Associates is a digital storage analyst as well as a business and technology consultant. He has over 40 years in the data storage industry with engineering and management positions at several companies. Dr. Coughlin has many publications and six patents to his credit. Tom is also the author of Digital Storage in Consumer Electronics: The Essential Guide, which is now in its second edition with Springer. Coughlin Associates provides market and technology analysis as well as Data Storage Technical and Business Consulting services. Tom publishes the Digital Storage Technology Newsletter, the Media and Entertainment Storage Report, the Emerging Non-Volatile Memory Report and other industry reports. Tom is also a regular contributor on digital storage for Forbes.com and other blogs. Tom is active with SMPTE (Journal article writer and Conference Program Committee), SNIA (including a founder of the SNIA SSSI, now CMSI), the IEEE, (he is an IEEE President in 2024, Past Director for IEEE Region 6, Past President of IEEE USA, Past Chair of the IEEE New Initiatives and Public Visibility Committees and active in the Consumer Electronics Society) and other professional organizations. Tom is the founder and organizer of the Storage Visions Conference (www.storagevisions.com) as well as the Creative Storage Conference (www.creativestorage.org). He was the general chairman of the annual Flash Memory Summit for 10 years. He is a Fellow of the IEEE and a board member of the Consultants Network of Silicon Valley (CNSV)

Amir Regev, CTO, Weebit-nano

Paper Title:

ReRAM: Emerging Memory Goes Mainstream

Paper Abstract:

ReRAM today is being integrated as an embedded non-volatile memory (NVM) in a growing range of processes from 130nm down to 22nm and below for a range of applications: automotive, edge AI, MCUs, PMICs and others. It is low-power, low-cost, byte-addressable, scales to advanced nodes, and is highly resilient to a range of environmental conditions including extreme temperatures, ionizing radiation and electromagnetic fields. In this session, Weebit will discuss what technology enhancements are needed to proliferate ReRAM even further into applications with extended requirements. We will discuss the latest technical and commercial developments including data in advanced processes.

Author Bio:

Amir Regev is VP of Quality and Reliability at Weebit Nano. He has two decades of experience in semiconductor devices and technology, with particular expertise in flash memory technology. He previously held senior engineering roles at companies including Intel, SanDisk, Micron and Marvell. Amir holds a M.Sc. in Electrical Engineering from Tel-Aviv University and a B.Sc. in Material Science and Engineering from Ben-Gurion University.

James Pan, Senior Principal Engineer Project Manager, Northrop Grumman

Paper Title:

Ultra-High Speed Photonic NAND FLASH

Paper Abstract:

Ultra-high-speed operations with much lower voltages and power consumption can be achieved with the Photonic NAND FLASH technology. A Photonic NAND FLASH memory consists of a vertical NAND FLASH transistor (which is a traditional vertical NMOSFET with multiple gates as Word Lines), Lasers or LEDs in the top drain region, and photon sensors in the well region. When gate voltages are forced to the Word Lines, and a drain voltage is applied (Bit Line), the entire vertical NAND FLASH NMOSFET is turned on (READ operation). When the gate voltage is set to 0V, the vertical NAND FLASH NMOSFET is turned off, so as the lasers and photon sensors. In this report we will discuss: (1) Energy band diagrams for the WRITE and ERASE cycles of Photonic NAND FLASH. (2) Fowler Nordheim Tunneling, Frenkel Poole Tunneling, Traps-Enhanced FN Tunneling, and Photon-Enhanced Tunneling for Photonic NAND FLASH. (3) Data showing Higher the Photonic NAND FLASH Laser power, lower the WRITE time and operating voltage. (4) Photonic NAND FLASH Operating Voltage and WRITE / ERASE times vs. Laser Power.

Author Bio:

Manus Hayne, Chief Technology Officer, Quinas Technology

Paper Title:

ULTRARAM: Progress and prospects

Paper Abstract:

PROGRESS. We will report on the technical progress of UTRARAM since we introduced it to FMS in 2023. Crucial requirements for ULTRARAM’s technical and commercial advancement are the development of a dry-etch fabrication processes compatible with device scaling and integration of devices into arrays. We report on the results of an improved self-aligned process in device fabrication and the production of small arrays. Having previously observed that temperatures of 100 C (212 F) induced no discernible change in the charge stored in ULTRARAM devices with the logical state completely unaffected, we have now pushed these experiments up to 200 C (392 F). PROSPECTS. I will highlight opportunities for ULTRARAM in specific applications that will benefit from its extraordinary set of properties. These include space, where its unrivalled energy efficiency and tolerance to extremes in temperature are key; extreme cryo-computing, where its ability to work at the very lowest achievable temperatures is advantageous for interfacing with quantum computers; in-ULTRARAM arrays for highly-efficient and massively parallel matrix multiplication in AI applications.

Author Bio:

Prof Hayne is co-founder and Chief Scientific Officer of Quinas Technology Ltd, and recipient of the 2023 UK Elektra Awards ‘Readers’ Choice Award University Research Group of the Year’ for his work on ULTRARAM. He is Deputy Head of the Physics Department at Lancaster University, Director of Research, Director of Business Engagement and Impact Champion. He is co-author on >100 articles and (co-)inventor on four (pending) patent families, three of which are on ULTRARAM and related technologies. He gained a BSc in Physics with Electronics from Southampton University and a PhD in Physics from Exeter, and spent 10 years working in Paris and Leuven before being appointed at Lancaster.

Jim Handy, General Director, Objective Analysis

Paper Title:

Life Beyond Flash: Will Emerging Memories Take Over?

Paper Abstract:

Author Bio:

Paper Session Description:

In this session, we discuss emerging memories. Ultra-High Speed Photonic NAND FLASH technology revolutionizes memory operations by achieving ultra-high speeds with lower voltages and power consumption. This technology combines vertical NAND FLASH transistors with lasers/LEDs and photon sensors for efficient READ operations. ReRAM is now mainstream in applications such as automotive and edge AI due to its low power, scalability, and resilience to environmental conditions. We will explore the technology enhancements needed for wider adoption and the latest developments in advanced processes. ULTRARAM boasts exceptional properties like energy efficiency and extreme temperature tolerance, making it ideal for space and high-performance computing applications. We will highlight progress in fabrication processes and potential applications. Finally, we will discuss life beyond flash and the future of memory technologies like MRAM, ReRAM, PCM, and FRAM. Analysts will explore the impact on computer architectures, AI, and the memory market in the next 20 years, emphasizing the inevitability of transitioning to emerging memory types.

Open SPOS-201-1: NVMe 2.1 Specification, CXL Support & Windows Innovations NEW

Ballroom A, Floor 1

Track: Sponsored Sessions

Sponsor:

NVM Express

Paper Presenters:

Scott Lee, Software Engineer Lead, Microsoft

Paper Title:

NVMe® Innovations in Windows

Paper Abstract:

The session will provide updates on Windows support of the NVMe® family of specifications providing information on new features available and guidance to the industry on how best to work with some existing and new features planned in the areas of device power and device reliability.

Author Bio:

Scott Lee is a software Engineer with 10+ years of experience from startup to Fortune 50 working in Open-Source, Video Gaming, Commercial Scientific Software, Internal Research Tools and Web Development.

Phil Cayton, Principal Engineer, OpenFabrics Alliance

Paper Title:

NVMe 2.1 Specification Overview and SOTU

Paper Abstract:

Author Bio:

Phil Cayton is a Principal Engineer at Intel, leading research and development on Composable Disaggregated Infrastructures (CDI), HPC fabrics, and non-volatile local and remote storage technologies. He has over 25 years’ experience in architecture and software design, has applied for or been granted 23 patents, has several published technical articles, and has presented at many, many conferences. He is involved with, has worked on, and has influenced several industry specifications including NVMe, SNIA Swordfish, and the Open Fabrics Alliance (OFA) Sunfish CDI Framework. Notably: He was one of the original architects and designers of NVMe-over-Fabrics (NVMe-oF), wrote the initial NVMe-oF driver stack, was a primary author of the NVMe Boot Specification, and helped architect the open-source prototype of booting over NVMe/TCP. He is a principle architect of Sunfish, developing a technology and vendor agnostic framework for developing true composable disaggregated server infrastructures. He has spent several years as a principle architect developing the SNIA Swordfish storage management specification and associated profiles and prototypes.

Bill Martin, Principal Engineer SSD I/O Standards, Samsung Electronics

Paper Title:

NVM Express® (NVMe®) Support for CXL®

Paper Abstract:

As CXL becomes the memory interface protocol of choice, connecting CXL memory and NVMe Subsystem Local Memory (SLM) becomes critical. SLM allows access to memory on an NVMe device with NVMe commands. This memory is then used for the Computational Programs Command set. To improve performance and to enable new paradigms of Computational Programs, it is beneficial for the SLM to be able to be accessed using CXL. NVMe Host Addressable SLM is being developed to allow the mapping of SLM to the Host Physical Memory Address space using Host-Managed Device Memory (HDM) addressing. This presentation will bring you up to speed on where this development effort is.

Author Bio:

Bill Martin has over 30 years of experience in the storage industry. He is currently responsible for driving Solid State Storage forward within the industry for Samsung in a variety of standards arenas, including NVM Express board member, Co-Chair of the SNIA Technical Council, Chair of the SCSI T10 Committee, Co-Chair of the of the NVMe Computational Storage Task Group, Co-Chair of the SNIA Computational Storage Technical Work Group, Secretary of ATA T13 Committee, and editor of the SCSI T10 Block Commands document. He has also had extensive experience in the Fibre Channel arena including with the T11 Standards committee and leading FC interoperability events. His employers have included HP, Gadzoox, Brocade, Sierra Logic, Emulex and now Samsung. His industry work has been recognized with numerous awards from NVMe, INCITS, FCIA and SNIA.

Jason Molgaard, Principal Storage Solutions Architect, Solidigm

Paper Title:

NVM Express® (NVMe®) Support for CXL®

Paper Abstract:

Author Bio:

Jason Molgaard is an experienced storage controller RTL designer and architect having worked for various storage device companies architecting and designing HDD and SSD storage controllers. As a Principal Storage Solutions Architect on the Solidigm Pathfinding and Advanced Development Team, Jason focuses on future storage controller architectures and technologies, including Computational Storage and CXL. Jason is co-chair of the SNIA Computational Storage TWG and the SNIA Technical Council. Jason helps drive the Computational Storage standard at both SNIA and NVMe. Jason holds a Master of Science degree in Electrical Engineering.

Paper Session Description:

NVMe technology has become synonymous with high-performance storage and with widespread adoption in client, cloud, and enterprise applications. Although initially developed for direct-attached PCIe SSDs, NVMe architecture is now widely used in both direct-attached and fabric-attached applications. This presentation provides an overview of the latest NVMe technologies, summarizes the NVMe standards roadmap, and describes new NVMe standardization initiatives. NVM Express (NVMe) Support for CXL As CXL becomes the memory interface protocol of choice, connecting CXL memory and NVMe Subsystem Local Memory (SLM) becomes critical. SLM allows access to memory on an NVMe device with NVMe commands. This memory is then used for the Computational Programs Command set. To improve performance and to enable new paradigms of Computational Programs, it is beneficial for the SLM to be able to be accessed using CXL. NVMe Host Addressable SLM is being developed to allow the mapping of SLM to the Host Physical Memory Address space using Host-Managed Device Memory (HDM) addressing. This presentation will bring you up to speed on where this development effort is. NVMe Innovations in Windows The session will provide updates on Windows support of the NVMe family of specifications providing information on new features available and guidance to the industry on how best to work with some existing and new features planned in the areas of device power and device reliability.

09:45 AM to 10:50 AM

No search results found in this timeslot.

PRO ASIA-202-1: Asia Memory and Storage Markets Part 2

Ballroom F, Floor 1

Track: Asia Memory and Storage Markets

Organizer:

Janet Liu Erickson, Project Manager, Sage Micro

Janet Liu Erickson is a project manager at Sage Microelecronics.

Paper Presenters:

Mark Liu, Research Manager, TrendForce Corp.

Paper Title:

How AI impact Server Market Dynamics under the projections into 2025

Paper Abstract:

Driven by the ascent of AI, our analysis delves into the supply and demand dynamics of Server/CSP manufacturers, projecting how Server DRAM prices will respond to market pressures and interact with AI. We underscore the strategic implications for stakeholders, encompassing major supplier strategies, capacity adjustments, and growth forecasts. This presentation serves as a strategic roadmap on supply/demand, sufficiency, and ASP, providing actionable insights for navigating the complexities of the Server DRAM market in 2025 and beyond.

Author Bio:

Prior to joining TrendForce, Liu worked for four years as a semiconductor industry analyst at related industry. Liu’s research encompasses the entire Datacenter, Server DRAM, Server CPU & Related Server Supply Chain.

Jianjun (Jerome) Luo, President, Sage Microelectronics

Paper Title:

Matching the Right Technology for the Application Drives NVM Trends

Paper Abstract:

Many innovative memory devices, including PRAM, RRAM, MRAM, and FeRAM, have emerged as potential successors to flash memory, each boasting unique advantages. Nonetheless, akin to NOR and NAND flash, each device possesses inherent weaknesses that render it difficult to supplant with alternatives. Delving into the physical mechanisms of these semiconductor devices reveals opportunities for each to carve out a niche in the market. Presently, artificial intelligence is driving the development of high-performance storage solutions utilizing System-on-Chip (SoC) and chiplet technologies. These advancements integrate multiple memory devices within a single packaged module or even on a single chip (die), tailored to the distinct functionalities of each memory type. For instance, RRAM stands out as a leading embedded NVM memory, while MRAM shows promise in replacing DRAM for high-end applications.

Author Bio:

Dr. Jianjun (Jerome) Luo, founder and Chairman of Sage Microelectronics, leads a pioneering effort in providing ICs and solutions for digital storage and data security applications. With previous roles as Director of R&D at Initio Corporation in San Jose and Eastcom in China, he brings over 30 years of experience in communication and storage IC design to his leadership at Sage Micro. Dr. Luo holds a Ph.D. in semiconductor technology from Zhejiang University, a Master’s in Microelectronics from the Hangzhou Institute of Electronics Engineering, and a Bachelor’s in Electronics Engineering from Shanghai Jiaotong University.

Jonathan Chou, Product Marketing Manager, Silicon Motion

Paper Title:

AI Influence on SSD Markets in Asia

Paper Abstract:

Since ChatGPT, the development speed of various AI technologies has been astonishing. Fields that previously took years to see progress have experienced rapid advancements with the support of AI. We can expect the emergence of generative imagery to bring about a greater demand for storage, particularly for high-speed and high-capacity portable SSDs. We will explore the current applications of portable SSDs and the overall market landscape, and provide some insights into the localization of portable SSDs in the Asian region.

Author Bio:

Jonathan Chou is a seasoned professional in the semiconductor industry, specializing in marketing analysis, product planning, and USB SSD products. With a decade of expertise, Jonathan excels in leading OEM projects and product marketing strategies within IC design houses. He is adept at product design-in, design-win management, and cultivating strong client relationships, with a keen focus on driving innovation in the USB SSD domain through collaboration with NAND vendors and SSD module manufacturers.

Paper Session Description:

In the ever-evolving landscape of the Server market, the impact of AI cannot be overstated. Our analysis dives deep into the dynamic interplay between AI and Server/CSP manufacturers, forecasting how Server DRAM prices will ebb and flow in response to market forces. With a laser focus on strategic implications, we outline supplier strategies, capacity adjustments, and growth forecasts that will shape the Server DRAM market in 2025 and beyond. This strategic roadmap is essential for stakeholders looking to navigate the complexities of AI's influence on the Server market with confidence and clarity. The rise of AI technologies, spearheaded by advancements like ChatGPT, has revolutionized the SSD markets in Asia at an unprecedented pace. As generative imagery continues to drive demand for high-speed, high-capacity portable SSDs, we anticipate a surge in uptake across the region. Our analysis delves into the current applications of portable SSDs, offering insights into market trends and localization strategies tailored for the Asian market. As the SSD landscape continues to evolve in the wake of AI innovation, stakeholders can leverage these insights to capitalize on emerging opportunities and stay ahead of the curve.

PRO CLDS-202-1: Cloud Software

Ballroom B, Floor 1

Track: Cloud Storage and Applications

Organizer:

Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft

Paper Presenters:

Dmitry Livshits, CEO, Xinnor

Paper Title:

Distributed Erasure Coding for NVMe SSDs in a Virtualized Cloud Infrastructure

Author Bio:

Dmitry is the Chief Executive Officer at Xinnor. Dmitrii was deeply involved in mathematical researches and product development for last 15 years. He received his MS degree in Computer Science in 1998, PhD in mathematics in 2002 and graduated Harvard Business School in General Management Program in 2012.

Sujit Somandepalli, Principal Storage Solutions Enginee, Micron Technology

Paper Title:

Quantifying Power Efficiency with Real Workloads in the Data Center

Paper Abstract:

Measuring power consumption from various parts of a server or storage system helps with planning and designing efficient data centers. In this talk we cover different methodologies to measure power consumption from an data center SSD and show the impact of measuring power efficiencies on various applications with standard application benchmarks. These impacts further multiply significantly in hyperscale data centers. We will also explore the need for self-monitoring this information on SSDs and how it can be implemented at scale.

Author Bio:

Sujit is a Principal Engineer at Micron Technology, working on application performance and data analysis for Enterprise SSDs since 2015. He has previously worked in storage solutions at Dell and as a software engineer at Qualcomm. He has a M.S in Computer Science from North Carolina State University.

Wojciech Malikowski, Software Engineer, Solidigm

Paper Title:

Cloud Storage Acceleration Layer (CSAL) using append cache

Paper Abstract:

Cloud Storage Acceleration Layer (CSAL) - Cache Mode introduces a novel approach to storage software cache, specifically designed to work with NAND media as a cache device. The invention addresses the technical problems of write amplification factor (WAF), cache fragmentation, higher cache lookup latency, and lack of user IO atomicity, which are common in modern storage deployments. The invention's advantages include no random workload to the cache device, no WAF, no cache fragmentation, faster data lookup procedure. The invention also leverages the append-only access pattern to the cache device and the fact that cache is not fragmented, so the cache allocation for bigger IOs is done in a contiguous manner. This allows to code the mapping information in the one hash item for a bigger IO. The results show that the invented cache is 80 times faster than the regular cache in terms of cache lookup time, and has 30% less WAF than the regular cache. This results in better Quality of Service (QoS) and performance. In summary, the invention provides a more efficient and effective approach to storage software cache, offering significant improvements in performance and QoS.

Author Bio:

Wojciech is an experienced Software Engineer and Technical Leader. He has over fifteen years of professional practice in software development in all phases including designing, architecting, implementation, testing, publishing, and supporting. For the last ten years focused on data-storage technologies. He has experience in storage drivers for a variety of technologies like persistent memory, RAID, and VMD. He is a funder of the FTL (flash translation layer) library in SPDK (storage performance development kit) which is the backbone of CSAL (cloud storage acceleration layer) solution software. His area of expertise is focused on WAF (write amplification factor) optimization techniques and caching mechanisms. He has a master's degree in electronics and telecommunication from the Wrocław University of Technology.

Dan Helmick, NVMe SSD Interface Architect, Samsung Electronics

Paper Title:

SSD Implementation of Live Migration

Paper Abstract:

PCIe® Infrastructure for Live Migration (LM) is a new NVM Express® (NVMeTM) feature developed with strong inputs from SSD customers, Google and Microsoft. Live Migration is a capability generally discussed in the context of moving a Virtual Machine (VM) from one running system to another while that VM is running or live. LM as standardized in NVMe is a host managed and controlled capability. The new standard enables the removal of the host abstraction and virtualization layers, and the VM is provided more direct access to its stored data. However, hosts depend on a compliant and reliable implementation from an SSD. One example concern point includes the ordering expectations of migration queue entry insertion and completion queue entry insertion from the drive. Race conditions for these multiple PCIe transactions across a complex host system must be met by all parties for interoperability. This presentation will discuss several highlighted points of concern during SSD implementation. Further NVMe-oF systems may have different preferences on implemented capabilities in comparison to PCIe attached SSDs, and several example differences will be provided.

Author Bio:

Dan is a Principal Architect focusing on future generation NVMe SSDs for Samsung Semiconductor. A strong background in HDD Control Systems has folded into performance FW in SSDs and future product architectures for storage products of several different medias. Dan has worked closely with customers to understand future requirements, develop industry leading standards to achieve those requirements, and design the product feature for servicing the new standardized feature. He has been a primary SSD Architect shaping features such as Zoned Namespaces (ZNS), Flexible Data Placement (FDP), Live Migration (LM), Quality of Service (QoS), and many more industry leading features.

Paper Session Description:

Distributed Erasure Coding for NVMe SSDs in a Virtualized Cloud Infrastructure introduces a new approach to storage software cache, addressing common technical problems such as write amplification factor and cache fragmentation. Cloud Storage Acceleration Layer (CSAL) using append cache offers advantages such as faster data lookup and reduced WAF. Quantifying Power Efficiency with Real Workloads in the Data Center discusses methodologies for measuring power consumption in data centers to improve efficiency. SSD Implementation of Live Migration explores the PCIe infrastructure for live migration, emphasizing the need for reliable and compliant SSD implementations to meet the standards set by NVMe. The presentation highlights concerns and differences in implementation for NVMe-oF systems

PRO COMP-202-1: Computational Storage Futures NEW

Ballroom G, Floor 1

Track: Computational Storage

Organizer:

Scott Shadley, Strategic Planner, Solidigm

Paper Presenters:

Nilesh Shah, VP, Business Development, ZeroPoint Technologies

Paper Title:

Exploring Innovations in Storage & Memory Compression Technologies at Hyperscale

Paper Abstract:

In the realm of Generative AI and cloud-native applications, the demand for terabytes of data at data center scale poses challenges to storage and memory hierarchies. Industry responses include process node shrink, new tiers, and innovative form factors. Computational storage/memory accelerators are explored to process data where it resides. However, scalability hurdles emerge, impacting SRAM scaling and memory bandwidth growth. New technologies like CXL memory and QLC SSDs present capacity benefits but pose challenges in latency and infrastructure. Balancing power, thermal, and cost constraints is crucial. To overcome limitations, lossless compression technology is being explored at various hierarchy levels, necessitating careful considerations in algorithmic implementation, compaction, and software compatibility. Choices between industry-standard and proprietary algorithms, operating granularities, and integration with emerging technologies like CXL memory semantic SSDs are critical. Offload accelerators are available, but decisions must consider options like processor-integrated accelerators, SmartNIC cores, and specialized FPGAs.

Author Bio:

Yann Collet is the Inventor/ creative mind behind the groundbreaking LZ4 and Zstandard compression algorithms, both recognized as open-source Industry standards. Currently serving as the Open Source Lossless Data Compression Lead at Meta, he continues to drive innovation in the field of data compression, contributing significantly to the development of open-source technologies. Nilesh currently leads Business Development at ZeroPoint Technologies where he is responsible for engaging Hyperscalers, Memory Module , controller and processor/accelerator manufacturers to develop Data Center and Smart Device solutions . He's an active member of the CXL Consortium, JEDEC, SNIA, represents the company at OCP. Previously, Nilesh developed Data Center SSD products and Computational Storage initiatives at Intel and holds several patents in this area. Nilesh runs several Meet Up Communities with upwards of 5000 active members and serves as an Advisor to several other companies in the Emerging Memory Technology IP and SoC space.

David McIntyre, Director Product Planning, Samsung Electronics

Paper Title:

Computational Storage Applications and Future Development

Paper Abstract:

Computational storage has been an ongoing evolution to provide improved performance and efficiencies within data centers. The latest advancements in CXL memory and storage tiering and in-memory compute aligns well with distributed compute applications from cloud to edge. This presentation illustrates architecture developments and application use cases that benefit from computational storage, including data analytics and database performance advantages. Specific architecture designs will be included to provide the audience with design considerations when deploying computational storage in data center infrastructures. Application development and integration from a software viewpoint will also be discussed.

Author Bio:

David McIntyre drives compute, memory and storage acceleration solutions strategy for Samsung and has recently embraced the most important field of corporate sustainability across product technology development. He has held senior management positions with IBM, AMD and Intel along with numerous Silicon Valley startups. Prior to Samsung, he consulted for Fidelity, Goldman Sachs, UBS, and Mckinsey. He is on the SNIA board of directors. David is a frequent presenter at technical conferences where he strives to bridge the gap between technical solutions, application developers and the end customer experience, for a responsible and sustainable future.

John Li, VP of Marketing and Operations, DapuStor

Paper Title:

Stream CSD: Reducing Enterprise SSD WA & Improving SS Performance

Paper Abstract:

The garbage collection (GC) process in flash-based SSDs significantly impacts both performance and lifespan due to write amplification (WA). Multi-stream SSDs segregate written pages by their lifetime similarity into different streams, thereby reducing data rewriting during GC. However, existing stream management solutions require modifications to host-side applications or kernels to embed stream ID information in IO commands. Host dependency is a major obstacle to the widespread adoption of multi-stream SSDs. In today's AI-driven era, we advocate the industry to move beyond naive host-dependent stream ID labeling methods. We propose Learned Streaming, a stream management mechanism based on in-storage content learning. Leveraging the emerging computational storage drive (CSD) architecture and an existing CSD with a hardware compressor, the StreamCSD, which employs compression ratios as data features and customizes the streaming K-means clustering method for automatic and completely host-transparent stream management, effectively handles scenarios and delivers comparable performance to host-labeling stream allocation.

Author Bio:

John is a seasoned professional with 13+ years of product and marketing experience in the storage industry. Currently the Vice President of DapuStor, he oversees product line management, market strategy, and global supply chain operations. His expertise in strategic planning and execution has been instrumental in driving the company's success.

Paper Session Description:

As data centers strive for improved performance and efficiencies, computational storage has emerged as a solution with advancements in CXL memory and in-memory compute. This session delves into architecture developments and application use cases, such as data analytics and database performance enhancements. Design considerations for deploying computational storage in data center infrastructures will be discussed, along with application development and integration from a software perspective. With the demand for terabytes of data in Generative AI and cloud-native applications, new storage and memory compression technologies are being explored. We will discuss industry responses that include process node shrink and new form factors to process data at scale. We will also examine how the impact of garbage collection on flash-based SSDs is being mitigated and more efficient approach leveraging compression ratios as data features and customized clustering methods, automatic and host-transparent stream management which can achieve improved performance without host dependencies.

Open CRER-202-1: Career Strategies Part 1

GAMR 1 (Great America Meeting Room 1), Floor 2

Track: Career Strategies

Paper Session Description:

Description Not Available

PRO CXLT-202-1: CXL Memory Pooling

Ballroom E, Floor 1

Track: CXL

Organizer + Chairperson:

Anil Godbole, Xeon CXL Strategy & Marketing Manager at Intel Corporation, Intel

Anil is Xeon CXL Strategy & Marketing Manager at Intel Corporation.

Paper Presenters:

Jianping Jiang, VP, Xconn Technologies

Paper Title:

A Solution of CXL Memory Pooling System and Performance Study

Paper Abstract:

How XConn CXL2.0 switch is used for CXL memory expansion, pooling and sharing; For the CXL1.1 based servers, a Fabric manager (FM) is the central point to manage XConn CXL switch and a memory pool (composed of a number of CXL memory devices attached to the CXL switch downstream ports). For CXL 2.0 based server host CPUs, the configuration and the fabric manager functions will be different from the prior case. We compared the FM functions in these two cases. We will present performance data such as bandwidth and latency for memory access with the use of switches vs direct attached CXL memory, these are measured data using performance benchmark testing such as MLC. A video of memory sharing will be presented to demonstrate that memory sharing is feasible with CXL2.0 though software is responsible for managing the access and maintaining data coherency. We will show a prototype hardware system with CXL switch, and a memory pooling demo configuration with multiple CXL servers, multiple CXL memory devices (memory pool) and a CXL switch. We will present a solution to support CXL memory hot plug and removal.

Author Bio:

Jianping (JP) Jiang is the VP of Business, Operation and Product at Xconn Technologies, a Silicon Valley startup pioneering CXL switch IC. At Xconn, he is in charge of CXL ecosystem partner relationship, CXL product marketing, business development, corporate strategy and operations. Before joining Xconn, JP held various leadership positions at several large-scale semiconductor companies, focusing on product planning/roadmaps, product marketing and business development. In these roles, he developed competitive and differentiated product strategies, leading to successful product lines that generate over billions of dollars revenue. JP has a Ph.D degree in computer science from the Ohio State University.

Brian Pan, General Manager, H3 Platform

Paper Title:

CXL Memory Sharing System Architecture and Solution Demo

Paper Abstract:

This is the first external CXL switch implementation for memory memory sharing among 8 hosts. The 256 lanes CXL switch will be used for host and CXL memory connections to form a composable memory cluster. The topics will be the system topology (8 hosts sharing 14 CXL memory devices), fabric management API/ GUI (what API is used by users), demo in Linux environment, performance results (the latency in different architecture), and implementation experience sharing.

Author Bio:

I am Brian Pan, CEO and founder of H3 Platform. Brian has long experience in developing the PCIe related solution by using Broadcom PCIe Gen3/ Gen4/ Gen5 switch. Brian is working with Xconn CXL 2.0 switch. He was also involved in the composable memory and GPU solution development. Besides, Brian has rich experience working with tier 1 cloud service providers and data centers to design composable solutions.

Jungmin Choi, Memory System Architect, SK hynix

Jungmin Choi is a Memory System Architect and Principal Engineer in Memory Systems Research at SK hynix. He is responsible for developing the memory system architecture for CXL disaggregated memory solution. He joined SK hynix in 2018 as a memory system architect, working on system-level architecture design for emerging memory solutions. He has a diverse background spanning memory devices to controllers with expertise in the area of CPU, GPU, DSP, FPGAs, fabric interconnect, and memory system.

Sanjay Goyal, Sr Technical Dir, Rambus

Paper Title:

Pooling, Sharing using MH-SLD vs MLD

Paper Abstract:

Memory costs are a significant percentage of server/datacenter costs. There have been multiple papers published indicating that pooling and/or sharing of memory will help reduce costs. Pooling helps with stranded memory capacity while sharing allows for less number of data hops reducing costs related to data movement. CXL 3.1 provides more than one mechanism to implement pooling and sharing namely MH-SLD and MLD. The presentation will explain why MH-SLD is better suited than MLD, at least for first generation of CXL devices. DCD features provides flexibility for dynamic allocation / deallocation of memory capacity across hosts, thus enabling a MH-SLD with DCD features to go to production faster for pooling and sharing applications.

Author Bio:

I am Senior Technical Director at Rambus. I am an architect, part of CXL product development group. I worked in storage industry for 20+ years, mostly in PMC-Sierra, now Microchip. Starting 1997, I moved into serialized memory controller space. First device developed was for OMI to DDR4, is in production.

Paper Session Description:

In the quest to reduce memory costs in server/datacenter operations, pooling and sharing of memory have emerged as viable solutions. By utilizing mechanisms like MH-SLD and MLD provided by CXL 3.1, organizations can optimize memory utilization and minimize data movement expenses. This session will examine the benefits of MH-SLD over MLD for initial CXL device deployment, particularly focusing on the efficiency of dynamic memory allocation using DCD features. Additionally, a detailed look at the implementation of a CXL memory pooling system and its performance study will be showcased, revealing insights on memory expansion, pooling, and sharing within a multi-host environment.

PRO OMEM-202-1: Memory for AI - Solutions

Ballroom C, Floor 1

Track: Other Memory Technologies

Organizer:

Dave Eggleston, Sr Business Development Manager, Microchip Technology

Paper Presenters:

Jack Guedj, CEO, Numem

Paper Title:

SmartMem-enabled MRAM for AI LLM/CNN Applications

Paper Abstract:

AI LLM demands exponential growth in high performance memory capacity. SRAM, while capable of delivering speed/latency requirements, exhibits poor power efficiency. New memory technologies such MRAM and ReRAM have to date mostly been considered as replacements for legacy non-volatile memories such as NOR Flash as the perception has been that their attributes such as write cycle time and write endurance make these devices unsuitable as an SRAM upgrade. In our presentation, Numem will demonstrate how its SmartMem IP with its patented PEP (Performance, Endurance, Power) Engine, has transformed MRAM technology by delivering remarkable improvements in write and read cycle times, and in endurance and power through advanced power management. We will showcase quantitative data showing how Numem’s NuRAM based on proven foundry MRAM process augmented by SmartMem IP can address the high performance required in AI LLM/CNN applications, while providing reduction in power, memory density and lower total cost of ownership. Our presentation will also discuss how SmartMem makes MRAM easier to deploy in volume and can be paired to other MRAM or ReRAM and even Flash to provide similar benefits.

Author Bio:

Jack was President and CEO of Tensilica since 2008 where, he transformed Tensilica into a rapidly growing company ascending to the #1 position in merchant DSP and ultimately leading to the Cadence acquisition in 2013 where he served as Corporate VP, Tensilica Products. Prior to Tensilica Jack led the spin-out of Magnum from Cirrus Logic serving as founder, president and CEO. Jack led Magnum’s growth from ground zero to leadership in Multimedia SOCs for the Professional Video Broadcast, Consumer PVR TV/Camcorder/DVD Recorder and Set Top Box markets and the acquisition of the Consumer Products Group of LSI Corporation (C Cube). Prior to Cirrus, Jack was President of Tvia, Inc., leading that company’s successful IPO in August 2000. Jack holds an MBA from the UCLA Graduate School of Management. Jack attained a MSEE from Pierre & Marie Curie Engineering School of Paris, and a doctoral degree from the University of Pierre & Marie Curie

Simone Bertolazzi, Technology and Market Analyst, Yole Intelligence

Paper Title:

Emerging Non-Volatile Memory - Technology and Market Trends

Paper Abstract:

In this presentation, I will provide an overview of emerging non-volatile memory (NVM) markets and technologies, discussing their technical maturity and their recent progress towards mass adoption in stand-alone and embedded applications. After reviewing the different NVM solutions currently available at leading semiconductor foundries/IDMs – among which MRAM, ReRAM, and PCM – I will discuss the challenges and opportunities for their adoption as embedded NVM in microcontrollers and edge-AI devices. The discussion will be supported by recent technology and market data which are part of the recent Yole’s report “Emerging Non-Volatile Memory 2024”.

Author Bio:

Geraldo Francisco De Oliveira Junior, PhD Candidate, ETH Zurich

Paper Title:

Enabling the Adoption of Data-Centric Systems: Methodologies and Workloads

Paper Abstract:

The increasing growing size of data in modern applications has led to high costs for computation in traditional systems. Moving large volumes of data between memory devices and computing elements across bandwidth-limited memory channels can consume more than 60% of the total energy in modern systems. To mitigate these costs, the processing-in-memory (PIM) paradigm moves computation closer to where the data resides. Many works from academia and industry have shown the benefits of PIM for a wide range of workloads from different domains. However, fully adopting PIM in commercial systems is still very challenging due to the lack of tools and system support for PIM architectures, which includes (i) workload characterization methodologies and benchmark suites targeting PIM architectures; (ii) frameworks that can ease the implementation of algorithms using the underlying PIM primitives; (iii) compiler support and compiler optimizations targeting PIM architectures; and (iv) operating system support for PIM-aware virtual memory. Our goal in this talk is to highlight tools and system support for PIM architectures that aim to ease the adoption of PIM in current and future systems.

Author Bio:

Geraldo F. Oliveira is a Ph.D. candidate in the Safari Research Group at ETH Zürich, working with Prof. Onur Mutlu. His current broader research interests are in computer architecture and systems, focusing on memory-centric architectures for high-performance and energy-efficient systems. In particular, his Ph.D. research focuses on taking advantage of new memory technologies to accelerate distinct classes of applications and provide system support for novel memory-centric systems. Geraldo has published several works on this topic in major conferences and journals such as HPCA, ASPLOS, ISCA, MICRO, and IEEE Micro.

Paper Session Description:

This session will discuss solutions for memory in AI, and how they address the exponential growth in high-performance memory capacity, reduce power consumption and memory density while lowering total cost of ownership. We will discuss tools and system support for processing-in-memory architectures, aiming to ease the adoption of PIM in current and future systems. Lastly, we will overview emerging non-volatile memory markets and technologies, highlighting the challenges and opportunities for mass adoption in embedded applications.

Open SPOS-202-1: SNIA: The Future of Data and Storage Technologies NEW

Ballroom A, Floor 1

Track: Sponsored Sessions

Sponsor:

SNIA

Organizer + Chairperson:

Richelle Ahlvers, Storage Technology Enablement Architect, Intel

Richelle Ahlvers serves as Vice Chair on the Board of Directors of the Storage Networking Industry Association (SNIA). Richelle has been engaged with industry standards initiatives with SNIA and DMTF for many years. She served as the SNIA Technical Council Chair and has been engaged across a breadth of technologies ranging from storage management to solid state storage, cloud, and green storage. She is currently Chair of the SNIA Storage Management Initiative. At Intel, Richelle is a Storage Technology Enablement Architect, where she promotes and drives enablement of new technologies and standards strategies. She has spent over 25 years in Enterprise Storage R&D teams in a variety of technical roles, leading the architecture, design and development of storage array software, storage management software user experience projects including mobility, developing new storage industry categories including SAN management, storage grid and cloud, and storage technology portfolio solutions.

Paper Presenters:

Jason Molgaard, Principal Storage Solutions Architect, Solidigm

Paper Title:

Computational Memory

Paper Abstract:

Computational Memory? WHAT? Don't you mean computational storage? What is this? As the lines between block and byte blur, so do the applications of technologies. In the same way computational storage works to co-locate computation with the data, computational memory works to co-locate computation with the data for memory-resident data technologies. Learn about how SNIA is working to expand its standards for computational storage to computational memory, and what programs, like the persistent memory hackathon, you can expect to see to support this work.

Author Bio:

Dave Landsman, Director of Industry Standards, Western Digital

Paper Title:

DNA Data Storage

Paper Abstract:

The rate of data generation continues to grow exponentially; thinking outside the box to solve issues related to long term data storage and archiving has led to the development of SNIA's DNA Data Storage group. This group combines both traditional storage organizations with non-traditional companies to apply DNA encoding / decoding concepts to store data. Get a high-level overview of the technology, learn the timelines, and what to expect over the next few years as this technology matures.

Author Bio:

Dave Landsman is Director of Industry Standards at Western Digital, where he manages storage standards across Western Digital’s businesses. Dave has been an active technical member in storage standards since 2008, representing SanDisk and, post-merger, Western Digital, making contributions to NVMe, PCI-SIG, JEDEC, SATA-IO, T10, T13, SNIA, SFF, and others. He is currently WD’s board representative for NVMe, SATA-IO, and the Compact Flash Association. Dave has over 35 years of experience in the technology/semiconductor industry, having spent his “first career” at Intel, and “second career” in storage, at msystems/SanDisk/WD, with brief hiatus at a startup in between. He earned a BA in computer science from the University of California, San Diego.

Eric Hibbard, CISSP, FIP, CISA, Director, Product Planning – Security, Samsung Semiconductor, Inc.

Paper Title:

Security

Paper Abstract:

Security, privacy, protection - some of the most critical areas of concern when it comes to data, storage and data transport. There are a myriad of challenges to keeping not only the data, but the compute and storage ecosystem protected and secure, and more on the horizon. Learn where SNIA contributes to developing standards-based solutions, both directly and with its partners, to help address security concerns for today's and tomorrow's ecosystems.

Author Bio:

Eric A. Hibbard is the Director, Product Planning – Security at Samsung Semiconductor, Inc. and a cybersecurity and privacy leader with extensive experience in industry and U.S. Government. He also has experience architecting and auditing information and communications technology (ICT) infrastructures and solutions involving a wide range of technologies (IoT, cloud, storage, big data, AI, smart cities, blockchain) in organizations throughout the world. Mr. Hibbard holds leadership positions in standards development organization and industry associations, including ISO/IEC, INCITS, the IEEE Computer Society, the American Bar Association (ABA), the Cloud Security Alliance (CSA), and SNIA. Hibbard is or has served in an editorship role on several international standards projects: ISO/IEC 22123 (Cloud computing – Vocabulary/Concepts/Reference Architecture), ISO/IEC 27050 (Electronic discovery), ISO/IEC 27040 (Storage security), ISO/IEC PAS 20648 (TLS for storage systems), ISO/IEC 27404 (Cybersecurity labelling framework for consumer IoT), and IEEE 1619-2018 (XTS-AES). Mr. Hibbard possesses a unique set of professional credentials that include the (ISC)2 CISSP-ISSAP, ISSMP, and ISSEP certifications; IAPP FIP, CIPP/US and CIPT certifications; ISACA CISA and CDPSE certifications; and CSA CCSK certification. He has a BS in Computer Science.

Paper Session Description:

As the world both produces and consumes more data, SNIA is investigating technologies and developing standards to support and manage the proliferation of data, and the storage infrastructure it sits in. With the rapid explosion in data density, we need much more efficient ways to store data; DNA data storage looks at mimicking the efficiency of DNA to store user-generated data. With the increase of shared memory and memory at the edge, there is a need to minimize movement of data from that disaggregated memory to the host. Computational memory investigates how to perform compute in or near that memory. While the technologies in the systems integrate increasingly complex protection technologies (ala post-quantum cryptography), data protection, privacy and security concerns continue to grow. There is still much work to do to ensure secure systems.

PRO SUST-202-1: Sustainable Data Centers and Energy Efficiency

Ballroom D, Floor 1

Track: Sustainability

Organizer:

Wayne Adams, SNIA Chairman Emeritus, SNIA

Wayne Adams has over 35 years of IT industry experience spanning business development, technical product/solution management, and partner ecosystems. Wayne has been involved in SNIA leadership roles since 2002. Wayne has served on the SNIA Board of Directors since 2003 including roles as Chair, Chair Emeritus, Treasurer in addition to a number of leadership roles for forums and initiatives, conferences, and strategic alliances. He has spoken at numerous industry forums and events. Over his career, Wayne M. Adams was a Senior Technologist and Director of Standards within the Office of the CTO at EMC, technical alliances partner manager, and a manager of product managers for its portfolio of SRM products. Prior to EMC, Wayne was responsible for product marketing and business development for several strategic software and hardware products at Digital Equipment Corporation. He started his high-tech career at Eastman Kodak as a system designer of real-time control systems. Wayne has been involved in many industry associations including serving on the DMTF Board of Directors, serving as Advisory Committee member of W3C, contributing to the Industrial Internet Consortium for IoT/big data test-beds, leadership of the Fibre Alliance, and participating with various committees within INCITS, OASIS, Cloud Security Alliance, and TheGreenGrid. Wayne holds a Bachelor of Science degree with a dual major in Computer Science and Mathematics from the University of Pittsburgh.

Paper Presenters:

Qingru Meng, Principal Engineer, Solidigm

Paper Title:

SSD Controller Scalability to PCIe Gen6 and Beyond

Paper Abstract:

As AI, cloud computing, and other high-performance computing (HPC) applications demand ever higher throughput and better latency from storage devices, NVMe SSDs have progressed from PCIe Gen3, to Gen4 and Gen5. With each generation, the bandwidth of SSDs has doubled. The energy efficiency must be improved accordingly to maintain the pace of this performance scalability. Unsurprisingly, the majority of the SSD power is consumed by NAND, the storage media. The next component drawing significant power is the SSD controller. In this report, we studied the power consumption of 7 different SSD controllers in PCIe gen4 and gen5 SSDs from 6 different vendors. There are 3 distinct groups observed based on both idle power and the incremental power efficiency. It is revealed some architectures have more advantage over the others and are better positioned for SSDs in PCIe Gen6 time frame and beyond. In summary, optimizing power consumption in SSDs remains crucial for achieving high performance while maintaining energy efficiency. The interplay between NAND, SSD controllers, and architectural choices will continue to shape the landscape of storage technology.

Author Bio:

Qingru, a seasoned professional in the field of storage, boasts extensive expertise in NOR, NAND, and 3D X-point technologies. Currently serving as a Principal Engineer within Solidigm’s System Integration group, she focuses on power and performance analysis, as well as predictive forecasting for data center SSDs. She holds a Ph.D. in electrical engineering from Duke University.

Toru Tanzawa, Professor, Waseda University

Paper Title:

NAND Flash Design for 30% Power Reduction

Paper Abstract:

Today, data centers consume over 1% of worldwide electricity, with data storage accounting for about 20% of the total power used in these data centers. Consequently, reducing power consumption in NAND Flash, which plays a key role in data storage, is imperative. The current NAND Flash memory operates with supply voltages of 3 V for peripheral circuits (VDD) and 1.2 V for IO circuits (VDDQ). During read and program verify operations, capacitively heavy 64 KB bit-lines are pre-charged from VDD at once. As a result, BL pre-charge is a primary contributor to energy dissipation. This presentation will focus on how VDDQ is utilized for BL pre-charge without impacting die size and read latency while maintaining compatibility with the existing NAND interface. This 'plug-in design' is expected to enable each NAND Flash die to reduce power consumption by 30%, contributing to the greening of data centers.

Author Bio:

Toru Tanzawa is a professor in the Graduate School of Information, Production and Systems at Waseda University. He pursues the Greening of integrated circuits and systems from a circuit design perspective. He has been engaged in research and development of memory, analog, and power circuits at Toshiba and Micron for 23 years and at Shizuoka university for seven years. Dr. Tanzawa holds 280 U.S. patents and has published 60 papers in IEEE conferences and journals. Toru Tanzawa is a Fellow of IEEE. He received the B.S. degree in physics from Saitama University, Saitama, Japan, in 1990, the M.S. degree in physics from Tohoku University, Sendai, Japan, in 1992, and the Ph.D. degree in electrical engineering from The University of Tokyo, Tokyo, Japan, in 2002.

Satvik Vyas, Strategic Marketing Manager for SSDs, KIOXIA America, Inc

Paper Title:

Achieve Significant Reduction in Data Movement by Offloading Data Scrubbing.

Paper Abstract:

Data scrubbing plays a crucial role in ensuring reliable data availability for applications. Currently, during the scrubbing process, data travels through transport channels like PCIe, SATA, or Ethernet, as well as the memory subsystem. After scrubbing, all data is discarded. If errors are detected, the host initiates data recovery. 100% of the energy spent on reading and processing this data is an overhead. By offloading data scrubbing to the entity where data resides, we can significantly reduce data movement, freeing up CPU, PCIe, and memory resources. This, combined with power-efficient hardware, contributes to lowering system power consumption and aligning with sustainability goals. We propose a novel approach leveraging existing standardized software stack with minimal new development to achieve these benefits.

Author Bio:

Satvik Vyas has held product management and product development engineer positions within the semiconductor and data storage industry for over 20 years. Satvik’s areas of expertise include; enterprise storage, cloud infrastructure, emerging memory technologies, and storage interfaces.

Paper Session Description:

In the realm of NAND Flash Design, ensuring a 30% reduction in power consumption is critical for the sustainability of data centers. In this session, we examine a number of methods to achieve this goal while maintaining compatibility with existing NAND interfaces, including plug-in designs, controller scalability, optimizing power consumption, and offloading data scrubbing.

11:00 AM to 11:30 AM

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Open Keynote 8: Micron: Data is at the Heart of AI: Micron Memory & Storage are Fueling AI Revolution

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Sponsor:

Micron Technology

Keynote Speakers:

Raj Narasimhan, Senior VP and GM, Compute & Networking Business Unit, Micron

Raj Narasimhan is senior vice president and general manager of Micron's Compute and Networking Business Unit. Narasimhan is responsible for leading Micron’s largest business, driving advances in memory products focused on high-performance computing, artificial intelligence, and cloud and client computing.

Keynote Description:

In the rapidly evolving landscape of AI, data drives our insights, decisions, and innovations. This keynote will highlight the key role that Micron storage and memory play in this dynamic ecosystem, starting with the data center's role in enabling AI. As AI applications expand into every corner of our lives, they will rapidly exceed the confines of the data center to the edge - the car, the PC, the phone, and beyond – to deliver amazing real-time user experiences. Edge devices, equipped with advanced storage and memory capabilities, are playing a crucial role in bringing AI to the real world. We will explore how Micron’s leading technologies – such as HBM3E, high-capacity DDR5 DIMMs, high-performance NVMe™ SSDs, and high-capacity SSDs – are revolutionizing data center architectures, enabling faster, more power efficient ingestion, processing and analysis of vast data volumes. Join us as we look at Micron’s memory and storage innovation from cloud to edge and explore how AI is integrating seamlessly into our lives – enriching our future.

11:30 AM to 11:40 AM

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Open Special Presentation: SuperWomen of FMS Leadership Award

Mission City Ballroom, Floor 1

Track: FMS 2024 Special Sessions

Sponsor:

Evaluator Group

Special Presentation Description:

The SuperWomen of FMS Leadership Award recognizes women who have shown outstanding leadership in the growth, development and use of flash memory and associated or related technologies and systems. The previous awards recognized Amy Fowler, VP and GM of FlashBlade Pure Storage, Amber Huffman, Intel Fellow, Calline Sanchez, IBM Vice President, Barbara Murphy, VP WekaIO and Dr. Yan Li, VP Western lDigital. This special presentation will recognize the 2024 winner.

11:40 AM to 12:10 PM

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Open Keynote 9: Silicon Motion: Energy Efficiency and Data Efficiency in the Next Cloud-to-Edge AI Era

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Sponsor:

Silicon Motion

Keynote Speakers:

Gary Adams, Associate VP of Enterprise Marketing, SMI

Gary Adams is Associate Vice President of Enterprise Marketing at Silicon Motion. He leads a focused team in defining and promoting Enterprise controllers and development platforms that accelerate High Performance, Data Center SSD development. Gary has over 20 years in providing innovative leadership for storage products and business solutions addressing market application needs. He has held various marketing and sales management positions at Microchip, Microsemi, PMC-Sierra and IDT. Gary earned a BS and MS in Electrical Engineering from California State University, Chico.

Robert Fan, Senior VP of Global Sales, Silicon Motion

Robert Fan serves as Senior VP of Global Sales and is in charge of Silicon Motion's worldwide sales, sales operations, and FAEs. He also oversees corporate marketing communications and public relations. Mr. Fan has over 30 years of sales and marketing experience and joined Silicon Motion in May 2013 and served as the President of Silicon Motion USA until 2023. Prior to Silicon Motion, Mr. Fan served in executive management roles at Spansion, IDT, Staktek, and at two venture capital-backed startups. He also spent over nine years at Intel in sales, marketing and management positions and was a chip designer earlier in his career.

Keynote Description:

Artificial Intelligence is driving the implosion of data usage. Whether data is used for training or inference, it needs to be processed, secured, and stored. For both the Cloud and the Edge, AI will require high capacity, high performance, and low power characteristics of NAND storage as well as the cost-effectiveness of QLC NAND. In the coming years, new categories of AI servers, AI PCs, and AI smartphones will drive device growth. AI servers, AI PCs, and AI Smartphones will need the high performance of PCIe Gen 5 SSDs and UFS 4.0 solutions to optimize for AI storage performance. Silicon Motion, as a leading merchant supplier of SSD controllers and solutions, will discuss the current and future SSD controller innovations to address the evolving and unique requirements in cloud storage and edge devices and introduce how our latest technology and comprehensive product portfolio drive AI innovations in flash storage.

01:10 PM to 01:40 PM

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Open Keynote 10: Phison: Unlocking AI's Potential: NAND Flash Technology Used to Mitigate Data Expansion

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Sponsor:

Phison Electronics Corp.

Keynote Speakers:

Chris Ramseyer, Director of Technical Marketing, Phison Electronics

Chris Ramseyer joined Phison in 2020 after a twenty-year career as a leading technology journalist at sites like Tom’s Hardware, TweakTown, HardOCP, and The Adrenaline Vault (Avault). He quickly rose to the role of Director of Technical Marketing and is responsible for bridging the gap between the highly technical R&D teams, corporate marketing, and the media. In 2023, Chris applied for his first patent for Link-State Thermal Throttling, a technology that increases a throttled SSDs performance by 20x.

Sebastien Jean, CTO, Phison Electronics

Sebastien Jean is the Chief Technology Officer at Phison Electronics, where he focuses on developing technology strategy and building alliances with other innovative companies. He also works closely with engineering teams to help integrate new concepts into products. With 24 years of experience and over 30 filed patents, he has established himself as a thought leader in the storage industry. Before joining Phison, he held senior technology positions at Micron, SanDisk, and Western Digital. At Phison, he helped devise an iterative technology roadmap that advances Security, AI, PCIe Gen 5, USB4, BGA NVMe, Client Gaming Drives and Enterprise High-density E1.S. He earned a BS in Computer Science at the University of Ottawa (Canada).

KS Pua, Chairman, Phison Electronics

As the original founder and CEO of Phison Electronics, Mr. Pua led the company to its first success in 2000, with the design and manufacture of the world’s first single-chip USB flash controller storage device named the “Pen Drive.” Originally from Malaysia, Mr. Pua moved to Taiwan to attend the National Chiao Tung University where he earned a Master’s Degree in Electrical, and Control Engineering. Under Mr. Pua’s executive leadership, Phison has become the largest independent NAND flash controller and storage solution provider in the world. Mr. Pua is a firm believer in giving back to the community that supported his entrepreneurship. He actively participates in Director roles at: the Schoolfellow Association of NCTU, Taiwan, the Pan Wen Yuan Foundation, and the Global Talentrepreneur Innovation and Collaboration Association.

Keynote Description:

Embark on an exclusive journey with K.S. Pua, Chairman and CEO of Phison Electronics Corp., as we unveil a new enterprise brand - Pascari. Phison enterprise emerges as a beacon of innovation within the industry, pioneering revolutionary storage technologies tailored for seamless integration into the forefront of next-generation data centers. Engineered with an unwavering commitment to efficiency, Pascari sets the standard for rapid deployment, ensuring optimal performance and operational excellence. Join us for a glimpse into the future of storage solutions. This presentation will also explore Phison's innovative utilization of NAND flash technology to effectively mitigate the challenge of exponential data expansion in AI training, particularly in developing large-language models. By harnessing the power of NAND flash, Phison empowers applications to achieve unprecedented milestones, enabling them to deliver responses from generative AI models that rival human-like capabilities.

01:40 PM to 01:50 PM

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Open Addressing Storage and Data Technology Challenges with Industry Standards

Mission City Ballroom, Floor 1

Track: FMS 2024 Special Sessions

Sponsor:

SNIA

Special Presentation Description:

Richelle Ahlvers, SNIA Vice Chair, will highlight the latest developments in standards-based technology trends in storage and data, and discuss how SNIA’s data-centric focus combined with their strong standards alliances help not only address today’s and tomorrow’s challenges, but accelerate solutions.

01:50 PM to 02:20 PM

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Open Keynote 11: Western Digital

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Sponsor:

Western Digital

Keynote Description:

Description Not Available

02:20 PM to 02:50 PM

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Open Keynote 12: KOVE: Software-Defined Memory is Here

Mission City Ballroom, Floor 1

Track: FMS 2024 Keynotes

Sponsor:

KOVE

Keynote Speakers:

Ian A. Hood, CTO/Chief Strategist, Red Hat

Ian is currently the CTO/Chief Strategist, Global Service Providers for Red Hat, the world’s leading provider of open-source technologies. Strategic and trusted advisor engaging and leading our global industry community of customers and partners, focused on building innovative cloud-native solutions that improve their business outcomes. Over his career, Ian was the chief communications design architect or deployment of many global operator and enterprise systems (e.g. Petronas Towers, DISA, Bank of Canada, CSIS, MCI, SBC, and the global Canadian embassy system in 100+ countries around the world). Ian has been recognized in the telecom industry as a diamond member of the IBM Academy, IEEE CommSoc, and is a licensed Professional Engineer in Ontario, with a B.A.Sc (Honours) in Electrical Engineering from University of Waterloo. Ian grew up in Owen Sound, just a few hours north of Toronto, in Canada, and now resides in the beautiful pacific northwest.

Thomas Zscharch, Chief Innovation Officer, SWIFT

Tom is the Chief Innovation Officer with responsibility for growing and championing SWIFT’s innovation capabilities. He joined in January 2020, and is charged with driving new growth opportunities across the company and in collaboration with the SWIFT Community and partners. Prior to joining SWIFT, he was the Chief Information Officer at CLS Group based in London where he was responsible for the technology function and for further developing the organization’s technology vision. He served on the Executive Management Committee at CLS. Prior to CLS, he was the Chief Information Officer for LCH. Clearnet, one of the world’s leading multinational clearing houses. Tom worked for more than twenty years in several investment banks including Bank of America / Merrill Lynch as Head of Rate and Currencies Technology and at Barclays Capital as Managing Director in Technology and Global Head of Equities, Prime Brokerage and Client Technology. Tom studied Computer Science and Finance from California State University, and earned an Executive MBA from TRIUM.

Dr. John Overton, CEO, KOVE

John Overton is the CEO and founder of Kove IO, Inc., responsible for introducing the world's first Software-Defined Memory offering, Kove:SDM™. Once considered impossible, Kove:SDM™ delivers infinitely scalable memory, and unleashes new Artificial Intelligence and Machine Learning capabilities while also reducing power consumption by up to 50%. In the late 1990s and early 2000s, Dr. Overton co-invented and patented pioneering technology using distributed hash tables for locality management. This breakthrough technology created unlimited scaling, and enabled the advent of cloud storage, scale-out database sharding, among other markets. While at the Open Software Foundation in the late 1980s, Dr. Overton wrote software used by approximately two-thirds of the world's workstation market. Dr. Overton has more than 65 issued patents world-wide, has peer-reviewed publications across a number of academic disciplines, and holds post-graduate and doctoral degrees from Harvard and the University of Chicago.

Keynote Description:

Software-Defined Memory (SDM) addresses the next wave of memory solutions to address the challenges of the “memory wall”. It performs like local memory, scales linearly, and works on any hardware - right now. In this talk, Kove and Red Hat will show how Software-Defined Memory technology has arrived. Red Hat will illustrate technology and operational benefits based on empirical test results of Kove:SDM™ configured on Red Hat OpenShift application platform using StressNG, Intel P- States, and standard Supermicro server hardware. Our comprehensive test data shows power savings from 12-54%, near-local CPU performance, and superior performance from remote memory compared to local memory. We’ll show real world use cases in multiple industry sectors that demonstrate Kove’s pooled memory solution Kove:SDM™ working on existing infrastructure, with no code changes. We’ll close with a leading expert from Swift discussing how they are changing the game for preventing economic crime for their customers with Kove:SDM™, where the stakes couldn’t be higher.

03:00 PM to 04:05 PM

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PRO AIML-203-1: Generative AI

Ballroom B, Floor 1

Track: AI and ML Applications

Organizer:

David McIntyre, Director Product Planning, Samsung Electronics

Paper Presenters:

Prasad Venkatachar, Solutions Director, Pliops

Paper Title:

Generative AI foundation to Real World use cases

Paper Abstract:

Generative AI, such as Open AI, -ChatGPT, Google Gemini, Olama, etc has undoubtedly changed the business and technology landscape. This talk covers the foundational elements of building a Gen AI application from Prompt Engineering, Rag (Retrieval augment Generation), Fine Tuning and Building LLM models from scratch. It also delves into real world use cases across the industry from Retail, Fintech, Insurance etc to across enterprise functions from customer support, marketing & HR. Get up to speed on generative AI with this session.

Author Bio:

Prasad Venkatachar is Sr Director Solutions & Products at Pliops. He is focused on Product strategy and leading and driving Data, Analytics & Storage solutions with partners. He has launched multiple industry-leading Data & AI/ML products & solutions collaborating with Microsoft, IBM, Oracle, Cloudera, and ISV partners to grow revenue & gain market share at Lenovo & HPE. He also served as a Microsoft Data and AI Partner Advisory Council Member and Member of Lenovo Technology Innovation. Served fortune 500 enterprise customers as SME to deliver business value outcomes for Datacenter and Cloud deployments. He has good experience and certified with Multiple Cloud (AWS/Azure/GCP/IBM) and Database (Oracle/DB2/Azure Data) and AI/ML certifications. A regular speaker in Industry Conferences: Microsoft Ignite, Oracle Open World, Developer conferences: Pass Summit, Oracle users group, Flash Memory Summit,SNIA & Gartner Conference

John Lorenz, Senior Analyst, Yole Group

Paper Title:

LLM Acceleration: Hardware and Memory Trends

Paper Abstract:

Generative AI and LLMs are pushing computational requirements exponentially higher, and the same is true of system memory and bandwidths. HBM has become the memory of choice for the flagship data center accelerators, but what about the memory configurations for the coming propagation of gen AI at the edge and on-device LLMs? In this presentation, we intend to examine the connections between LLM compute requirements and the corresponding flavors of enabling memory in the accelerator and the broader systems. Additionally, the audience will enjoy an overview of the HBM market dynamics, a segment of DRAM that is witnessing phenomenal growth in 2024.

Author Bio:

Assaf Sella, Senior Director Machine Learning R&D, KIOXIA

Assaf Sella has over 25 years of experience in leading research and development in the wireless communication, networking and storage industries. Having held senior positions in large corporations, as well as co-founding a startup company developing AI-based, remote monitoring solutions, Assaf is accomplished in driving innovation and product strategy.

Vishwas Saxena, Technologist, Firmware Engineering, Western Digital

Paper Title:

Flash Powering the Adoption of LLMs on Edge

Paper Abstract:

Large language models are central to natural language processing, delivering exceptional performance in various tasks. However, their intensive computational and memory requirements present challenges, especially for devices with limited DRAM. A Retrieval-Augmented Language Model (RALM) augments a large language model (LLM) by retrieving context-specific knowledge from an external database via vector search. This strategy facilitates impressive text generation quality even with smaller models, thus reducing computational demands by orders of magnitude. Both technologies pose a huge demand on GPU DRAM and system RAM, restricting their adoption to Edge Computing. We propose a novel approach to reduce GPU DRAM usage of LLMs (and RALMs) by one-third and CPU system RAM usage of RAG search vector by half. Our innovative architecture is a platform-independent host stack closer to LLM and RAG on a client PC that efficiently stores and loads LLM and RAG context from a Flash drive without a significant impact on model prediction quality or system throughput. We also propose a methodology to leverage the direct DMA of LLM parameters from SSD to GPU to further enhance model performance.

Author Bio:

Vishwas is Senior Technologist, Firmware Engineering at Western Digital, where he has conceptualized, architected, and lead multiple products in emerging tech areas namely Machine Learning, Security, Blockchain, Networking, Wireless e.g., WD Crypto HW Wallet, Encrypted Content Search, wireless storage Drives, Edge Analytics based Video Surveillance Systems, Semantic image retrieval, He has led Flash Firmware products e.g NVMe-based CFexpress removable cards, CFast Cards. He has more than 16 years of experience in firmware and embedded software development and almost 24 years of experience in the technology industry. He holds more than 21 Patents and Trade Secret at Western Digital He earned a Masters in Machine Learning and AI (2021) from Liverpool John Moores University, Liverpool, UK, and Bachelor’s in computer science (2000) from Netaji Subhas Institute of Technology, Delhi, India

Paper Session Description:

Generative AI has revolutionized the business and tech landscape, with Gen AI applications transforming industries like Retail, Fintech, and Insurance. This session explores the foundational elements of building a Gen AI application, from Prompt Engineering to Fine Tuning LLM models. Real world use cases in customer support, marketing, and HR will be discussed, showcasing the impact of generative AI across enterprise functions. On the hardware side, LLM acceleration presents challenges in computational and memory requirements, especially for edge computing. The session will explore innovative approaches to reduce GPU DRAM usage and system RAM, making LLMs more accessible on client PCs. Audience will also gain insights into memory trends and the booming HBM market in 2024.

Open CRER-203-1: Career Strategies Part 2

GAMR 1 (Great America Meeting Room 1), Floor 2

Track: Career Strategies

Panel Members:

Vincent Phipps, Chief Executive Officer & Owner of Communication VIP Training & Coaching, Communication VIP Training & Coaching

Vincent Phipps, is an interpersonal communication expert, that specializes in keynote speeches and interactive sessions to address the value and impact of leadership influence, conflict resolution, and public speaking skills. He is Certified Speaking Professional and in the Top 1% of the World’s Best Professional Speakers and Trainers. Vincent is also a Certified Virtual Presenter, Certified Analyst for Behavioral Assessment, and Certified for Psychological Aptitude Profile Interpreter. He has his Bachelor's degree in Speech / Language Communication and Linguistic Sciences, Master's degree in Leadership and Management, and is currently working on his Ph.D. of Communication Philosophy.

Panel Session Description:

Description Not Available

PRO CXLT-203-1: CXL Memory Tiering

Ballroom E, Floor 1

Track: CXL

Organizer + Chairperson:

Anil Godbole, Xeon CXL Strategy & Marketing Manager at Intel Corporation, Intel

Anil is Xeon CXL Strategy & Marketing Manager at Intel Corporation.

Paper Presenters:

Joergen Hansen, Sr. Technologist, Western Digital

Paper Title:

Hot Data Detection for CXL Memory

Paper Abstract:

Understanding data placement in heterogeneous memory is crucial for optimal application performance in the era of Compute Express Link (CXL). At various levels, data placement can occur, including at the application level where data can be partitioned, at the middleware level where domain-specific knowledge can be applied, and at the memory management level where page access can be tracked to estimate data temperature. In this talk, we take a closer look at how the different approaches can benefit from emerging hardware-assisted hot data detection. Using an emulated CXL Type 3 device, we examine potential performance gains for a range of applications including in-memory databases and caching.

Author Bio:

Joergen S. Hansen is a Sr. Technologist at Western Digital in the Emerging System Architectures group. His research interests include emerging memory and storage technologies, virtualization, and RDMA networking. Jorgen earned a Ph.D. in distributed systems from the University of Copenhagen. Before joining Western Digital, he was working at VMware for more than a decade.

Manzanares Adam, Senior Manager, Samsung Electronics

Paper Title:

CXL: A case study in data and control plane separation for memory

Paper Abstract:

CXL is an emerging interface that is capable of load/store access to device attached memory. In addition, CXL also supports a command-based interface for handling RAS features and controller functionality such as a performance monitoring unit. In this talk, we will cover some of the core functionality that is enabled by CXL and how it is implemented in the Linux kernel software stack. We will draw parallels to how Linux exposes other performance differentiated memory such as HBM to show that the software stacks of the future must evolve to be aware of the performance differentiation of memory as well as be aware of the separate control plane considerations.

Author Bio:

Adam Manzanares is a director at Samsung Electronics who leads the USA site of the Global Open Source Team within the memory division of Samsung. He has worked in the storage/memory industry for over a decade and focuses on the development of systems software for emerging hardware.

Divya Vijayaraghavan, Technical Lead, Intel Programmable Solutions Group

Paper Title:

Use Cases for CXL-based Active Memory Tiering and Near Memory Accelerators

Paper Abstract:

As the CXL ecosystem evolves, two prominent use cases have emerged - Active Memory Tiering and Near Memory Compute Acceleration. In the Active Memory Tiering use case, local and remote memory tiers address the challenge of limited server memory capacity, and migration of hot and cold pages between tiers dramatically improves storage and network efficiencies. Remote memory tiers are enhanced to accelerate or process data in close proximity to the memory elements in Near Memory Acceleration use cases. This presentation describes approaches utilized to implement active memory tiering and near memory acceleration and shares challenges encountered and expected performance metrics, comparing CXL-based transactions to traditional solutions using PCI Express.

Author Bio:

Divya Vijayaraghavan is a Technical Leader in Altera, formerly the Intel Programmable Solutions Group in San Jose. She has worn many hats in her career ranging from being a vertical champion and subject matter expert for UPI and CXL customer enablement and proliferation to a technical lead for FPGA acceleration solutions to a technical manager for several key customers and ecosystem partners. She has 26 granted patents and has represented Altera on industry standards committees such as the PCI-SIG. She has a BTech EE from the Indian Institute of Technology, Madras, India and a MS EE from the University of Texas at Austin.

Andy Banta, Storage Janitor, Magnition IO

Andy has over 30 years of experience in high-tech industry giants. He is currently a technology consultant for Magnition IO and regular delegate at Tech Field Day events. Previously, he worked on development teams at SCO, Sun Microsystems, VMware and NetApp-SolidFIre producing primarily storage and networking products. Andy is known for promoting simplicity and economy and has presented at numerous conferences, technology events and podcasts. Outside of high tech, Andy is involved in auto racing, auto restoration and hiking. His interests include travel, wines and food.

Paper Session Description:

In this session, we dive into the fiery world of hot data detection for CXL memory, emphasizing the importance of understanding data placement in heterogeneous memory for optimal application performance. We discuss the significance of data and control plane separation in CXL memory, highlighting its load/store access capabilities and command-based interface for RAS features. Additionally, we examine memory compression within CXL memory controllers, and touch on use cases for CXL-based active memory tiering and near memory accelerators, shedding light on the challenges and expected performance metrics in implementing these innovative approaches.

PRO OMEM-203-1: Heterogeneous Solutions for Performance

Ballroom C, Floor 1

Track: Other Memory Technologies

Organizer + Chairperson:

Dave Eggleston, Sr Business Development Manager, Microchip Technology

Paper Presenters:

Hieu Tran, Sr. Technical Fellow, Microchip Technology

Paper Title:

Analog Compute-in-Memory memBrain Technology for Edge AI/ML Acceleration

Paper Abstract:

Various hardware solutions are being proposed and researched for more efficient compute engine needed for AI/ML Accelerators. Analog compute-in-memory is most efficient in very low power and fast latency making it suitable for edge AI/ML Accelerators. memBrain technology, a ACIM technology, using proven in production floating gate SuperFlash memory technology is solution ready for market adoption now. memBrain technology utilizes precision sub threshold region in nA region allows extreme low power and wide tensor-in and tensor-out (Vector Matrix Multiplier) VMM engine to address various operations of the neural nets. memBrain architecture allows pipelining to speed up through put. The technology has been adopted by multiple customers for edge audio and video applications. Advanced future development includes memBrain 3D/2.5D and memBrain chiplet allow it to expand into the very high weight networks and to allow flexibility of the system implementations for different applications.

Author Bio:

Currently Senior Technical Fellow at Microchip Technology. Currently working in analog CIM AI accelerator, emerging memory, and advanced ESF Technolgies. Has worked in industry for over 30 years.

Igor Sharovar, Chief Technology Officer, Truememorytechnology LLC

Paper Title:

High-performance storage device, on a base of NVDIMM for embedded systems

Paper Abstract:

The fastest storage devices for embedded systems are SSDs designed on an NVMe PCIe gen3 X4 interface base. This interface could provide up to 4 GB/s bandwidth. The higher bandwidth requires adding extra PCIe lines. It would increase power consumption, system footprint, and CPU utilization to a level that makes small computer systems unusable. The company develops an NVDIMM solution that uses DDR4 or DDR5 memory interfaces for non-volatile storage that could provide bandwidth up to 40GB/s (DDR5). Such bandwidth allows designing storage devices for small systems with performance close to high-end server types SSDs. Using the proposed technical solution eliminates external buses and reduces the size of the system. It also decreases the power consumption necessary to maintain external buses. In addition, removing the software management component would also decrease the CPU utilization in the system. Because of the cache organization of the technology, the storage solution would provide sequential read and write operations to non-volatile memory with a DDR-like high-speed data rate.

Author Bio:

Igor Sharovar is a founder of Truememorytechnology and the author of patents protecting the IP of the technology on which the company works now. Igor has worked in many companies, from small startups to big enterprises, and was involved in different engineering projects. He is the author of a published book( https://www.amazon.com/-/es/Igor-Sharovar/dp/3639230914). Igor’s most relevant project experience includes developing novel SSD-PCIe bus technology in FusionIO (acquired by SanDisk) and Xilinx. During his time in FusionIO Igor worked on different company projects and got professional expertise and knowledge about flash memory and modern memory subsystems. In Xilinx, he provided a consulting service for the Hardware Accelerator team( https://www.xilinx.com/products/design-tools/acceleration-zone.html ) and was involved in research and production projects for High-Performance Computing (HPC). Igor holds an M.S. in electrical engineering from the National Technical University of Ukraine and an M.S. in computer engineering from the University of Ottawa, Canada.

Norio Chujo, Senior Researcher, Hitachi Data Systems

Paper Title:

BBCube 3D: Heterogeneous 3D Integration Using WoW/CoW for Near Memory Computing

Paper Abstract:

We propose BBCube 3D technology for near-memory computing. BBCube 3D is characterized by the use of bumpless technology to achieve the shortest and highest density TSV (Through-Silicon Via) interconnects between dies. It is constructed by vertically stacking heterogeneous xPU (CPU, GPU, etc.) chiplets and 3D DRAM wafers, employing Chip-on-Wafer and Wafer-on-Wafer technologies, respectively. BBCube 3D enables near-memory computing with the lowest power consumption, making it a potential solution for future AI and HPC applications.

Author Bio:

Norio Chujo received an M.S. degree in electrical engineering from the Musashi Institute of Technology, Tokyo, Japan, in 1989, and the Ph.D. degree in engineering from University of Tsukuba, Japan, in 2015. In 1989, he joined Hitachi Ltd., Kanagawa, Japan. He have been involved in high-speed data transmission circuit and PCB design. In 2019, he joined WOW alliance and have been involved to study architecture of 3D integration and electrical/thermal characteristics.

Mark Webb, Analyst, MKW Ventures

Paper Title:

Memory Technologies : How Chiplets Change Everything

Paper Abstract:

Presenters like us have talked about roadmaps for DRAM, NAND, and Alternative Memories MRAM, ReRAM, FeRAM, PCM for many years. We looked for replacements and the end of scaling. Chiplets, hybrid bonding, and packaging options have dramatically changed the dynamic, the costs, and the end possibilities. Comments like “SRAM/NOR doesn’t scale”, “MRAM process is not compatible”, “we cannot embed NAND or DRAM effectively” are no longer valid issues for compute solutions. We show how the roles each memory plays, and the limitations of each memory type, are completely different in this new chiplet environment. We show costs and performance characteristics for options and how these will lead to different futures for each memory type than we expected just 3 years ago.

Author Bio:

Mark Webb is principal analyst and advisor at MKW Ventures Consulting LLC. His focus areas are memory and storage technology and markets. Mark is a recognized expert in NAND, DRAM, MRAM, RRAM, and Emerging Memory technologies and costs. Mark was previously Manufacturing Director in the NVM Solutions Group at Intel Corporation from 2008-2012 responsible for all aspects of component and system manufacturing. Prior to that, Mark was Product Quality and Reliability Manager at IM Flash Technologies from 2006-2008. Mark is a frequent presenter at Flash Memory Summit and other Memory and Storage conferences.

Paper Session Description:

This session will discuss heterogeneous Solutions for Performance. Chiplets and hybrid bonding have revolutionized the landscape of memory technologies, eliminating previous limitations and opening up new possibilities We will discuss how they are paving the way for innovative solutions that surpass our expectations from just a few years ago. We will also discuss breakthroughs in analog Compute-in-Memory, providing unparalleled efficiency for edge AI/ML Accelerators, and NVDIMM solutions for embedded systems utilizing DDR-4 and DDR5 memory interfaces to deliver unparalleled bandwidth up to 40GB/s. Finally we will examine a solution for near-memory computing that optimizes interconnectvity and power efficiency.

Open SPOS-203-1: NVMe Live Migration, High Availability & Event Notification NEW

Ballroom A, Floor 1

Track: Sponsored Sessions

Sponsor:

NVM Express

Chairperson + Speaker:

Mike Allison, Sr. Director, Samsung Electronics

Mike Allison is a Sr. Director in the Samsung DSA Product Planning and Business Enablement team focusing on standards for existing and future products. He has been a participating member of NVM Express since 2016, co-author of many technical proposals, chair of the NMVe Errata Task Group, Samsung alternate for the NVMe Board of Directors, and a represents the OCP Storage Project on the OCP Steering Committee. For over 38 years, Mike has been an embedded firmware engineer and architect working on systems and simulations for laser beam recorders, fighter aircraft, graphics cards, high end servers, and is now focusing on Solid State Drives. He holds 31 patents in graphics, servers, and storage. He has earned a BSEE/CS at University of Colorado, Boulder.

Paper Presenters:

Nicolae Mogoreanu, Staff Software Engineer, Google

Nicolae Mogoreanu, aka mogo, is a Storage virtualization tech lead at Google overseeing Google Compute Engine virtual machine monitor integration with offloaded storage. Mogo joined Google in 2010 to work on the GCE VMM, specializing in distributed durable storage - Persistent Disk and then transitioned to working on VMM - offloaded storage integration.

Chaitanya Kulkarni, Director, NVIDIA

Chaitanya Kulkarni is a Director at NVIDIA.

Myron Loewen, Platform Architect in NVM Solutions Group, Intel

Paper Title:

Manageability Adds High Availability and Event Notification

Paper Abstract:

The NVMe workgroup added new features for High Availability and Asynchronous Event notifications to the NVM Express® Management Interface Specification, Revision 1.3. This session will demonstrate how multiple BMCs can manage a dual-port NVMe® Storage Device via SMBus/I2C. It will also demonstrate how BMCs can subscribe to receive asynchronous event notifications from NVMe Storage Devices to avoid costly polling.

Author Bio:

Myron Loewen has more than 30 years of hardware, firmware, and architecture experience on storage and communications products, with a strong emphasis on protocols and manageability. He has 23 patents for designs that are shipping in millions of units from employers like Solidigm, Intel, Microchip, and Norscan. Myron is on the NVMe Board of Directors and leads Solidigm’s Industry Standards team. He is married with 8 kids on a micro dairy farm in Colorado and enjoys flying.

Klaus Jensen, Staff Engineer, Samsung Electronics

Klaus Jensen is a software engineer with a background in academia. He has worked in the state-of-the-art area of High-Performance Computing, avoided users as an old school conservative UNIX sysop, taken a stint in an IT consultancy shop, written a Ph.D. thesis on tape, been involved in the OpenChannel SSD community, and recently, in the proliferation of NVMe® Flexible Data Placement. He is involved in the NVMe community as a technical proposal co-author and maintains the QEMU emulated NVMe device. At Samsung Semiconductor Denmark Research, he leads a small, dedicated team tasked with technology adoption and ecosystem enablement of emerging NVMe and PCIe® technologies.

Lee Prewitt, Principal Hardware Program Manager, Microsoft

Lee Prewitt is a Director of Cloud Hardware Storage at Microsoft with 30 years of storage industry experience ranging from Magneto-Optical to spinning rust to Flash. His former work at Microsoft has included working in the Windows and Devices Group where he was responsible for many of the components in the storage stack including File Systems, Spaces, Storport and Microsoft’s inbox miniport drivers. His responsibilities included storage devices ranging from SD and UFS in mobile to NVMe in Enterprise and Data Centers. He currently works in the Azure Hardware group where his team is responsible for future Data Center storage initiatives, specifications, and evangelization.

Paper Session Description:

NVM Express Standardization of Live Migration Panel At FMS 2023, NVM Express outlined the work being done to standardize Live Migration. That work is complete and NVM Express has ratified Tracking LBA Allocation with Granularity and PCIe Infrastructure for Live Migration. This presentation details the new capabilities included in the NVM Express (NVMe) family of specifications that allow a host to seamlessly migrate a Virtual Machine (VM) and associated resources without affecting the user experience for use in data center load balancing and system maintenance. The presentation covers the migration of namespaces, tracking modifications to VM memory during the migration, and the migration of the controller. Manageability Adds High Availability and Event Notification The NVMe-MI workgroup added new features for High Availability and Asynchronous Event notifications to the NVM Express Management Interface Specification, Revision 1.3. This session will demonstrate how multiple BMCs can manage a dual-port NVMe storage device via SMBus/I2C. It will also demonstrate how BMCs can subscribe to receive asynchronous event notifications from NVMe storage devices to avoid costly polling.

PRO SSDT-203-1: Performance Optimization & Modeling Techniques for SSDs

Ballroom F, Floor 1

Track: SSD Technology

Organizer:

Erich Haratsch, Senior Director Architecture, Marvell

Erich Haratsch is Senior Director Architecture at Marvell, where he leads the architecture definition for Bravera™ SSD controllers and other memory-based products. Prior to joining Marvell, he worked at Seagate and LSI, where he worked on Nytro and SandForce branded SSD controllers. Earlier in his career, he developed signal processing and error correction technologies for multiple generations of HDD controllers at LSI and Agere Systems. He started his career at AT&T and Lucent Bell Labs, where he worked on Gigabit Ethernet over copper, optical communications and the MPEG-4 video standard. He is the author of over 40 peer-reviewed journal and conference papers, and holds more than 200 U.S. patents. He also is a Senior Member of IEEE, and earned his MS and PhD degrees from the Technical University of Munich (Germany).

Paper Presenters:

Eelin Tseng, Director, Enterprise SSD R&D HW, Silicon Motion

Paper Title:

Multi-segment L2P Table Lookups with HW Acceleration for SSD Performance

Paper Abstract:

In SSD controller, logical block address needs to be mapped to NAND physical address through a mapping table (L2P Table). The minimum mapping table size is O(n*lg(n)), where n is total number logical or physical address numbers. To achieve the minimal mapping table size, FW based lookup consumes costly CPU cycles and reduces performance drastically when the physical address bit number is not aligned to DRAM byte boundaries. This presentation will describe algorithms for single segment L2P table and multi-segmented L2P table lookup. The algorithms are implemented in HW as a L2P acceleration engine in SSD controller. The L2P acceleration engine further optimize memory access performance by implementing a cache controller, such that memory access is in the granularity of a 64B cache line, and address collision detection to ensure atomic operation for various L2P table operations.

Author Bio:

Eelin is a Senior Director of ASIC design at Silicon motion. With extensive design and architecture experience, she has led the ASIC hardware design team for numerous years, overseeing the development and delivery of a diverse range of Application Specific NAND controller ICs. These highly differentiated products range across a diverse set of markets: Enterprise, Client, Portable SSDs compliant with USB3.2/USB4.0, as well as controllers for expandable storage flash cards and USB flash drives. Beyond her leadership in hardware design, Eelin also assumes responsibility for block-level architecture within each of these products.

Jaehoon Shim, Student, Seoul National University

Paper Title:

Empowering Storage Systems Research & Development with NVMeVirt

Paper Abstract:

Since the advent of flash memory, Solid State Drives (SSDs) have seen dramatic improvements in performance and functionality with the NVMe interface playing a central role. The NVMe interface, which connects storage devices via the PCIe bus, has evolved to support a wide range of storage devices with various functions and features including block SSDs, KV-SSDs, ZNS SSDs, and Computational Storage. This presentation introduces NVMeVirt, an open-source software that enables the emulation of various NVMe-based storage devices at the software level ([https://github.com/snu-csl/nvmevirt](https://github.com/snu-csl/nvmevirt)). With NVMeVirt, the performance analysis of real applications on new storage devices can be conducted even in the absence of a physical device. Moreover, it enables seamless implementation of new interfaces and modification of internal storage structure. Given such versatility, NVMeVirt is expected to contribute significantly to storage systems research and development.

Author Bio:

Jaehoon Shim is currently a Ph.D. candidate in the Department of Computer Science and Engineering at Seoul National University (SNU), Korea. His research focuses on storage systems, specifically on finding ways to bridge the gap between emerging applications and new hardware solutions, such as Key-Value SSDs, Ultra-Low Latency SSDs, and Computational Storage.

Gary Adams, Associate VP of Enterprise Marketing, SMI

Paper Title:

SSD IO Performance Shaping using Multiple Virtual Functions

Paper Abstract:

Performance shaping is a unified mechanism to shape read/write IO, read/write throughput and power per user configurable QoS groups in NVMe SSDs. Each user defined QoS group is managed with performance credits for read or write IOPS/ throughput); the shaping engine monitors ongoing IO /throughput for each QoS group and ensures a QOS group’s subscribed performance is achieved. In this presentation, we discuss how are a unique architecture hardware design with PerformaShape™ technology uses a shaping engine to maximize user defined performance for IO traffic among Multiple Virtual Functions. From the actual experimental data, we will demonstrate how a performance shaping engine can effectively regulate IO performance to multiple users focused on several user defined performance functions.

Author Bio:

Gary Adams is Associate Vice President of Enterprise SSD Controller and Solutions Marketing at Silicon Motion. He is passionate at defining and promoting Enterprise controllers and development platforms that accelerate Enterprise SSD solutions for Data Center. Gary has over 20 years in providing innovative leadership storage products and business solutions addressing market application needs. He has held various marketing and sales management positions at Microchip, Microsemi, PMC-Sierra and IDT. He earned a BSEE and MSEE at CSU-Chico.

Rakesh Nadig, Ph.D. Student, SAFARI Research Group at ETH Zurich

Paper Title:

Venice: Improving Solid-State Drive Parallelism via Conflict-Free Accesses

Paper Abstract:

SSD capacity and performance are continuously improving to meet the demands of modern data-intensive applications. Communication between the SSD controller and flash memory chips is a critical performance bottleneck. SSDs use a multi-channel shared bus architecture where multiple flash chips communicate with the SSD controller using a single path. As a result, path conflicts occur while serving multiple I/O requests, which significantly limits SSD parallelism. Our goal is to increase the number of paths (path diversity) between the SSD controller and flash chips to mitigate path conflicts. We propose Venice, which introduces a low-cost interconnection network between the SSD controller and flash chips that increases the path diversity and intelligently resolves path conflicts. Venice employs: 1) a simple router chip added next to each flash chip without modifying the flash chip design, 2) path reservation from SSD controller to the target flash chip for conflict-free transfer, and 3) a fully-adaptive routing algorithm to utilize the increased path diversity. Compared to a baseline SSD, Venice improves 1) performance by 2.65x, and 2) energy efficiency by 61% on average.

Author Bio:

Rakesh Nadig is a third year Ph.D. student in the SAFARI Research Group at ETH Zurich, advised by Prof. Onur Mutlu. His main research areas are storage systems, heterogeneous storage/memory systems, near-data processing and machine learning in computer architecture. Prior to joining SAFARI, Rakesh worked as a Senior Staff Engineer at Samsung Semiconductor Research Labs in India. Rakesh obtained a master’s degree in Electrical and Computer Engineering from the University of California at Irvine. Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is also a faculty member at Carnegie Mellon University, where he previously held the Strecker Early Career Professorship. His current broader research interests are in computer architecture, systems, hardware security, and bioinformatics. A variety of techniques he, along with his group and collaborators, has invented over the years have influenced industry and have been employed in commercial microprocessors and memory/storage systems. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held various product and research positions at Intel Corporation, Advanced Micro Devices, VMware, and Google. He received the IEEE Computer Society Edward J. McCluskey Technical Achievement Award, the ACM SIGARCH Maurice Wilkes Award, the inaugural IEEE Computer Society Young Computer Architect Award, the inaugural Intel Early Career Faculty Award, US National Science Foundation CAREER Award, Carnegie Mellon University Ladd Research Award, faculty partnership awards from various companies, and a healthy number of best paper or "Top Pick" paper recognitions at various computer systems, architecture, and hardware security venues. He is an ACM Fellow "for contributions to computer architecture research, especially in memory systems", IEEE Fellow for "contributions to computer architecture research and practice", and an elected member of the Academy of Europe (Academia Europaea). His computer architecture and digital logic design course lectures and materials are freely available on YouTube, and his research group makes a wide variety of software and hardware artifacts freely available online. For more information, please see his webpage at https://people.inf.ethz.ch/omutlu/.

Paper Session Description:

In the world of SSD performance enhancement, the implementation of multi-segment L2P table lookups with hardware acceleration is a game-changer. By optimizing memory access performance through L2P acceleration engines and cache controllers, the performance bottleneck caused by costly CPU cycles is effectively eliminated. Additionally, SSD IO performance shaping using multiple virtual functions enables user-defined QoS groups to achieve subscribed performance levels, maximizing IO traffic efficiency. This innovative approach empowers storage systems research and development with the introduction of NVMeVirt, a versatile tool for emulating various NVMe-based storage devices at the software level. Through the introduction of conflict-free accesses with Venice, SSD parallelism is significantly improved, leading to enhanced performance and energy efficiency.

PRO SUST-203-1: Circular Economy for Storage

Ballroom D, Floor 1

Track: Sustainability

Organizer:

Wayne Adams, SNIA Chairman Emeritus, SNIA

Paper Presenters:

David Logue, Operations Manager | Lead Data Recovery Engineer, Ontrack

Paper Title:

Complying with Evolving Modern-day Data Sanitization and Verification Standards

Paper Abstract:

With current supply issues, the rising costs of data storage, the growing cyber threat burden and risks surrounding protecting sensitive data, increased data regulations, and global circular economy & green initiatives, the redeployment of storage media would be a significant cost and resource savings. However, organizations must sanitize data entirely and verify eradication at end-of-life. Data Sanitization has become a substantial part of the data storage lifecycle process. But how can one be sure that evolving data sanitization standards such as IEEE-2883, NIST 800-88r1, and other international standards are met? Is data sanitization enough to protect against GDPR, HIPAA, PII, or PCI breaches, and what happens when there is a failure to comply? This presentation will discuss the different methods of data sanitization related to various storage media & potential hardware problems, the importance of third-party sanitization verification, and a recent OEM customer case study of how to implement and verify a sanitization process to comply with current modern-day and evolving data sanitization standards.

Author Bio:

Dave Logue is the Operations Manager and Lead Data Recovery Engineer at Ontrack Data Recovery. Dave assists customers worldwide with data recovery from failed or damaged computer systems while ensuring efficiency and quality at every stage of the data recovery process. Dave joined Ontrack in 2001 and has over 20 years of data recovery experience. Leveraging Dave's expertise, he currently leads teams whose members specialize in the remote recovery of high-end SAN and NAS storage technologies, data erasure and sanitization verification of storage media, and provides technical support to customers. Dave also works closely with Ontrack development teams to communicate client needs, build innovative tools, and create and deliver custom solutions for specific data loss needs. He is further involved with the system administration & storage teams in managing the IT infrastructure for the data recovery business. Before joining Ontrack, he held server and database administration positions with a leading healthcare company and management roles within their technical support teams. Dave received two B.A. degrees in Business Administration and Psychology from Hamline University. He also earned a J.D. from Hamline University School of Law and is licensed to practice in Minnesota. Specialties: Data Recovery, Data Sanitization and Verification, MS SQL, Oracle, Exchange, VMware, Product Management, Ransomware Recovery Dave has presented at several storage conferences, including FMS, in the past.

Jonmichael Hands, VP Storage, Chia Network

Paper Title:

Security and Longevity driving Circular Economy Solutions for Storage

Paper Abstract:

The Circular Drive Initiative (CDI) convenes global leaders in digital storage, data centers, and blockchain to promote the secure reuse of storage hardware. By implementing Cradle to Cradle and Circular Economy principles, CDI aims to revolutionize the ICT industry's approach to data management. This initiative focuses on creating systems that facilitate and ensure the secure and efficient reuse of data storage devices, setting a foundation for sustainable practices that reduce e-waste and environmental impact. In alignment with these principles, the OCP NVMe DSSD Specification introduces a series of advanced features that enhance both the security and longevity of storage devices. Key elements such as health monitoring, telemetry, error reporting, log pages, and improved reliability are central to extending the usable life of storage solutions. OCP has three new programs that impact data security and storage reuse, OCP S.A.F.E, OCP L.O.C.K, and Caliptra that ensure the trust is met for security to enable storage reuse.

Author Bio:

Shruti Sethi, Sr. PM, Microsoft

Paper Title:

DNA Data Storage System Interoperability

Paper Abstract:

The Global Storage market is growing at a CAGR of 17.8% between 2024-30 (Ref: Fortune Business Insights). While current storage technologies are still satisfying the current capacity needs, the explosive growth in the digitization of information has warranted research and analysis into new futuristic media, such as molecular/DNA storage, that can scale to large capacity with much lower carbon impact. In this session, we will present a concept of an end-to-end DNA Data Storage System that can function independently, is integrated with automation, and can be deployed at scale. We will describe a) the building blocks of a DNA Data Storage System; b) the abstract interface model between the functional blocks in an end-to-end system c) selecting and configuring DNA equipment blocks (codec, write, store, retrieve, read) when designing such an end-to-end system; and d) the power, liquid plumbing, waste management and other resources/support required by such a system. The main takeaway of this session is to describe a conceptual storage system that can be built using the DNA equipment blocks and how interoperability could be achieved for its real life application.

Author Bio:

Shruti Sethi is a passionate professional having a deep experience in multiple technological aspects of computing and storage systems. She has 11+ years of industry experience working extensively on Graphics power management, workload management, setting performance targets and Data Center storage hardware. She is currently most vested in the intersection of Data Center Technology and Sustainability, driving the next wave of initiatives in this domain for AZURE STORAGE PLATFORMs. She holds an MS degree in Computer Engineering from Georgia Institute of Technology and an MBA from University of California, Berkeley.

Paper Session Description:

In a world where data is king, complying with evolving modern-day data sanitization and verification standards is crucial. With the growing cyber threats and regulations surrounding data protection, organizations must ensure complete data sanitization and verification to avoid costly breaches. This session will explore various methods of data sanitization for different storage media, the importance of third-party verification, and a real OEM case study on implementing and verifying a sanitization process. We will look at new futuristic storage solutions like a DNA data storage system. We will also discuss the Circular Drive Initiative (CDI) and its approach to data management in the ICT industry. Finally we will explore OCP's programs like S.A.F.E, L.O.C.K, and Caliptra that ensure data security and trust for enabling storage reuse. Join the movement towards sustainable practices that reduce e-waste and environmental impact while maintaining data security and longevity.

PRO TEST-203-1: Testing NVMe Devices

Track: Testing and Performance

Organizer:

Christopher Cox, Fellow, AMD

Christopher Cox is a Fellow at AMD. Previously, he is the Vice President of Technology at Montage Technology. Prior to joining Montage, he was with Intel for over 21 years focused primarily on Memory Architecture with previous time at 3Dfx and AMD. Cox is currently the JEDEC JC42 (All Memories) Committee Chair, the CXL Consortium’s DRAM Subcommittee Chair and is on the Board of Directors for JEDEC and RangerRoad.org (a non-profit disabled veterans’ organization). He has been in the semiconductor industry for about 30 years, including some time in the U.S. Air Force. He holds over 170 issued and pending patents.

Paper Presenters:

Swati Chawdhary, Senior Manager, Samsung Electronics

Paper Title:

FabTest - An NVMe/NVMe-oF Compliance Test Platform

Paper Abstract:

NVMe over fabrics technology is gaining momentum and getting more traction in data centers, resulting in various type of NVMe/NVMe-oF products being deployed. Once in market, these products will be utilized in many NVMe-oF environments, from various vendors. Today NVMe/NVMe-oF Compliance suits available in the market are proprietary and very expensive. In this talk, we will introduce Fab Test - a python based Fabric compliance framework that can be easily pluggable to any other standard framework. We will be talking about the framework design and its features. The framework currently supports all mandatory requirements defined by NVMe/NVMe-oF specification and support for OCP Datacenter NVMe SSD is being added. Some of the salient features include - - Simple cli interface - Support for NVMe Base(1.4), NVMe-oF(1.1a) over RDMA(RoCE) and TCP - NVMe Device emulation - Test analysis by Wireshark packet capture and tracing - Error Injection - Performance Tests with various data patterns

Author Bio:

Swati Chawdhary is a Senior Manager at Samsung Semiconductor India Research.

Kiran Bhat, Product Marketing Engineer, Solidigm

Paper Title:

Quantifying the value of NVMe SSD in all stages of the AI data pipeline

Paper Abstract:

High density Storage is becoming a critical requirement for efficient XPU utilization in AI and ML application as the dataset is exploding and model sizes are growing several magnitudes beyond what memory can hold. So, optimizing SSD storage for AI and ML is becoming paramount. To optimize SSD for AI and ML applications requires understanding of the AI and ML Pipeline and workload and data characteristics of each stage of the pipeline. The class covers AI and ML pipeline and characteristics of each phase of the pipeline and workloads available for AI and ML and used by Solidigm to optimize our SSD for performance advantage in AI and ML applications.

Author Bio:

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Aldo Cometti, Strategic Advisor, NplusT

Paper Title:

Reliability Testing of Emerging NVMs - How to Shorten Time-To-Result

Paper Abstract:

Measuring reliability, endurance, and understanding its characteristics over lifetime and stress for emerging non-volatile memory technologies is becoming increasingly challenging, especially when considering the extremely high endurance and ultra-fast memory operations. In our presentation, we address the methodologies, equipment architecture, and critical instrumentations for the different NVM technology stages, from memory device development, through mini-arrays and polymorphic computational structures, until full array, final product engineering. We demonstrate how the solutions and results achieved are critical to shorten time-to-results and help obtaining high-quality technology data in a very reasonable time.

Author Bio:

Aldo has 30+ years of experience in the semiconductor and storage industry, has an MSEE from the Polytechnic Institute of Milan, holds 18 patents and author of numerous publications. Aldo resides in San Diego, California, and advises the CEO of NplusT in business development and product marketing strategies. Aldo was Vice President of Product in PetaIO, joined to transform the company from an SSD controller to a complete SSD drive company, shipping 10k drives per month. Before PetaIO, Aldo had several management and consultant positions in Microsoft, HGST, Western Digital, STMicroelectronics.

Carter Snay, Technical Manager, UNH-IOL

Paper Title:

Testing New Features of NVMe SSDs: Computational Storage and Beyond

Paper Abstract:

The purpose of this presentation is to discuss the process of developing new tests for the latest NVMe features. There has been a big jump in the last several years on what an NVMe SSD is capable of, starting with read/write storage, to new features such as being able to provide host addressable subsystem local memory to offload computation to the device. With new features and paradigm shifts in the industry, the testing required to validate the SSDs also has needed to change. This presentation will go over the test process of an NVMe SSD to be put on the NVMe Integrator's List and NVMe Product list, covering topics such as developing tests for the new Computational Programs Command set, how the use of memory and compute namespaces have changed what an NVMe SSD is capable of, and additional SSD compliance testing requirements.

Author Bio:

Carter Snay is the Technical Manager at the University of New Hampshire Interoperability Laboratory (UNH-IOL), focusing on Datacenter Technologies, specifically NVMe-PCIe and NVMe over Fabrics. His work at UNH-IOL began in March 2017, initially within the iSCSI testing service before transitioning to NVMe technologies in August 2017. Snay's educational background includes studying at the University of New Hampshire, where he studied Computer Science before switching to Environmental Science and is now pursuing an MBA at the Peter T. Paul College of Business and Economics.

Paper Session Description:

There are a variety of approaches to test NVMe devices. Reliability Testing of Emerging NVMs: We look at the challenge of measuring reliability, endurance, and understanding characteristics of emerging non-volatile memory technologies to shorten time-to-results while ensuring high-quality technology data. We delve into the process of developing new tests for the latest NVMe features, such as computational storage. We discuss an NVMe/NVMe-oF Compliance Test Platform offering a cost-effective, pluggable solution. We explore the importance of optimizing SSD storage for AI and ML applications by understanding the AI and ML pipeline, workload characteristics, and data requirements.

04:00 PM to 06:15 PM

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Open SuperWomen at FMS Reception

Evolution Courtyard, Floor 1

Track: Sponsored Sessions

Sponsor:

SK hynix and KIOXIA

Panel Session Description:

Join industry leaders at the SuperWomen at FMS Reception sponsored by SK hynix and KIOXIA, celebrating the successes of women in the memory and storage sector, while also advocating for increased female participation in this dynamic field. This event, and other industry activities at FMS24 foster a diverse community interested in advancing the role of women in memory and storage technology.

07:15 PM to 09:00 PM

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Open FMS 2024 Chat with the Experts

Ballroom A-D, Floor 1

Track: FMS 2024 Special Sessions

Special Event Description:

This popular annual session at FMS is your chance to network in person with industry leaders in the major technology segments influencing the future of memory and storage. Come prepared with your questions, grab some food and beverage, and find a table or tables that meet your interests!

08:30 AM to 09:35 AM

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Open BMKT-301-1: AI and Storage

GAMR 1 (Great America Meeting Room 1), Floor 2

Track: Business Strategies and Memory Markets

Organizer + Moderator:

Jean Bozman, President, Cloud Architects Advisors

Paper Presenters:

Glenn Fuller, Sr. Director of Software Engineering, Viking Technologies

Paper Title:

Right Sizing AI/ML Deployments for Small/Medium Size Enterprises

Paper Abstract:

Discusses way to optimize the deployment size of an AI/ML solution enable better access and deployment of AI/ML for small to medium size enterprise. Includes basic scalable topologies that can be deployed to reduce the acquisition cost making bespoke AI/ML deployment more accessible

Author Bio:

Glenn Fuller is the Senior Director of Software Engineering for the Viking Enterprise Solutions (VES) division of Sanmina. Glenn has led the team developing Kubernetes based solutions for storage and AI/ML applications that utilize VES's custom hardware designs. Glenn has experience developing software for public safety and manufacturing for Atos, Motorola, Boeing, Alcoa, and several startups in the US and Asia. Glenn's previous roles have included CIO, COO, IT Director, Director of Project Management, VP of Software Engineering, etc.

Jin Kim, CEO, MetisX

Paper Title:

CXL Computational Memory: Beyond Just Another CXL Memory Expander

Paper Abstract:

Jin will highlight the Memory Wall issue, a major topic in AI Data Centers, and explore CXL Computational Memory, which effectively processes large-scale data. He will describe the structure and functionality of the computational memory chip leveraging the full potential of CXL 3.0 and illustrate how it can be applied in a wide range of AI and big data applications to significantly improve the Total Cost of Ownership (TCO) in data centers.

Author Bio:

Jin Kim is the CEO of MetisX and has been developing Memory-based solutions for around 20 years. Prior to MetisX, Jin led next-gen solution architectures and SSD firmware as corporate vice president at SK Hynix, and he also worked at Samsung Electronics and SK Telecom.

Vince Chen, Director of Solution Architecture, Super Micro Computer, Inc.

Paper Title:

Unlock Your Data: Optimized Storage to Accelerate Your AI Data Pipeline

Paper Abstract:

Storage optimized for AI workloads must have high performance throughput to stage data on GPU cluster servers while also having a very large, cost-effective, capacity optimized mass storage tier to collect, process and label large data sets needed for the AI model training. In this session, Supermicro will discuss AI storage solutions using high performance flash-based storage servers and high-capacity disk storage servers with file and object storage solutions from partners such as WEKA, OSNexus, Quantum ActiveScale and Scality. We will also describe how a 25PB AI-optimized storage implementation was deployed at a leading technology manufacturing company for use in machine vision applications and how similar storage can be deployed for other applications.

Author Bio:

Vince Chen is a director of solutions architecture at Supermicro and has 20 years in the computer industry including Supermicro, Intel and Dell. He leads a team focused on implementing large scale, complex storage, networking and compute implementations which include software partners.

Frank Kung, Senior Analyst, TrendForce Corp.

Paper Title:

Exploring Generative AI's Influence on AI Servers to 2025 with HBM and CoWos

Paper Abstract:

This Presentation mainly focuses on the overall server growth driven by generative AI, covering aspects including the overall AI server market forecast and the key dynamics of the AI server supply chain, such as CoWos, ODM, HBM, etc. In addition to NVIDIA and AMD's GPU solutions, TrendForce believes that the trend worth noting in the future is the expansion of self-developed ASIC chips by large CSPs, such as AWS, Google, etc. Additionally, Chinese players are also accelerating their self-developed AI under the U.S. ban. From key AI chips specifications to technological advancements and shipment forecasts, It is estimated the CAGR of global AI server shipments, from 2022 to 2027, is expected to reach 25~30%. TrendForce will provide insights to foresee the complexities of the AI market in 2025 and beyond. Throughout, we offer insights into the evolving AI Server market, covering essential aspects like CoWoS, HBM, and more. By navigating complexities, stakeholders can strategically position themselves for transformative growth opportunities.

Author Bio:

Years of experience in industry analysis and project management, with a specialization in the server industry. Focused on areas such as cloud data centers, edge servers, and the market dynamics of the server industry—particularly HPC/AI chips, server production solutions, and memory technologies (e.g., HBM)—in response to evolving industry trends.

Jeff Yang, Director, Silicon Motion

Paper Title:

1M-IOPS Challenge: Single NAND Package Solutions for AI Applications

Paper Abstract:

This presentation addresses the formidable challenge of achieving 1M-IOPS on a single NAND Package for AI applications. We delve into the inherent noise generated by advanced 3D NAND processes and the considerations surrounding NAND, interface, package, and loading limitations. Moreover, we discuss strategies to overcome noise obstacles, enabling efficient error recovery flow and minimizing latency. Additionally, we highlight the crucial role of Flash Processing Units (FPUs) in managing workload demands. Finally, we explore methods for effectively matching AI workloads to the physical access capabilities of NAND, ensuring optimal performance in demanding AI applications.

Author Bio:

Jeff Yang is the Director of the Algorithm & Technology team at Silicon Motion, with prior experience at Realtek Inc. focusing on WiFi projects. He earned a Master of Science in Electrical Engineering from National Taiwan University and a Ph.D. in Electrical Engineering from National Tsing Hua University, Taiwan. His research expertise lies in error correcting codes, including encoding/decoding algorithms, VLSI architectures, and NAND flash characteristics analysis. Yang's current focus is on error recovery flow for NAND flash applications, showcasing his dedication to advancing flash memory technology. With a strong academic foundation and extensive industry experience, Yang is a leading figure in electrical engineering and algorithm development, particularly in the realm of NAND flash technology

Paper Session Description:

This session begins by examining the complexity of achieving high performance on a single NAND package for AI applications, addressing noise issues and latency concerns. We will explore innovative solutions to the Memory Wall problem in AI Data Centers, showcasing the benefits of CXL Computational Memory in optimizing data processing. We’ll dive into market forecasts and the growing trend of self-developed AI chips by major CSPs. Finally, we will offer insights into optimizing AI solutions for small to medium-sized enterprises, and discuss storage solutions for accelerating AI data pipelines.

Open COLD-301-1: Archive Market Trends, Applications and Technology Solutions Part 1

Ballroom B, Floor 1

Track: Cold Data

Organizer + Chairperson:

Rich Gadomski, Head of Tape Evangelism, FUJIFILM Recording Media USA

As Head of Tape Evangelism for FUJIFILM Recording Media U.S.A., Inc., Rich is responsible for driving industry awareness and end user understanding of the purpose and value proposition of modern tape technology. Rich joined Fujifilm in 2003 as Director of Product Management, Computer Products Division, where he oversaw marketing of optical, magnetic, and flash storage products.

Paper Presenters:

Alistair Symon, Vice President, Storage System Development, IBM Storage

Paper Title:

Tape Outlook

Paper Abstract:

Tape as a cold archive has seen a strong resurgence. There are many reasons including being able to meet the high security requirements in today's market, offering the lowest CO2e, and having the best total cost of ownership. With the growing amount of data to be stored, Tape is the best technology to store cold data. This presentation explores different aspects of tape storage: the technology itself, a comparison to new potential archive storage technologies, tape environmental sustainability and air gap / malware / ransomware protection. The presentation will show that Tape has made tremendous strides in technology while still having a lot of capability before hitting fundamental physics limits.

Author Bio:

Alistair is the head of development for storage systems in IBM where he leads the development of IBM storage products including All Flash Arrays, Hybrid Disk Systems and Tape. Prior to this Alistair was Vice President of Distributed Storage Development leading worldwide development of the XIV, All Flash Arrays and SVC/Storwize products. Earlier in his career, Alistair was responsible for IBM's Enterprise Storage Systems including DS8000 and Tape Systems. He has also led the development of IBM’s Storage Software products including the Spectrum Control and Spectrum Protect products that enable customers to manage and backup their data centers. He was the manager of storage development in the UK. In this role he was responsible for the development of the SAN Volume Controller, IBM’s software for virtualizing storage area networks, and the RAID engine for ESS 800 and DS8000. Alistair began his career as a software engineer at the Hursley Laboratory in the UK working on software infrastructure for the retail industry. He then moved to storage development where he has held various management positions over the last 25 years. Alistair received his BSc in Computer Science from the University of Warwick in the UK.

Dave Landsman, Director Standards Group, Western Digital

Paper Title:

No Storage Device Is Ever Lonely; HDDs Are Here To Stay

Paper Abstract:

As the volume of cold data skyrockets, the demand for archival storage solutions is increasing, and new forms of media (DNA, glass, ceramic, etc.) are being considered. Technical advances and capacity growth in all storage tiers are needed, and the HDD tier is no exception. This talk will discuss the continued vitality of the HDD business, how and why the HDD tier will continue to grow as archival data grows at massive scale, and what technical advancements will fuel this growth, from areal density improvements, to device level storage abstractions necessary to optimize IOPS/TB and latency, to library-wide container access strategies which enable optimization of diverse media types, whether integrated with or decoupled from the read/write mechanism

Author Bio:

Dave is currently a Distinguished Engineer at Western Digital, focused on storage standards. He has been a technical representative, committee chair, and/or Board member in NVMe, PCI-SIG, T10 (SAS/SCSI), T13 (ATA), SATA-IO, TCG, JEDEC, OCP, SNIA, SFF, and others, contributing to standards at all levels of the storage hierarchy (mechanical, electrical, and protocol). Dave’s focus these days is exploring archival storage media and devices to address the TCO challenges arising from the “digitization of everything”. Dave is also one of the founders of the DNA Data Storage Alliance.

John Monroe, , Further Market Research

Paper Title:

Archive Market Trends, Future Outlook, and Challenges to be Addressed

Paper Abstract:

Despite unprecedented downturns in demand during the last two years, the active installed base of enterprise data grew to 6 zettabytes at the end of 2023. We are generating more and more data and deleting less and less of the data we create, most of which, within 60 days of their creation, will become "cool" or "cold" or "frozen," with infrequent access times of minutes to days to weeks to years to decades, with little or no need for the performance of SSDs and HDDs, but with greatly expanding needs for Sustainability, Immutability, and Security (SIS), which SSDs and HDDs can neither cost effectively nor power efficiently fulfill. If the surging tide of stuff to be stored cannot be stemmed - and apparently it cannot - then new enterprise data infrastructures must not only cost less but must also consume less power to be in crucial and resilient alignment with the total availability of energy.

Author Bio:

Before founding Furthur Market Research in 2022, Monroe was a VP Analyst at Gartner for 25 years, responsible for charting the history and forecasting the future of diverse consumer and enterprise storage markets. Prior to joining Gartner in 1997, from 1980 to 1997 Monroe held various sales and marketing management positions in the distribution/VAR channels, responsible for the purchase, OEM integration, and profitable resale of HDDs, controllers, subsystems, and tape. Unlike most industry analysts, Monroe has had balance-sheet accountability for the stuff that he studies. Monroe earned a BA degree summa cum laude, Phi Beta Kappa from Amherst College in 1976 and a master’s degree in fine arts (MFA) with a merit scholarship from Columbia University in 1980.

Lee Prewitt, Principal Hardware Program Manager, Microsoft

Paper Title:

End User Perspective

Paper Abstract:

This presentation will provide an end user outlook of archive market trends, applications, and technologies.

Author Bio:

Paper Session Description:

Despite a downturn in demand, the active installed base of data continues to grow exponentially. With the majority of data becoming "cool" or "cold" within 60 days of creation, there is a pressing need for more sustainable, immutable, and secure storage solutions. This session will provide a futures outlook and challenges facing the enterprise data storage industry. Tape storage has seen a resurgence due to its security, low CO2 emissions, and cost efficiency, making it a key technology for storing cold data. HDDs remain vital in the face of increasing archival storage demand, with technical advancements driving growth and efficiency. Finally, we will discuss valuable insights from an end user perspective on the evolving archive market trends, applications, and technologies.

Open CXLT-301-1: CXL Use Cases

Ballroom E, Floor 1

Track: CXL

Paper Presenters:

Arun Bosco, Associate Director, Samsung Semiconductor India Research

Arun is currently Associate Technical Director in Samsung Semiconductor India Research. He brings over 19 years of experience in the tech industry specializing in hardware IP evaluation and system verification. In Samsung, he leads the functional validation of PCIe based NVMe SSDs and CXL based Memory controllers. Arun holds Master of Signal Processing from NTU, Singapore and Bachelor of Engineering in Electronics from Anna University, India.

Jim Handy, General Director, Objective Analysis

Paper Title:

CXL Is Exciting, But Where is It Headed?

Paper Abstract:

CXL has been a hot topic for the past few years, growing in importance as elements of GenZ, CCIX, and OpenCAPI have been absorbed into the CXL specifications. But what is CXL really for, and is the opportunity large enough to provide the necessary momentum? In this session noted industry analyst Jim Handy will present the findings of his recent CXL report to give a practical review of CXL, ranging from the fundamental problems that CXL was designed to solve, through the basics of CXL technology, to the wants and needs of prospective CXL users, capping off with a forecast of CXL adoption and its impact on future computing architectures and the semiconductor market. Attendees will gain a solid understanding of CXL and of how their companies must respond to make the most of this opportunity.

Author Bio:

Mahinder Saluja, Director, SSD Strategy, KIOXIA

Paper Title:

TCO Use Cases for CXL Attached Flash Memory.

Paper Abstract:

CXL attached flash memory can be tiered and pooled to provide orders of magnitude improvement in both price and capacity with appropriate performance. Flash over CXL presents a compelling case by seamlessly marrying the speed and reliability of Flash memory with the low latency and high-bandwidth capabilities of CXL. This symbiotic integration addresses the limitations of traditional storage solutions, especially for large memory, non-blocking AI use cases where premium compute accelerators cannot be idle while data loads from traditional storage solutions.

Author Bio:

Mahinder has 20+ years of engineering leadership in innovative storage technologies development, building teams and product delivery. Currently Mahinder heads SSD technology strategy at KIOXIA America, Inc., collaborating with industry experts. He has several pending storage related patents.

Brian Morris, Platform memory technology lead, Google

Paper Title:

Making Memories at HyperScale with CXL

Paper Abstract:

CXL (Compute Express Link) enables the addition of a new tier of memory to the memory hierarchy using type-3 devices. There are many first-generation CXL memory expansion devices in the market that enable this capability. However, due to additional controller and board costs and associated power consumption, much of the value proposition of memory tiering is diluted. We will outline a framework to enable CXL devices that can be deployed at scale and allow expanding platform memory capacity in an incremental and cost-effective fashion. We believe that this framework will be a fundamental enabler for more ambitious CXL-enabled memory architectures going forward.

Author Bio:

Brian is the platform memory technology lead at Google, driving improvements in memory cost, performance, and reliability. Prakash is a Hardware systems architect at Meta. He is Meta's representative at the CXL Board of Directors and the CXL technical task force.

Paper Session Description:

The exciting world of CXL continues to evolve, with advancements in GenZ, CCIX, and OpenCAPI being incorporated into CXL specifications. But where is this technology headed? This session will provide valuable insights on the practical applications of CXL, from its core purpose to the needs of potential users, culminating in a forecast of CXL adoption and its impact on future computing architectures. We will also explore the potential of CXL in memory expansion and flash memory applications, offering cost-effective solutions for scaling memory capacity and enhancing performance in AI use cases.

Open DSEC-301-1: AI/ML Attacks Ransomware

Ballroom D, Floor 1

Track: Data Security/Ransomware Protection

Organizer + Chairperson:

Camberley Bates, VP and Practice Lead, Futurum Group

Panel Members:

Eric Herzog, Chief Marketing Officer, Infinidat

Eric Herzog is the Chief Marketing Officer at Infinidat. Prior to joining Infinidat, Herzog was CMO and VP of Global Storage Channels at IBM Storage Solutions. His executive leadership experience also includes: CMO and Senior VP of Alliances for all-flash storage provider Violin Memory, and Senior Vice President of Product Management and Product Marketing for EMC’s Enterprise & Mid-range Systems Division.

Dejan Kocic, Sr Systems Engineer, NetApp

Dejan is a visionary and a leader whose innovative and out of box thinking have earned him the reputation of creative solutions wizard. Dejan is part of several SNIA committees, and he is regularly invited to chair conferences and to present on the latest technologies. Currently, Dejan is a Sr. Product Manager at NetApp and is leading initiatives related to AI, Ontap and Hybrid Cloud adoption, amongst other things. Dejan has many years of industry experience in Storage, Cloud, HPC, and AI technologies, and he also holds an MBA and a Masters in Information Technology degrees.

Roman Pletka, Research Staff Member, IBM Research

Roman Pletka is a senior research scientist and master inventor for storage and AI systems at the IBM Zurich Research Laboratory where he focuses on non-volatile memory technologies in storage systems. He is a frequent speaker at international conferences, has published over 20 articles and obtained more than 120 patents in managing non-volatile memories, security, scalability, and availability of distributed storage systems as well as quality-of-service in high-speed networks, active networks, and network processors. He has made presentations at many international conferences including the ACM International Conference on Systems and Storage (SYSTOR) and the Nonvolatile Memory Workshop. He earned a PhD in computer networking from ETH Zurich, Switzerland and an MS in the same subject from EPFL (Swiss Federal Institute of Technology of Lausanne) and has over 20 years experience in storage systems research.

Panel Session Description:

Yes, AI / ML is a boon to the bad guys, but it is also a lever for the good guys to implement. In this session three leading systems providers will outline how and where they are using ML/AI to thwart the cyber criminals

Open NETC-301-1: Networking Flash Based Storage for AI

Ballroom F, Floor 1

Track: Networks and Connections

Organizer + Chairperson:

Rob Davis, VP Storage Technology - Networking Business Unit, NVIDIA

Rob Davis is Vice President of Storage Technology at NVIDIA where he focuses on ways to apply their high-speed interfaces (such as 40G and 100G) to storage systems. Over the last two years he has moved NVIDIA into a leadership position in NVMe over Fabrics. As a technology leader and visionary for over 35 years, he has been a key figure in the development of an entire generation of storage networking products. Davis was previously VP/CTO at QLogic, where he drove development and marketing of Fibre Channel, Ethernet, and InfiniBand technology into new markets such as blade servers. Before joining QLogic, Davis worked at Ancor Communications, where he drove development and marketing of Fibre Channel and InfiniBand products. Davis’ areas of expertise include virtualization, Fibre Channel, InfiniBand, RoCE (remote DMA over converged Ethernet), and NVMe.

Paper Presenters:

Richard Solomon, Vice-President, PCI-SIG

Paper Title:

The PCIe® Specification: A High Bandwidth Interconnect Solution for AI and ML

Paper Abstract:

Software, hardware, and system designers face the ongoing challenge of processing and distributing data with low latency and smaller form factors over ever-increasing AI/ML models and datasets. From GPUs, CPUs, FPGAs, SoCs and more, there are many hardware platforms that require a unique interconnect solution for interoperability and future scaling needs. PCI Express® (PCIe®) technology allows developers to build accelerators regardless of the application-specific integrated circuit (ASIC) technology. By leveraging PCIe technology, developers have the flexibility to add more AI accelerators in servers or compute platforms using PCIe CEM AIC form factors for high power or M.2 for low power. This session will explore key PCIe technology benefits for AI/ML applications including its low-power modes like L0p and security features like Integrity and Data Encryption (IDE). Finally, this session will preview the upcoming PCIe 7.0 specification (targeting 128 GT/s) and how PCIe technologies continued doubling of the data rates allows AI chipset vendors and AI accelerator developers to maintain a clear path for growth today and into the future.

Author Bio:

Richard Solomon serves as Vice-President of the PCI-SIG. He is the Technical Marketing Manager for Synopsys' DesignWare PCI Express Controller IP and has been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec. Prior to joining Synopsys, Richard architected and led the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. He has served on the PCI-SIG Board of Directors for over 10 years and continues to represent Synopsys on a wide variety of PCI work groups. Richard holds a BSEE from Rice University and 26 US Patents, many of which relate to PCI technology.

CJ Newburn, HPC Lead, NVIDIA

Paper Title:

Accelerating and Securing GPU Accesses to Networked Flash Datasets

Paper Abstract:

Feeding large data to GPUs requires support for 100,000 fine-grained GPU accesses to flash based datasets that no longer fit in memory, and often need to come from across RDMA networks. New apps (GNNs, VectorDB) make fine-grained requests from every GPU thread to more data than can fit in the memory of many nodes. SCaled Accelerated Data Access (SCADA) is a new programming model that avoids painful out-of-memory errors with load/store and leverages NVMes to reduce total cost of ownership. Sharing storage among tenants makes data vulnerable to attacks from hijacked compute nodes. Moving the storage driver from untrusted compute nodes into more-secure DPUs mitigates security threats. We introduce secure storage technologies that both enhance security and retain high performance. We'll also show how a new 0-copy secure storage stack on the DPU defends traditional storage from attack.

Author Bio:

CJ is a distinguished engineer who drives high performance computing strategy and the software product roadmap in NVIDIA Compute Software, with a special focus on data center architecture and security, IO, systems, and programming models for scale.

Al Yanes, STSM, PCI-SIG

Al Yanes has served as president of the PCI-SIG since 2003 and chairman since 2006 and is a Distinguished Engineer for IBM in the Systems & Technology Division. He has 26 years of experience working with ASIC design in the I/O industry. Yanes holds 25 patents for PCI™ and other I/O technologies. Yanes is a PCI Express® technology expert for the IBM Rochester office and he is involved in I/O design for IBM's Server products. Yanes holds a B.S. in computer engineering from Rensselaer Polytechnic Institute.

Paper Session Description:

For networked flash storage in AI, high capacity, performance, and low latency are crucial to support data ingestion and training stages. This session explores key PCIe benefits for AI/ML, including low-power modes and security features like Integrity and Data Encryption. The upcoming PCIe 7.0 specification (targeting 128 GT/s) provides a clear growth path for AI chipset vendors and developers. We will discuss how the PCIe Specification offers a high bandwidth interconnect solution for AI and ML applications, allowing developers to build accelerators regardless of ASIC technology. With PCIe technology, developers can add AI accelerators in servers using various form factors for high or low power needs We will also discuss various protocols, networks, security, and scaling of storage capacity, including how accelerating GPU access to networked flash datasets requires support for fine-grained GPU accesses and secure storage technologies to prevent attacks.

Open OPSW-301-1: Linux Mainline Project Status

Ballroom C, Floor 1

Track: Open Source Software

Organizer:

Javier Gonzalez, Principal Software Engineer, Samsung Electronics

Javier Gonzalez leads Samsung Memory Solutions' Global Open-Source Team (GOST), managing a distributed team of engineers who are focused on open-source software. He is the founder and site manager for Samsung Semiconductor Denmark Research (SSDR) -- which is Samsung’s Memory Solutions first R&D center in Europe and its fifth such center worldwide. Javier’s interests are centered in the hardware/software co-design space, where systems software, hardware architecture, and open-source meet. He contributes to a wide range of open- source projects, including the evolution of the Linux Kernel. He is a regular speaker at several top industry and academic conferences each year.

Paper Presenters:

Ben Walker, Principal Software Engineer, NVIDIA

Paper Title:

An Open Software Framework For DPUs

Paper Abstract:

For large clusters storage is often networked and distributed. The clients that connect to these systems can be resource-heavy and they may require access to a private network that should not be accessible to the consumer of the storage. DPUs provide a solution to both of these problems, offloading infrastructure work from the host compute resources onto a PCIe device that presents light-weight, standardized interfaces such as NVMe or virtio-blk to the host system. These DPU devices can be extremely flexible, allowing the DPU administrator to modify any reported value and to define an I/O path with inline offloads such as encryption, checksumming, and routing to local flash or over the network. This talk will cover progress on the design of an open software framework, based on the well-established SPDK project, that allows for full customization and extension of the device, including the ability to present any BAR layout required (NVMe, virtio-blk, etc. are provided by default), a mechanism for constructing a custom I/O path including custom network protocols, and a framework to interact with local hardware accelerators.

Author Bio:

Ben is a principal engineer at NVIDIA focused on storage functionality and features for the BlueField DPU product line. His focus is currently on defining a software framework for users to extend their DPUs to present fully software-defined NVMe devices to host systems with a wide range of custom functionality, including presenting remote, network-backed devices as local NVMe devices. He's also deeply focused on targeted hardware offloads and performance for storage workloads on these devices. Ben is also a co-creator of and core maintainer for the Storage Performance Development Kit (SPDK) and an active member in the NVMe TWG.

Keith Busch, Software Engineer, Meta

Paper Title:

State of the Linux NVMe subsystems

Paper Abstract:

The Linux kernel is constantly moving, and it has been a while sense we last checked in with the state of the Linux NVMe driver. This will be a broad overview of all the most interesting features and enhancements across the various transports we support. A portion will be dedicated to utilizing recently supported high performance kernel interfaces to access the most advanced features the NVMe protocol provides, including Flexible Data Placement, application accessible metadata regions, and usage with experimental/novel command sets.

Author Bio:

I am a Linux kernel developer, with primary focus on storage related subsystems. I am maintainer of the NVMe driver, and also contribute to block and io_uring layers. I was also the original author of the QEMU nvme emulated device, and nvme-cli Linux tooling, and co-maintain these.

Jim Harris, Principal Engineer, Samsung

Paper Title:

SPDK: State of the Project

Paper Abstract:

The Storage Performance Development Kit (SPDK) continues to be a key enabler in the open source storage software landscape. This talk will focus on the the most recent work being done in SPDK, especially its focus on DPU use cases and accelerator offloads.

Author Bio:

Jim is a principal engineer in Samsung's Global Open Source Team, focused on enabling storage and memory technologies in the open source ecosystem, primarily through SPDK and the Linux kernel. Jim founded the SPDK open source project over 10 years ago and continues as one of its core maintainers. Jim has 20+ years of storage software experience in a variety of roles across Samsung and Intel. He has a BS/MS in computer science from Case Western Reserve University.

Paper Session Description:

The Storage Performance Development Kit (SPDK) remains a cornerstone of the open source storage software landscape. In this session, we will delve into the latest advancements within SPDK, with a particular emphasis on its application in DPU use cases and offloading accelerators. As the demand for distributed storage solutions grows, DPUs have emerged as a key technology for offloading infrastructure tasks and enhancing network security. We will explore the development of an open software framework, inspired by the success of SPDK, that empowers users to customize and extend DPU devices We will also examine the evolution of the Linux NVMe driver, with numerous enhancements and features being added. Join us for an insightful overview of the latest developments across different transports supported by the Linux kernel.

Open SPOS-301-1: Advancing the Chiplet Ecosystem with UCIe

Ballroom A, Floor 1

Track: Sponsored Sessions

Sponsor:

UCIe Consortium

Organizer + Presenter:

Dr. Debendra Das Sharma, UCIe Consortium Chairman and Senior Fellow at Intel Corporation, Intel

Dr. Debendra Das Sharma is an Intel Senior Fellow and co-GM of Memory and I/O Technologies in the Data Platforms and Artificial Intelligence Group at Intel Corporation. He is a leading expert on I/O subsystem and interface architecture. Das Sharma is a member of the Board of Directors for the PCI Special Interest Group (PCI-SIG) and a lead contributor to PCIe specifications since its inception. He is a co-inventor and founding member of the CXL Consortium and co-leads the CXL Technical Task Force. He co-invented the chiplet interconnect standard UCIe and is the chairman of the UCIe Consortium. Das Sharma has a bachelor’s in technology (with honors) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst. He holds 160+ US patents and 400+ patents world-wide. He is a frequent keynote speaker, plenary speaker, distinguished lecturer, invited speaker, and panelist at the IEEE Hot Interconnects, IEEE Cool Chips, IEEE 3DIC, SNIA SDC, PCI-SIG Developers Conference, CXL consortium, Open Server Summit, Open Fabrics Alliance, Flash Memory Summit, Intel Innovation, various Universities (CMU, Texas A&M, UIUC), and Intel Developer Forum. He has been awarded the Distinguished Alumnus Award from Indian Institute of Technology, Kharagpur in 2019, the IEEE Region 6 Outstanding Engineer Award in 2021, the first PCI-SIG Lifetime Contribution Award in 2022, and the IEEE Circuits and Systems Industrial Pioneer Award in 2022.

Paper Session Description:

UCIe (Universal Chiplet Interconnect Express) is an open industry that defines the interconnect offering high-bandwidth, low-latency, power-efficient, and cost-effective on-package connectivity between chiplets. The UCIe 1.1 Specification was released at FMS last year, delivering valuable improvements to the chiplet ecosystem, extending reliability mechanisms to more protocols and supporting broader usage models. This session will explore the demands and developments that brought about the need for a UCIe specification and how end-users can easily mix and match chiplet components provided by a multi-vendor ecosystem for System-on-Chip (SoC) construction. The presentation will also highlight the future of the UCIe specification.

Open TEST-301-1: Memory Device Testing

Ballroom G, Floor 1

Track: Testing and Performance

Organizer + Chairperson:

Christopher Cox, Fellow, AMD

Christopher Cox is a Fellow at AMD. Previously he was the Vice President of Technology at Montage Technology. Prior to joining Montage, he was with Intel for over 21 years focused primarily on Memory Architecture with previous time at 3Dfx and AMD. Cox is currently the JEDEC JC42 (All Memories) Committee Chair, the CXL Consortium’s DRAM Subcommittee Chair and is on the Board of Directors for JEDEC and RangerRoad.org (a non-profit disabled veterans’ organization). He has been in the semiconductor industry for about 30 years, including some time in the U.S. Air Force. He holds over 170 issued and pending patents.

Paper Presenters:

Erin Holley, Senior Member of Technical Staff, Introspect Technology

Paper Title:

Design of a 72-Channel, 40 Gbps PAM3 ATE-on-Bench Test System for GDDR7 Memories

Paper Abstract:

GDDR RAM is a class of high-performance dynamic access memory that enables extremely high bandwidth. With the seventh generation GDDR7 edition, this memory will provide up to 64 Gb of storage and more than 1 Tbps throughput. This translates to a per-pin data rate of 32 Gbps on single-ended, bidirectional pins connected between a memory controller and a memory. To enable such fast speed, GDDR7 deploys advanced signaling technologies such as PAM3, it introduces new training modes, and it adds features for checking data transmission integrity on read and write operations. The new GDDR7 specification poses test challenges that have previously not been experienced in the industry. In this presentation, we describe the design of a test solution for GDDR7 memory ICs. On one hand, the presentation will describe analog design trade offs associated with creating low-latency bidirectional PAM3 encoding on such a large scale, and on the other hand, we will describe multiple digital technologies we deployed to enable true functional testing of memory cells within a GDDR7 IC. Additionally, we will describe innovative software solutions for command scheduling and stress testing of GDDR7 memories.

Author Bio:

Erin Holley is a Senior Member of Technical Staff at Introspect Technology, a leading manufacturer of innovative test and measurement products for high speed digital applications. A graduate of McGill University in Montreal, Canada, Erin currently leads the development of Introspect's memory interface test solutions, and she is responsible for delivering and sustaining highly-parallel test instruments that operate at data rates of up to 64 Gbps. Erin is a member of the JEDEC Association, the MIPI Alliance, and PCI-SIG, and she regularly represents Introspect Technology at industry events. Her main interests are in high-speed digital design and test system architecture. She works with vendors at all stages of DDR memory interface design, translating difficult industry challenges into extremely compelling design validation tools for engineers.

Haocong Luo, PhD Student, SAFARI Research Group at ETH Zurich

Paper Title:

DRAM Simulation and Testing Infrastructures

Paper Abstract:

To improve DRAM in all aspects and overcome DRAM scaling challenges, it is critical to 1) simulate and evaluate both existing and emerging DRAM standards and designs, and 2) experimentally understand the operation and characteristics of real DRAM chips. We present two open-source software infrastructure for DRAM simulation and testing, Ramulator 2.0 and DRAM Bender. Ramulator 2.0 is a modern, modular and extensible DRAM simulator written in C++20. Its software architecture allows the rapid and agile implementation and evaluation of DRAM related research and design ideas. We showcase the modularity and extensibility of Ramulator 2.0 by implementing six different RowHammer mitigation techniques without intrusive changes to a common memory controller implementation. DRAM Bender is an FPGA-based infrastructure that enables experimental studies on DDR4 and HBM2 DRAM chips with easy-to-use C++ and Python programming interfaces. DRAM Bender allows fine-grained control of the DRAM data, commands, and timings. To demonstrate that DRAM Bender is a versatile infrastructure, we conduct three case studies, two of which lead to new observations about the DRAM RowHammer vulnerability.

Author Bio:

Haocong Luo is a PhD student in the SAFARI Research Group at ETH Zurich, advised by Prof. Onur Mutlu. His main research interests include the performance and reliability of memory systems, near (in) memory computing, and storage systems. Ataberk Olgun is a Computer Architecture researcher and a Ph.D. student in SAFARI Research Group at ETH Zürich, Switzerland, led by Prof. Onur Mutlu. His research interests lie in the intersection between computer architecture and memory system reliability and performance.

Seshu Madhavepeddy, CEO, Frore Systems

Paper Title:

How will AI accelerated computing impact memory and storage providers.

Paper Abstract:

Advancements in memory and storage technologies have followed a trend of exponential growth in capacity and performance over time, driven by innovations in materials science, manufacturing techniques, and engineering breakthroughs. This is having a huge impact on device performance, and combined with the rise of AI accelerated computing in Data Center, Edge and Mobile, is creating incredible demands on storage, memory and thermal solutions. Hear from the thermal industry's most innovative expert discuss rising to the challenges and how to ensure device performance is never throttled due to thermal limitations.

Author Bio:

Seshu Madhavapeddy is the co-founder of Frore Systems. He is a repeat entrepreneur who has scaled two startups, Spatial Wireless and Sipera Systems from founding to revenues to successful exit. Seshu has also held key leadership roles in Qualcomm, Samsung and Texas Instruments. Most recently, he was the VP/GM of Qualcomm’s ultrasonic fingerprint sensor business, which he built from demo stage into a highly successful business. Seshu has a bachelor of technology degree from the Indian Institute of Technology, Kharagpur, India, and Ph.D. in computer science from the University of Texas at Dallas.

Shyam Sharma, Software Architect, Cadence Design Systems

Paper Title:

Solving Memory Subsystem Verification Challenges for Multi-Instance Designs

Paper Abstract:

This presentation talks about the importance of the higher memory sub system level verification needs for protocol compliance of recent generation of memory sub systems using DDR like DDR5, Lpddr5 and how Cadence verification IP memory model team has come up/implemented a generic solution to describe such interconnect hierarchy in a modular and simple way. This approach defines a feature, associated grammar to capture memory sub system and implementation of handshake mechanism with triggers (like commands) to enhance individual instance DRAM model to be able to get visibility into other DRAM devices present in the design that are sharing resources like data bus, ZQ registers etc. Paper also given example of how this innovative solution has been used a number of customers to enhance their sub system level verification to the next level while verifying protocol compliance for JEDEC define specification for multi-rank memory sub systems for DDR5 and Lpddr5 based designs. This solution can extend to any kind of volatile or non volatile designs with shared resources.

Author Bio:

Shyam has done his BS in Electrical Engineering from Indian Institute of Technology, Kanpur and has over 23 years of experiences in various fields of Electronic Design Automation. His area of expertise includes processor architecture, Interconnects, storage, persistent memories and memory sub systems. He is currently working as Senior Software Architect responsible for Server/PCDDR, Low Power DRAM and other memory VIPs product solutions offered by Cadence. He has 2 Patents (filed) and several papers/posters presentation to internal/external conferences. He has worked at Mentor Graphics and Denali Design Systems before joining Cadence Design Systems in 2010.

Paper Session Description:

In this session, we explore the new era of high-performance memory device testing solutions. We’ll address the unique challenges posed by GDDR7, from analog design trade offs to digital testing technologies. We discuss two open-source software infrastructure for DRAM simulation and testing to improve DRAM in all aspects and overcome DRAM scaling challenges, Experts will discuss rising to the challenges of AI accelerated computing on storage, memory, and thermal solutions. We will also examine high memory sub system level verification needs for protocol compliance of recent generation memory subsystems and solutions that extend to volatile and non volatile designs.

09:45 AM to 10:50 AM

No search results found in this timeslot.

Open BMKT-302-1: CTO Panel

GAMR 1 (Great America Meeting Room 1), Floor 2

Track: Business Strategies and Memory Markets

Panel Members:

Greg Lavender, , Intel

Greg Lavender is executive vice president, chief technology officer (CTO) and general manager of the Software and Advanced Technology Group (SATG) at Intel Corporation. As CTO, he is responsible for driving Intel’s future technical innovation through his leadership of Intel Labs, Intel Federal LLC and Intel Information Technology (IT). He is also responsible for defining and executing Intel’s software strategy across artificial intelligence, confidential computing and the growing need for open accelerated computing to support Intel’s range of business and hardware offerings. Lavender joined Intel in June 2021 from VMware, where he served as senior vice president and CTO. He has 40 years of experience in software and hardware product engineering, cloud-scale systems architecture and engineering, and advanced research and development. Prior to his role at VMware, Lavender held executive and technology leadership positions at Citigroup, Cisco Systems and Sun Microsystems. Lavender holds a Bachelor of Science degree in computer science from the University of Georgia, and a Master of Science and Ph.D. in computer science from Virginia Tech.

Rita Wouhaybi, AI Fellow, Solidigm

Manoj Wadekar, Hardware System Technologist, Meta

Manoj has been in the Server, Storage, and Networking industry for more than 28 years. His specialities are transforming hyper-scale infrastructure to drive performance and efficiency (proven for "ebay servers". Technology Research and Innovation. Product and Technology Strategy. Product Roadmaps. Business cases. High-level architecture, and IP development. Cross-industry initiatives and collaborations.

Paul Borrill, Founder and CTO, Daedaelus

Paul Borrill is founder and CEO of DÆDÆLUS and is a leading industry expert on the foundations of resilient network and storage infrastructures. He has served as CEO of Earth Computing on Apple’s Infrastructure team, as CEO of Replicus Research, VP/CTO for VERITAS Software; VP/Chief Architect for Storage Systems at Quantum Corporation; Distinguished Engineer, Director of Architecture & Performance and Chief Scientist for IR at Sun Microsystems. Paul has a BSc. In Physics from the University of Manchester, a Ph.D in Physics from University College London, and is a graduate of the Stanford Executive Program.

Bijan Nowroozi, CTO, OCP

As the Chief Technology Officer at Open Compute Project Foundation, I am responsible for bridging the gap between technology, business, and market objectives, and driving operational excellence across the organization. I translate the leadership's vision into executable plans for teams, and establish and maintain meaningful relationships with partners, stakeholders, and customers. I am passionate about innovating and solving complex problems, and I leverage my expertise and experience to create truly leading-edge telecom hardware/software solutions that benefit the industry and society.

Steve Scott, Corporate Fellow Network & Systems Architecture at AMD, AMD

After a refreshing break, I'm excited to start my new position tomorrow as Coporate Fellow for Network and Systems Architecture at AMD. I'm hugely impressed with AMD's technology and roadmap, and have always enjoyed working with the AMD team. I'm really looking forward to joining the team and working with our cloud and systems partners to enable high-ambition AI and HPC systems!

Panel Session Description:

CTOs and their staff do not have an easy life in the flash memory industry. Things are changing rapidly, and the road ahead is almost impossible to discern or understand. So what are these people thinking currently? What do they see as basic trends that will determine the course of artificial intelligence, memory technology, and storage? And what do they think are just transient issues that will soon be forgotten? What prized techniques can they recommend for gauging the future?

PRO COLD-302-1: Archive Market Trends, Applications and Technology Solutions Part 2

Ballroom B, Floor 1

Track: Cold Data

Organizer + Chairperson:

Rich Gadomski, Head of Tape Evangelism, FUJIFILM Recording Media USA

Paper Presenters:

Shashidhar Joshi, Principal PM, Microsoft

Paper Title:

Storage Innovation for Archive/Cold Data

Paper Abstract:

Archive & Cold Storage Landscape has been evolving and growing driven by both legacy and new cloud native applications. As data ages, depending on its value, latency, and access requirements data is categorized as Active Archive or Archive/Long Term preservation. The focus of this presentation is to highlight the storage requirements for these Archive segments and how they differentiate from standard storage. We will also highlight opportunities for innovation within storage device technology, including Silica, which is an optical storage technology being developed by Microsoft.

Author Bio:

Shashidhar Joshi has over 15yrs in the storage industry spanning responsibilities ranging from operations, engineering, product management and P&L management. Shashi is currently responsible for defining the next generation of Microsoft Azure Storage Platforms and in driving future storage technology innovations.

Olivier Lauvray, CTO, Biomemory

Paper Title:

Biomemory – Pushing DNA beyond Cold Storage

Paper Abstract:

Biomemory’s implementation approach for DNA Data Storage targets use-cases and applications well-beyond Cold Storage. The presentation provides an overview of the underlying technologies and IPs enabling the implementation and industrialization of the Write, Store, Search and Read functions within the constraints of a rackable system for a scalable deployment in Data Centers.

Author Bio:

Olivier is the CTO of Biomemory, focused on bringing to market scalable enterprise data storage solutions using DNA. He has a broad experience in hardware and software, from microelectronics to enterprise storage and networking. Olivier previously held various technical and business executive positions in Europe and USA, at companies such as Motorola, Netlogic Microsystems, Encore Semi Inc. or Kalray. He holds a MS degree in Electronics & Telecom from the French National Civil Aviation Engineering School.

Steffen Hellmold, Director, Cerabyte, Inc.

Paper Title:

Accessible Permanent Data Storage

Paper Abstract:

AI is driving demand for data storage not only in-memory compute or computational storage domain but also in the archive storage domain. The challenge is to not only store data sustainably & cost-effectively but also rapidly accessible to support further learnings and insights, enabling data to be monetized. Ceramic Nano Memory is a new sustainable affordable long-term storage technology offering access within seconds. It uses inorganic ceramic nanolayers on glass sheets to reliably store information. Data can be written & read using laser or particle beam scaling from 300 nm to 3 nm bit sizes, rendering EB-class data center storage rack solutions possible. Ceramic Nano Memory enables the writing and reading of data at GB/s class with access times of less than 100 seconds. Ceramic Nano Memory is paving the way towards century-scale archive storage solutions, scaling ADC and power efficiency by 100x, and driving TCO towards $1/PB/month. Cerabyte is poised to address the density, performance, and access paradigms as well as cost & sustainability demands of data centers, offering a scaling path to the Yottabyte Era, enabling the AI Storage Dataverse.

Author Bio:

Steffen Hellmold is the Director of Cerabyte, Inc. He has more than 25 years of industry experience in product, technology, business & corporate development as well as strategy roles. He served as Senior Vice President, Business Development, Data Storage at Twist Bioscience and held executive management positions at Western Digital, Everspin, SandForce, Seagate Technology, Lexar Media/Micron, Samsung Semiconductor, SMART Modular and Fujitsu. He has been deeply engaged in various industry trade associations and standards organizations including co-founding the DNA Data Storage Alliance in 2020 as well as the USB Flash Drive Alliance, serving as their president from 2003 to 2007. He holds an Economic Electrical Engineering degree (EEE) from the Technical University of Darmstadt, Germany.

Paper Session Description:

In this new session to FMS24, we will look at archive applications and technology solutions. Ceramic nano memory is a cutting-edge storage technology revolutionizing the AI Storage Dataverse, addressing the growing demand for sustainable and cost-effective data storage solutions. Concurrently, advancements in archive/cold data storage landscape and emerging technologies like silica are paving the way for even greater storage efficiency and scalability. Biomemory, on the other hand, is pushing DNA Data Storage beyond traditional cold storage applications, revolutionizing the way data is stored and accessed in data centers.

PRO CXLT-302-1: CXL AI Implications NEW

Ballroom E, Floor 1

Track: CXL

Paper Presenters:

David McIntyre, Director Product Planning, Samsung Electronics

Paper Title:

CXL Data Centric Computing

Paper Abstract:

AI applications are confronted with a misbalance of data center infrastructure resources, thereby impacting the performance thresholds that application end users expect to achieve. Compute, memory, storage and networking resources can be optimized in architectures through CXL and data centric computing, by bringing the compute to the data, reducing the burden on host processor complexes and networks. Benefits include improved performance, resource utilization and power efficiencies, subsequently reducing the impact to data center operating costs. This presentation will introduce new architecture options enabled by CXL, illustrating the benefit of balanced resources for AI workloads.

Author Bio:

Khurram Malik, Director of Product Marketing, Marvell

Paper Title:

CXL: Closing the Memory Gap

Paper Abstract:

Compute Express Link (CXL) technology represents a transformative force in data center architectures, offering high-speed, low-latency interconnectivity that revolutionizes performance across a spectrum of computing tasks. In this presentation, I will explore pivotal use cases showcasing the profound impact of CXL in accelerating artificial intelligence (AI) workloads, enhancing high-performance computing (HPC) applications, and optimizing memory expansion and tiering strategies. CXL's bandwidth and flexibility redefine memory architectures in HPC, facilitating efficient communication between processors and memory modules for enhanced computational efficiency in scientific simulations, numerical modeling, and computational fluid dynamics. Furthermore, CXL's memory coherence capabilities are instrumental in expanding memory capacity beyond traditional limits and implementing innovative memory tiering solutions. This enables organizations to leverage larger in-memory datasets for analytics and database applications. Join me as we explore these transformative use cases into the unparalleled potential of CXL technology.

Author Bio:

Khurram Malik is director of product marketing, CXL at Marvell. In this role, he leads the CXL product portfolio and drives technology adoption for data center and enterprise customers. Prior to this, he held product and technical marketing roles for Marvell’s storage accelerator product lines in the company’s Flash BU. Previously, he served as the technical marketing manager for enterprise, data center, and client SSD product portfolio at Samsung Semiconductor Inc. Before that, he held various positions at SK Hynix Memory Solutions, Link A Media Devices Corporation, Broadcom Corporation, and Maxim Integrated Products, contributing to product definition and development. He holds a Bachelor of Science degree in Electrical Engineering from Saginaw Valley State University and a Master of Science degree in Electronic Engineering from San Jose State University.

Harry Kim, CPO, MetisX

Paper Title:

Rebalancing Memory and Computing with CXL Computational Memory

Paper Abstract:

In AI+Data systems, performance is no longer synonymous with computational power; rather, it closely aligns with memory capacity and bandwidth. Limitations in memory capacity and bandwidth severely impact the efficiency of AI+Data systems that need to store and process large volumes of data. CXL opens up new opportunities for AI Data acceleration, potentially reducing the data center tax and dramatically improving TCO.

Author Bio:

Harry Kim is the CPO and co-founder of MetisX. He is an experienced system software architect with 10yrs of SoC background. He has developed hardware and software solutions for memory, storage, and processor systems. Before he joined MetisX, he worked at SK Hynix as an SSD controller and firmware architect.

Paper Session Description:

In the world of AI and data systems, the key to unlocking peak performance lies not in sheer computational power, but in the balance of memory capacity and bandwidth. The advent of Compute Express Link (CXL) technology offers a groundbreaking solution to this challenge, ushering in a new era of data-centric computing. With CXL, data center infrastructure can be optimized for maximum efficiency, reducing the strain on processor complexes and networks. The benefits are clear: improved performance, resource utilization, and power efficiencies, ultimately leading to lower operating costs. Thios session will delve into the transformative potential of CXL technology and its ability to revolutionize memory and computing in AI and data systems.

PRO DSEC-302-1: Cryptographic Keys/Quantum Cryptography

Ballroom D, Floor 1

Track: Data Security/Ransomware Protection

Organizer + Chairperson:

Camberley Bates, VP and Practice Lead, Futurum Group

Paper Presenters:

Dan Helmick, NVMe SSD Interface Architect, Samsung Electronics

Paper Title:

SSD Implementation of KPIO

Paper Abstract:

Key Per IO (KPIO) is a new NVM Express® (NVMeTM) and Trusted Computing Group® (TCG) feature, and aspects of KPIO are enabled in both standards. KPIO enables a more dynamic usage of security keys as managed by a Host. A Host might transition security keys in an SSD with very few key slots as the workload transitions, and this enables additional end clients to use the same limited capability SSD over different time periods. Even more interesting, KPIO reduces security exposure because a Host can manage the keys possessed by a drive. In the most ideal case, data security control can be extended all the way to the end customer. This presentation will discuss some of the implementation decisions for an SSD supporting KPIO along with the example use-cases. These use-cases will help the audience understand this feature because the diversity of usage enabled by the standards might overwhelm someone new to the topic. The presentation will highlight potential Host optimal usage points and some best practices for the SSD.

Author Bio:

Dan is a Principal Architect focusing on future generation NVMe SSDs for Samsung Semiconductor. A strong background in HDD Control Systems has folded into performance FW in SSDs and future product architectures for storage products of several different medias. Dan has worked closely with customers to understand future requirements, develop industry leading standards to achieve those requirements, and design the product feature for servicing the new standardized feature. He has been the primary SSD Architect shaping features such as Zoned Namespaces (ZNS), Flexible Data Placement (FDP), Live Migration (LM), Quality of Service (QoS), and many more industry leading features.

Jeff Andersen, Staff Software Engineer, Google, LLC

Paper Title:

OCP L.O.C.K.

Paper Abstract:

OCP L.O.C.K. (Layered Open-source Cryptographic Key-management) is an initiative to build an open hardware implementation of secure cryptographic key management for NVM Express storage devices. Built on top of Caliptra, and espousing the same goals of transparency and commonality, this work will provide a strong baseline for ensuring the confidentiality of user data entrusted to hyperscalers. In this talk we explore the design of the key management block and describe critical user journeys enabled by L.O.C.K.

Author Bio:

Jeff Andersen focuses on hyperscalar platform integrity solutions at Google. He has worked on Google's in-house Titan root-of-trust chip and is now looking to apply Google's domain experience to help advance the state of attestation APIs in the wider industry.

Paper Session Description:

This session will explore some of the latest approaches for locking down devices and systems. No single approach to security is enough, especially as the finish line seems to move each time we get closer. And, we are facing advanced systems that will be able to crack the codes we have used in the past. Hear from some leading technologist on what they are doing to address the hardened systems.

PRO NETC-302-1: NVMe over Fabrics Is Everywhere

Ballroom F, Floor 1

Track: Networks and Connections

Chairperson:

John Kim, Director of Storage Marketing, NVIDIA

John KIm is Director of Storage Marketing at NVIDIA

Paper Presenters:

Orit Wasserman, Distinguished Engineer, IBM

Paper Title:

Breaking Boundaries: Expanding Ceph's Capabilities with NVMe-oF

Paper Abstract:

Join us for a technical deep dive into open-source storage and its practical application with Ceph and its new NVMe-oF target. This session aims to explore an exciting advancement that brings together Ceph, an open-source software-defined storage, and industry-standard protocols, focusing on NVMe-over-Fabrics (NVMe-oF). NVMe-oF is a widely adopted storage protocol that provides users seamless access to Ceph clusters, opening up new possibilities for efficient data storage. During this session, we will delve into the architectural decisions behind the integration with SPDK and discuss the reasons for choosing SPDK as the foundation for our NVMe-oF target. Furthermore, we will address the implementation challenges we encountered while developing the NVMe-oF target, emphasizing the critical considerations for achieving high availability, exceptional performance, and scalability. By sharing our experiences, we aim to provide valuable insights into the practical aspects of deploying an NVMe-oF target within a Ceph ecosystem.

Author Bio:

Orit is a Distinguished Engineer at IBM, specializing in Software Defined Storage (Ceph) and storage for containerized apps (OpenShift Data Foundation) as well as hybrid/multi-cloud. With a strong background as a software engineer and architect, Orit's passion lies in open-source technologies and infrastructure. Her journey at Red Hat began with Ceph Rados Gateway, a highly available distributed storage solution. She was a principal architect at Lightbits Labs, focusing on NVMe/TCP development.

Mahinder Saluja, Sr. Specialist, Outbound Marketing, KIOXIA

Paper Title:

Redefining Data Redundancy with RAID Offload

Paper Abstract:

Data redundancy solutions by nature are compute intensive and pose challenges on system resources. NVMe SSD read and write performance doubles with every PCIe generation and data center redundancy has grown to support multiple calculations per stripe. These SSD performance gains, along with a growing number of calculations, have shifted the performance bottleneck of data redundancy solutions: the host’s computational resources and memory bandwidth. KIOXIA is introducing an application-orchestrated solution to offload data redundancy computation to SSDs. This proposed offload scales out, where performance scales with the number of SSDs. The offload is extremely flexible, and can easily be adopted by existing redundancy applications. This saves CPU cores while reducing DRAM bandwidth and TCO.

Author Bio:

Mark Miquelon, Partner Alliance Director, Western Digital

Paper Title:

NVMe-oF Ethernet SSDs and HDDs Technology and Solutions for AI BaM and more

Paper Abstract:

Ethernet-attached SSDs and now HDDs are one of the most interesting developments in NVMe-over-Fabric (NVMe-oF) networked block storage. They eliminate data path bottlenecks and data center switching layers while enabling easy local storage performance scaling for new AI applications like BaM. NVIDIA and WDC will show how tomorrowâs data centers can take full advantage of this new architecture, through the integration of NVMe-oF Ethernet direct connected SSDs and HDDs. Direct benefits include much-improved TCO, higher performance, scaling and ease-of-use.

Author Bio:

Mark Miquelon is currently Director of Partner Alliances for Western Digital's Platforms business. In this role he seeks out strategic partnerships that provide additional value to customers consuming JBOD/JBOF and servers developed by Western Digital. Prior experience includes leadership roles in both engineering and product line management at Seagate, Avago, LSI, Vitesse, Symbios Logic, At&T, and NCR.

Odie Killen, VP Hardware Engineering, Viking Technologies

Paper Title:

NVMeoF Everywhere

Paper Abstract:

Discuss the push to a ubiquitous host interface scheme based on NVMeoF. This could include discussions on replacing SAS HDD infra structure with HDD based solutions with NVMeoF front ends and the resulting challenges and opportunities

Author Bio:

Paper Session Description:

Join us for a technical deep dive into the groundbreaking advancements in open-source storage with Ceph and its NVMe-oF target. This session will explore the seamless integration of Ceph clusters with industry-standard protocols like NVMe-oF, revolutionizing data storage efficiency. Delve into the architectural decisions behind this integration, learn about the implementation challenges faced, and discover the key considerations for achieving high availability and exceptional performance. Additionally, gain insights into the widespread adoption of NVMe-oF as a universal host interface scheme, the benefits of offloading data redundancy computation to SSDs, and the latest developments in Ethernet-attached SSDs and HDDs technology for AI applications and beyond. Don't miss this opportunity to expand your knowledge and push the boundaries of storage capabilities.

PRO OPSW-302-1: Databases

Ballroom C, Floor 1

Track: Open Source Software

Paper Presenters:

Brian Carrig, Sr Program manager, Microsoft

Paper Title:

Microsoft SQL Server - Memory & Flash Storage Adoptions

Paper Abstract:

Throughout the various versions of SQL Server, the product has strived to remain at the forefront of new developments in storage and memory technology. This session will provide a brief overview of the key features in the product that take advantage of these latest and prior developments, such as enhancements for persistent memory (PMEM) and Single Level Cell (SLC) flash technology. These include performance improvements to the transaction log (Write Ahead Log), extensions to the buffer pool (in-memory cache) and the ability to bypass the kernel and write directly from user space to the storage subsystem using Direct Access (DAX) enabled filesystems such as XFS, EXT4 and NTFS and byte addressable storage such as PMEM.

Author Bio:

As a Senior Program Manager on the SQL Server Enterprise team at Microsoft, I have a strong focus on Data Platform, which covers anything that can impact the performance, scalability, or data integrity of the SQL OS. With over 5 years of experience in this role, I am responsible for managing the PM aspects of server hardware, file systems, storage fabric interconnects, Remote Direct Memory (RDMA), Hyperconverged Infrastructure (HCI), virtualization, and more.

Arun George, Senior Staff Engineer, Samsung Electronics

Paper Title:

Mitigating the multi tenant challenges of CacheLib deployments using FDP

Paper Abstract:

CacheLib is an open source caching engine from Meta to build high throughput, low overhead caching services. It has the built-in ability to transparently leverage DRAM and NAND. Flexible Data Placement(FDP) using NVMe is the latest technology in the field of Data Placement in SSDs. FDP support has been upstreamed to CacheLib to mitigate the device write amplification (WAF) challenges within the SSD. This talk explains how FDP helps the CacheLib deployments in the multi-tenant use cases. We report on how FDP can mitigate the device-side WAF challenges arising due to the differing I/O patterns for various tenants. Also, we show that FDP can help to achieve better performance and isolation among different CacheLib tenants in the same SSD.

Author Bio:

Arun George is an Associate Technical Director at Samsung Semiconductor India Research Ltd (SSIR) in Bangalore. Within Samsung Memory Solutions, he contributes as a member of the Global Open Eco-System Team, driving the collaborative initiatives focused on Flexible Data Placement technology over NVMe. As a seasoned software architect, Arun boasts extensive expertise across diverse storage technologies including NVMe, Distributed Storage Systems, and NVDIMM Persistent Memory. His proficiency includes architecting and resolving complex challenges on both the host and device sides of the storage software stack. With 18+ years of industry experience, Arun has generated 11 patents and many academic papers.

Prasad Venkatachar, Solutions Director, Pliops

Paper Title:

Empowering Enterprises with Universal Database Accelerator

Paper Abstract:

Enterprises employ multiple database technologies from traditional Relational databases, NoSQL databases and now vector databases to manage the current builds and build Gen AI applications. As this enterprise application grow with increased adoption of users, data growth often they will encounter performance and quality of service (QoS) challenges. This session will explore how enterprises design their database applications that will enable performance scaling and accomplish QoS requirements economically. We will discuss Pliops Database solutions providing significant performance acceleration, latency reduction, capacity expansion for Relational, NoSQL and Vector Databases.

Author Bio:

Prasad Venkatachar is Sr Director Solutions & Products at Pliops. He is focused on Product strategy and leading and driving Data, Analytics & Storage solutions with partners. He has launched multiple industry-leading Data & AI/ML products & solutions collaborating with Microsoft, IBM, Oracle, Cloudera, and ISV partners to grow revenue & gain market share at Lenovo & HPE. He also served as a Microsoft Data and AI Partner Advisory Council Member and Member of Lenovo Technology Innovation. Served fortune 500 enterprise customers as SME to deliver business value outcomes for Datacenter and Cloud deployments. He has good experience and certified with Multiple Cloud (AWS/Azure/GCP/IBM) and Database (Oracle/DB2/Azure Data) and AI/ML certifications from Azure, Deep Learning, Google. A regular speaker in Industry Conferences: Microsoft Ignite, Oracle Open World, Developer conferences: Pass Summit, Oracle users group, Flash Memory Summit,SNIA & Gartner Conference

Hao Wu, Software Engineer, Meta

Paper Title:

Cachelib: Open Source High Performance DRAM/SSD Hybrid Caching Engine

Paper Abstract:

This talk will cover CacheLib which is a high performance and highly scalable DRAM/SSD hybrid caching engine. Within Meta, CacheLib is powering 100's of services and operating exabytes of scale of SSDs. CacheLib is written in C++ and provides thread-safe API and rich feature set to build high throughput, low overhead caching services.

Author Bio:

Hao is an experience software engineer supporting Cachelib at Meta.

Paper Session Description:

In this session we explore a variety of databases that address multi-tenant caching challenges, incorporate Flexible Data Placement (FDP) with NVMe technology, and offer better performance and isolation among tenants sharing the same SSD. We will also discuss solutions that target database acceleration strategies for performance scaling and QoS requirements. Lastly, the session will look at how Microsoft SQL Server continues to evolve with advancements in memory and flash storage technologies like PMEM and SLC flash.

Open SPOS-302-1: JEDEC Session Highlighting AI and LPDDR6 Developments at FMS 2024

Ballroom A, Floor 1

Track: Sponsored Sessions

Sponsor:

JEDEC

Organizer + Moderator:

Hung Vuong, Director of Technical Standards, Qualcomm

Hung Vuong is currently a director of standardization at Qualcomm, at Qualcomm in San Diego, responsible for memory & storage technologies. Hung is currently serves as Jedec JC42.6 subcommittee chairman for LPDDRx, JC64.1 subcommittee chairman for mobile storage, and a vice-chairman of Jedec Board of director. Prior to joining Qualcomm, Hung held numerous position at Texas Instruments & Motorola within the mobile architecture, design, and technology team.

Paper Presenters:

Manoj Wadekar, Hardware System Technologist, Meta

Paper Title:

Hyperscale memory requirements for AI systems

Paper Abstract:

In recent years, hyperscale data centers have been optimized for scale-out stateless applications and zettabyte storage, with a focus on CPU-centric platforms. However, as the infrastructure shifts towards next-generation AI applications, the center of gravity is moving towards GPU/accelerators for the AI systems. To keep up with this dramatic change, innovation is necessary to ensure that hyperscale data centers can continue to support the growing demands of AI applications. This presentation will discuss evolving memory needs for Hyperscale data centers for AI systems.

Author Bio:

Manoj Wadekar is a highly experienced AI system technologist with over three decades of experience in the server/networking/storage industry. He has held various leadership roles at companies such as Meta, eBay, QLogic, Intel, and Nortel, where he has been responsible for driving innovation and growth through needle-mover tech initiatives, creating and driving innovation pipelines, and deep vendor and academia engagement. He has a proven track record of delivering results in complex and dynamic environments. Manoj has led various industry initiatives to drive Ethernet, Fiber Channel, InfiniBand technologies and he is currently leading the Composable Memory Systems project within OCP, an initiative aimed at developing new memory technologies that can support the growing demands of AI applications.

Eric Oh, LPDDR Product Planning Park Leader, Samsung Semiconductor

Paper Title:

Expanding LPDDR Memory Subsystem for the Generative AI era

Paper Abstract:

Generative AI is rapidly expanding across various industries, driving innovation in redefining memory subsystem to overcome AI-driven memory wall. As Gen AI becomes more prevalent, LPDDR memory is crucial in handling the high performance and low power needs of these applications. In this presentation, we will identify the key LPDDR requirements for major AI-driven applications and discuss development and standardization directions of LPDDR targeting for generative AI era.

Author Bio:

19 years experience in DRAM industry at Samsung Electronics Semiconductor Memory system architect with expertise on memory sub-system and device specification for DRAM. He worked as a head of LPDDR DRAM Product Planning in Samsung Semiconductor Memory Division in Korea and Currently, he relocated to Samsung San Jose office in charge of LPDDR product planning and enabling.

Howard David, Principal Technical Product Manager for Memory Interface IP, Synopsys

Paper Title:

LPDDR6 A Deep Dive Into the JEDEC Press Release

Paper Abstract:

The presentations in this session highlight JEDEC standards and how they enable and address the future of AI, cloud, and automotive applications, and will also highlight new technology initiatives important to the industry and emerging trends critical to planning for the future.

Author Bio:

Howard David brings more than 30 years of experience to his role as Principal Technical Product Manager for Memory Interface IP at Synopsys. He is responsible for driving the product definition and technical aspects of business opportunities relating to Synopsys DDR, LPDDR, HBM, and other memory interface IP, working closely with the field organization, key customers, R&D and strategic partners. Prior to Synopsys, Howard held Memory Architect and Engineering positions at Intel, Huawei, and Socionext, with each position building his technical acumen and industry knowledge in architecting innovative memory solutions. Howard holds more than 30 patents in memory architecture as well as a BS in Physics from Michigan State University and a Masters in Electrical Engineering from Carnegie Mellon University.

Frank Ross, Sr. Member Technical Staff, Micron Technology

Paper Title:

DRAM Innovations &Technology Trends Addressing Evolution of Data-Centric Compute

Paper Abstract:

As the landscape of workloads and applications evolves driven by AI, so do the demands placed upon our computing systems. To prepare for these changes, it’s critical to create system architectures that place data at the heart of design decisions. This presentation will introduce the concept of data-centric system architectures, and the application of future memory hierarchy and storage optimization. We will explore DRAM innovations and trends as well as enabling technologies that will allow systems not only to meet, but exceed the demands of tomorrow’s workloads.

Author Bio:

I received my B.S.E.E. degree from The University of Vermont in 1990. I have been employed by Micron since 1990 in various technical and managerial roles including Test Engineer, Product Engineer, PE Manager, Applications Engineer, Program Manager, and Memory Systems Architect. While at Micron I have worked on myriad memory products and technologies including DRAM, VRAM, SDRAM, RLDRAM, LP-DDR DRAM, Embedded DRAM, CAM, NVDIMMs, and CXL memory.

Paper Session Description:

JEDEC is the global standards organization that leads the development of the industry's memory standards including DRAM and NAND flash. With more than 3,000 volunteers representing over 350 member companies, JEDEC is the key forum where companies come together to decide and define the future for memory. The presentations in this session highlight JEDEC standards and how they enable and address the future of AI, cloud, and automotive applications, and will also highlight new technology initiatives important to the industry and emerging trends critical to planning for the future.

PRO TEST-302-1: General Testing Methods

Ballroom G, Floor 1

Track: Testing and Performance

Paper Presenters:

Clinton Aaron Beetham, Staff Engineer, Samsung Semiconductor India Research

Paper Title:

Autopilot for FW Validation and Test Gap Identification

Paper Abstract:

Automated testing of FW release is the most important stage in a CI\CD process to verify business value, identify regression priorities and detect defects early in execution. Itâs overwhelming and not scalable how testers can decide its priority manually for each FW Release. Autopilot is an AI\ML-powered tool that can be integrated with CI\CD to automatically configure and update priorities for a test plan based on the FW features enabled and Change points from GIT diff. FW binary extractor (FBE) module creates a database with all the FW capabilities and change points along with its versioning, which is parsed to the AI\ML module which uses Spark NLP Based Dynamic Test Case Bundling for FW Validation (Spark NLP-DTCB-FV) to identify keywords and map test cases in to a multi-level priority list. Test Assessment Module (TAM) Processes the FBE Database vs Test Suite and dynamically prepares priority test list and reports errors for test gaps for FW Supported features. Around ~40% to 60% test cases are filtered out automatically from pre silicon to SOC stage which enables automated optimized testing using CI\CD. Keywords â Automation, FBE, TAM, Autopilot, Spark NLP-DTCB-FV, CI\CD, AI\ML

Author Bio:

Clinton Aaron Beetham is a Senior Staff Engineer at Samsung Semiconductor India Research (SSIR) with 14+ years of experience in storage domain. Specializing in "NVMe Compliance Test Suite Development" for all spec versions (NVMe\MI\OCP\MFND), Clinton uses that experience to drive test team with innovative and modern solutions for automated compliance testing. He currently works on architecting the test coverage and test solutions for NVMe SSDs. He holds a Master degree in Computer Application (MCA).

Christopher Cox, Fellow, AMD

Sayali Shirode, Systems Performance Engineer, Micron Technology

Paper Title:

Characterizing Data Ingest for Deep Learning Recommendation Model Training

Paper Abstract:

Deep Learning Recommendation Model (DLRM) is a neural network tailored for accurate and personalized recommendations in areas like products or content. Its importance stems from its capability to process large datasets, offering enhanced user experiences and satisfaction in recommendation systems across diverse domains. This session delves into the critical aspect of Data Ingest within the context of DLRM training. We will examine characteristics of DLRM training ingest at various stages in the data processing pipeline (offline, inline, hybrid) through analysis of IO traces and provide guidance on representing this workload on CPU-based servers.

Author Bio:

Sayali received an M.S. in electrical and computer engineering from Colorado State University in 2015. She's currently a Storage Performance Engineer at Micron's Austin location and has previously worked as Firmware Test Engineer at Micron's Colorado location. She focuses on analyzing the performance of data center applications.

Mike Dearman, CEO, Quarch Technology

Paper Title:

Testing CXL: lessons learned from PCIe and NVM

Paper Abstract:

With the rapid uptake of CXL, the industry will have to test and validate new designs of controllers and devices. This presentation will cover common issues encountered in testing of PCIe/NVMe devices and discuss industry best practice tests that will be needed to mitigate the risks. We will cover physical layer tests including hot-plug, device enumeration, sideband interaction, fault injection and dual redundancy testing. We will also testing low power states and power vs performance metrics

Author Bio:

Mike is the CEO and founder of Quarch. He has many years experience in the storage industry as a hardware architect and started Quarch to provide powerful automated test tools to help engineers like himself avoid tedious manual testing.

Paper Session Description:

In this session, we discuss new approaches to general testing methods. Autopilot for FW Validation and Test Gap Identification performs automated testing for FW releases. Integrated with CI/CD, this AI/ML-powered tool automatically configures test priorities based on FW features and changes from GIT diff. We will look at lessons learned from PCIe and NVM in testing new CXL designs and share best practice tests for controllers and devices to mitigate risks. We will also look at the importance of deep learning recommended model training in personalized recommendations and the critical role of Data Ingest in DLRM training

10:00 AM to 11:00 AM

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Open Global Student Presentations

FMS Theatre, Floor 2

Track: FMS 2024 Special Sessions

Sponsor:

Biwin

Special Presentation Description:

FMS looks forward to providing university students with a platform to showcase their work, and the opportunity to interact with the leaders of some of the biggest companies in our industry. Now in its 18th year, FMS has expanded its scope to encompass all tiers of Memory and Storage.

11:00 AM to 12:00 PM

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Open Executive AI Premier Level Panel

Mission City Ballroom, Floor 1

Track: FMS 2024 Special Sessions

Sponsor:

NVIDIA

Speakers:

Rob Davis, VP Storage Technology - Networking Business Unit, NVIDIA

Niket Agarwal, Distinguished Software Engineer, NVIDIA

Niket Agarwal is a Distinguished Engineer working on DGX Cloud system architecture and full stack optimizations across Data and AI Infra. Before working on DGX Cloud, Niket worked on building Omniverse Cloud, a managed SaaS service running on Azure and being used by customers for digital twin simulations. Niket has spent one and half decades working on large scale AI and cloud distributed systems. Niket got his PhD in Compute Architecture from Princeton University and BTech in Computer Science with IIT Kharagpur.

Rupert Menezes, CTO, VAST Data

Rupert Menezes is CTO for Artificial Intelligence (AI) and Emerging Technologies (ET) at VAST Data (an AI focused startup) Inspired by the Terminator movies of the 80's, Rupert got his bachelors in CSE/Robotics in 1996 and a Master’s of Science in AI in 2004.

Patrick Chiu, Sr. Director, Product Management, Storage Systems, Super Micro Computer, Inc.

Patrick is Senior Director of Supermicro’s storage product management and oversees both NVMe all-flash and 3.5” HDD storage product lines. He has more than 20 years of experience in NAND flash storage, server and software product design, product management, and business development in the IT industry. Patrick earned his MS degree in Computer Science from NYU.

Rory Bolt, Principal Architect, KIOXIA

Rory joined KIOXIA America in 2017. He has founded, built teams, and delivered product at four storage startups successful exits. Rory has more than twenty-five years of experience in data storage systems, data protection systems, and high performance computing with tenures as VP software Engineering at Samsung, Technical Director/CTO counsel at NetApp, CTO counsel at EMC, Vice President, Chief Storage Architect, and Distinguished Fellow at Quantum. Rory has been granted over 12 storage related patents and has several pending. Rory has a BS in Computer Engineering from UCSD.

Paul Cho, EVP Products and Solutions, Samsung Semiconductor, Inc.

As a Corporate EVP Products and Solutions Planning at Samsung Semiconductor, Inc., Sangyeun Paul Cho leads product roadmap and technical collaboration discussions with US customers and partners. He is often involved in driving strategic initiatives and delivering new synergistic solutions building on Samsung's broad silicon products and technologies. Sangyeun has also contributed to developing multiple generations of server class storage solutions at Samsung. He holds a Ph.D. in Computer Science from the University of Minnesota and a B.S. in Computer Engineering from Seoul National University. He was a tenured faculty at the University of Pittsburgh and is a Fellow of IEEE.

Special Presentation Description:

Storage and Memory Innovation for AI Workloads. Hosted and Moderated by NVIDIA. Panelists: KIOXIA, Samsung, Supermicro, Vast Data

12:10 PM to 01:15 PM

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PRO AIML-303-1: AI and ML Techniques

Ballroom B, Floor 1

Track: AI and ML Applications

Organizer + Moderator:

David McIntyre, Director Product Planning, Samsung Electronics

Paper Presenters:

Wesley Vaske, Principal Storage Solutions Enginee, Micron Technology

Paper Title:

MLPerf Storage - Enabling easy Storage for AI benchmarking

Paper Abstract:

Benchmarking and sizing storage for AI has a host of difficulties; the biggest is the cost of AI systems followed closely by the small size of available datasets. MLPerf Storage Benchmark Suite is an effort by MLCommons to enable easy representation of storage workloads for AI as well as generation of synthetic datasets that mimic the real datasets. This session will provide an overview of MLPerf Storage Benchmark Suite; we will analyze the workloads supported by MLPerf Storage and compare them to the real GPU-enabled workloads through analysis of I/O traces. We will also discuss how end users and storage vendors can use MLPerf Storage to represent their own workloads.

Author Bio:

Wes Vaske is a Senior Member of Technical Staff, Systems Performance Engineer at Micron Technology, working on application tracing and data analysis for SSD development since 2015. Previously, he worked in the Global Solutions Engineering group at Dell Technologies and has a B.S in Physics from Iowa State University

Michael Ocampo, Senior Product Manager, Ecosystem Marketing, Astera Labs

Paper Title:

Accelerating AI & ML with CXL-Attached Memory

Paper Abstract:

AI applications encounter significant memory and performance bottlenecks since these applications run on multi-processor systems that are memory and performance intensive. As complexity of large language models (LLM) and other machine-learning (ML) algorithms continue to increase, data centers are in dire need of more memory capacity and bandwidth. As a result, AI data centers encounter a number of challenges such as out-of-memory errors, spilling memory to slow storage when main memory is full, and inefficiencies due to memory copying operations. An alternative is for AI applications to use DDR memory to complement limited native attached memory. Compute Express Link® (CXL®) is an emerging technology that transparently expands memory capacity at low latency and high throughput in a cache-coherent fashion. This presentation describes how CXL-Type 3 devices can be leveraged to utilize DDR memory for running AI workloads across multi-node systems.

Author Bio:

Michael is an evangelist for open ecosystems to accelerate hybrid cloud solutions. With over a decade in x86 system integration, IaaS, PaaS, and SaaS, he offers valuable customer insights to product teams designing high-speed connectivity solutions for AI Training, Inferencing, and Edge Computing Infrastructure. His leadership has helped generate billions of dollars with data center solutions by bringing out the best talent and ideas across multidisciplinary teams within start-up and corporate environments. At Astera Labs, which IPO’d in March '24, he leads ecosystem alliances and owns the Cloud-Scale Interop Lab, now expanded into APAC. His work is crucial for AI factories and hyperscalers developing PCIe 6.x/CXL 2.x fabric solutions to accelerate AI services. He has a strong track record in agile development, having architected CI/CD solutions with Kubernetes infrastructure to support cloud-native AI applications and data platforms, driving significant growth in GenAI.

Ramya BT, Senior Staff Engineer, Samsung Semiconductor India Research

Paper Title:

AI/ML Case study of Optimized CXL based platforms for TCO and Performance

Paper Abstract:

AI and ML models, especially deep learning models require significant memory for training and inference. Storing and processing large datasets includes parameters and activations of complicated models, can strain memory resources. Deploying memory-intensive systems frequently necessitates significant infrastructure investments, such as high-performance resources includes storage and networking. These upfront costs contribute to the total cost of ownership (TCO) of AI and ML ventures. The rapid growth of artificial intelligence era and the demand of high density DRAM have forced the development of new computing architectures. The Compute Express Link (CXL) protocols enables expansion of primary memory with reduced TCO(include Power efficiency), low latency, enhanced I/O performance and power efficiency (PE). Here demonstrating memory-intensive deep learning CNN (Convolutional Neural network) based medical image analysis for diagnosing diseases, planning treatment etc. This workload modelled to detect and classify abnormalities like tumor in human brains, fractures and identify signs of lung cancer by analyzing high-resolution 3D scan images to get accurate predictions and quantitative analysis with CXL. This case study help to understand TCO, I/O performance & PE between Legacy system memory (DRAM) vs DRAM + CXL subsystem. Also depicts the advantages of CXL over the traditional memory on the memory-intensive AI workloads. UVM is a standardized methodology for verifying digital designs. It provides a mechanism for building functional test benches for achieving 100% functionality coverage. To achieve this, the verification engineers follows random testing, directed testing and coverage-driven testing and these involves a lot of manual effort. There is research going on to use ML in this field to reduce manual effort. Here, we are proposing a LLM model which automates the process of testcase generation in UVM environment and target to achieve complete code coverage. The model shall be pre-trained with system verilog syntaxes and UVM rules/keywords. It will be trained to learn the UVM sequences and testcase generation mechanism and also comprehend the cover points, which shall significantly reduce manual effort of the verification engineers.

Author Bio:

Ramya BT is a Chief Engineer at Samsung Semiconductor.

Ramyakanth Edupuganti, Staff Applications Engineer, Microchip Technology

Paper Title:

Application Agnostic Machine Learning Engines in SSD

Paper Abstract:

Machine learning plays a crucial role in data centers, addressing diverse applications like data management, NAND management, QoS and advanced fault prediction. The rising demand for application-agnostic machine learning is evident in meeting the evolving requirements of SSDs in the modern era. A key application of machine learning in SSDs is optimizing NAND management, particularly in overcoming challenges posed by increased density and layers in newer NAND technologies. Solving this issue opens doors for broader applications, making it essential for machine learning engines embedded in SSD controllers to be flexible and application-agnostic. This presentation focuses on an example of an application-agnostic machine learning engine controller architecture, showcasing its versatility in serving multiple applications within modern data center SSDs.

Author Bio:

Ram Edupuganti is the Applications Engineering Manager for Flashtec® NVMe® SSD Controllers in the Data Center Solutions Business Unit at Microchip Technology Inc. With over 14 years of dedicated contribution to the field, Edupuganti has played a pivotal role in the product development of enterprise storage solutions. He holds a Master of Science in computer science from California State University, Sacramento.

Arun Pillai, Staff Engineer, SSIR (Samsung Semiconductor India Research)

Paper Title:

AI/ML Case study of Optimized CXL based platforms for TCO and Performance

Paper Abstract:

Author Bio:

Arun is a professional with 9+ years of experience with technical contribution mainly in the field of test and development of CXL, Computational Storage, NVMe-oF controllers and All Flash Array reference designs, currently focusing on building AI/ML solutions for CXL storage solutions.

Paper Session Description:

This session dives into the world of AI and ML acceleration with CXL-Attached Memory, addressing the memory and performance bottlenecks faced by AI applications in multi-processor systems. By utilizing Compute Express Link (CXL), AI data centers can expand memory capacity and bandwidth, improving efficiency and reducing errors. A case study demonstrates the optimized performance and reduced total cost of ownership (TCO) achieved through CXL-based platforms for memory-intensive AI workloads. Additionally, the potential use of machine learning in automating UVM test case generation and the importance of application-agnostic machine learning engines in SSD controllers are discussed. Lastly, the MLPerf Storage Benchmark Suite simplifies storage sizing and benchmarking for AI workloads, aiding in representation and generation of synthetic datasets for accurate analysis.

PRO AUTO-303-1: Software Defined Vehicles NEW

Ballroom A, Floor 1

Track: Automotive Applications

Organizer + Chairperson:

Bill Gervasi, Principal Systems Architect, Wolley Inc

Paper Presenters:

Nicolas Leng, Assistant Manager, Product Management, ATP Electronics

Paper Title:

The Challenges of PCIe SSD Robustness in Cross Temperature Applications

Paper Abstract:

As IoT and electric vehicles are emerging into ubiquitous adoption, technical challenges arise in harsh environment, especially in temperature extremes. This presentation delves into the challenges, the related engineering validations, and methods to guarantee SSD robustness in the cross temperature context. Next generation PCIe SSDs enjoy a big leap in speed and performance, but with that comes with the disadvantages of overheating, which adversely impacting the reliability and performance of an SSD. The performance and reliability of SSD functionality are enhanced by how innovative thermal management solutions implementing both hardware and firmware customization for optimization are presented while reliability standpoints verified by carefully designed testing and screening methods to detect potential SSD failures in solderability are also discussed. The presentation aims to explore thermal design and algorithm management that dynamically adjusts in mitigating heat dissipation, key component reliability, followed by the environmental testing for quality assurance.

Author Bio:

Nicolas Leng has been with ATP Electronics for 8 years, currently leading business management team of Nand Solution Group at ATP Electronics INC. His past experience includes working in technology development department of MXIC (8 years).

Sandeep Krishnegowda, Sr Director of Marketing and Applications, Infineon Technologies

Paper Title:

SDV architecture needs high-performance, safe, and secured Flash memories

Paper Abstract:

Software-defined vehicles (SDV) offer a new value proposition for automobile manufacturers: services-based revenue over the lifetime of the vehicle. Trends such as e-mobility, automated driving, and mobility services will be made possible by SDV. The complexity in delivering this value in a digitally connected world requires software to be continuously optimized within the limits of the hardware available in the vehicles. Which implies that the hardware E/E architecture needs be provisioned with scalable compute performance that is safe and secured. As vehicles move towards more centralized compute platforms, automotive SoCs are transitioning to advanced process nodes (e.g. 5nm) to deliver the necessary compute performance at reduced power and cost. In this presentation we will explore how new automotive architectures drive Flash memory requirements. We will also consider new challenges associated with emerging ISO 21434 cybersecurity and ISO 26262 functional safety standards for external memories.

Author Bio:

Sandeep Krishnegowda is Vice President of Marketing and Applications for the Flash Business Unit at Infineon Technologies. He has over 15 years in experience in a variety of engineering, management and marketing roles. He has a Master’s in Electronics from Rensselaer Polytechnic Institute and a Bachelor’s in Electronics and Communication from Visvesvaraya Technological University.

Xian Liu, Associate Director, Technology Development, Silicon Storage Technology, Inc.

Paper Title:

A Robust Automotive Grade-0 Embedded Flash Technology

Paper Abstract:

Automotive-grade embedded flash technology plays a critical role in ensuring the reliable operation of vehicles. Its high performance, high reliability, and ability to withstand extreme conditions are essential. Embedded SuperFlash® technology has been demonstrated to meet automotive grade-0 requirements, with maximum junction temperature of 175C. This technology features several advantages over alternative eNVM technologies, including high speed, low power consumption, simple flash operation, high endurance, and a long and robust data retention lifetime. As a result, it simplifies SoC design, enables robust functional safety features, and accelerates time-to-market. Ultimately, it contributes to the stability and longevity of automotive systems.

Author Bio:

Xian Liu is an Associate Director of Technology Development and Product Test Engineering in Silicon Storage Technology, Inc., a wholly owned subsidiary of Microchip Technology, Inc. She develops SuperFlash® technology in various process nodes. Xian received her M.S. degree in Electrical Engineering and Ph.D. degree in materials science and engineering from Stanford University. She is a senior member of the IEEE.

Antony Ambrose, Storage Subsystem Architect, Bosch

Paper Title:

Storage solutions for connected, automated, personalised vehicles

Paper Abstract:

In recent years, automotive flash memory storage has emerged as a critical component in modern vehicles, enabling advanced functionalities such as infotainment systems, navigation, advanced driver-assistance systems (ADAS), and autonomous driving capabilities. As automotive technology continues to evolve, the demand for reliable, high-performance, and secure flash memory solutions becomes increasingly paramount. This presentation aims to explore the latest advancements and challenges in automotive flash memory storage. It will delve into the key factors driving the evolution of flash memory technology within the automotive industry, including the need for higher storage capacities, faster read/write speeds, and enhanced data security and most importantly increased life time. In summary, this presentation aims to provide a comprehensive overview of the advancements, challenges, and future prospects of automotive flash memory storage. By understanding the complexities and opportunities inherent in this critical component, automotive engineers and stakeholders can make informed decisions to drive innovation and enhance the reliability, performance, and security of future vehicles.

Author Bio:

Storage subsystem architect of the Cockpit Technology platform of Bosch.My responsibility is to define and develop next generation storage Architecture for connected, autonomous and electrified Vehicles. Main goal is develop a reliable, high-performance, and secure flash memory solutions. I have more than 18 years of experience in design and development of Automotive platform software (OS and device driver). For the past 10 years, I am focusing on the storage technologies. I hold a Bachelor Degree in Electronics and communication (Distinction)

Ritesh Thakur, Staff Engineer, Samsung

Paper Title:

Adaptive Memory Technology - Automotive

Paper Abstract:

Adaptive memory technology involved dynamic allocation and optimization of memory resources within a vehicle’s ECU (Electronic Control Unit) and other computing systems. Adaptive memory technology in the automotive industry typically refers to advanced systems that optimize memory usage based on changing conditions. This can enhance vehicle performance, safety, and efficiency by adjusting memory allocation in response to various driving scenarios and applications. Examples include adaptive memory management for infotainment systems, navigation, and driver-assistance features, ensuring optimal resource utilization for a smoother and more responsive driving experience.

Author Bio:

I am Ritesh Thakur currently working with Samsung Semiconductor Europe GmbH in the Technical Marketing Group and located in Munich, Germany. My main role is enabling and supporting Automotive Memory business in EMEA. I have also worked in SSD Firmware Development (Client, DC and Enterprise) and Testing and have also held different roles in top tier memory companies like Toshiba, SanDisk and Micron.

Paper Session Description:

Adaptive memory technology in the automotive industry involves the dynamic allocation and optimization of memory resources within a vehicle's ECU and computing systems, enhancing performance, safety, and efficiency through memory allocation adjustments based on driving scenarios. Challenges in PCIe SSD robustness in cross-temperature applications are explored, focusing on overcoming overheating issues to ensure reliability and performance. The importance of flash memory storage in modern vehicles is highlighted, addressing the need for high-performance, secure solutions to enable advanced functionalities. As software-defined vehicles become prevalent, the need for high-performance, safe, and secure flash memories is emphasized to support evolving automotive architectures and standards. Embedded automotive-grade flash technology is also discussed for reliable and stable vehicle operation.

Open BMKT-303-1: Data-Intensive Customer Solutions

GAMR 1 (Great America Meeting Room 1), Floor 2

Track: Business Strategies and Memory Markets

Organizer + Chairperson:

Jean Bozman, President, Cloud Architects Advisors

Paper Presenters:

Molly Presley, SVP Marketing, Hammerspace

Bill Basinas, Sr. Director Product Marketing, Infinidat

Paper Title:

Delivering Value and Differentiation for Hybrid Cloud Environments

Paper Abstract:

Enterprise Storage is critical to empowering service providers and enterprises with exceptional value through differentiated hybrid cloud storage. By uniting high performance, scalability, and cost-effectiveness your hybrid cloud will be seamlessly integrated with your on-prem storage environment and deliver powerful OPEX savings. By harnessing cutting-edge machine learning and autonomous automation, hybrid cloud storage enables you to optimize customer value, efficiently managing data growth and lowering TCO. In today's threat landscape, ransomware, malware, and cyberattacks pose significant risks to data. State-of-the-art data protection, cyber resilience, and recovery with advanced detection capabilities play a crucial role in bolstering your overall hybrid cloud storage strategy, ensuring data remains safeguarded and recoverable.

Author Bio:

Bill Basinas is Senior Director, Product Marketing at Infinidat and has been focused in the storage industry since 1994 when he joined Legato Systems as the first field systems engineer. He was also an early employee at Avamar and spent time at enterprise companies such as EMC and HPE Storage in Global Marketing and Engineering roles.

Davide Villa, CRO, Xinnor

Paper Title:

Fast Storage Tier to Cache 100PB Tape Library

Paper Abstract:

In this presentation, we'll describe the tests done by Karlsruhe Institute of Technology (KIT) to select a fast cache solution to be used in front of their 100PB tape library. We'll compare the results of the tests conducted by KIT using NetApp E5700 with 120x 8TB HDD, Dell Powervault ME5024 with 2 extension enclosures with 48x 3.84TB SSDs each, and a x86 server with 10 NVMe drives and Xinnor's xiRAID to provide RAID protection. The outcome of the tests will show how xiRAID implementation can provide stable performance of 50GB/s in read and 25GB/s in write, greatly outperforming all other alternatives. This use case will show that also cold storage requires performance and RAID protected NVMe SSD outpeforms more expensive legacy implementations.

Author Bio:

Since the beginning of 2023, Davide Villa is the Chief Revenue Officer at Xinnor. Davide is a veteran in the storage and flash industries, bringing more than two decades of experience. Prior to joining Xinnor, Davide served as Director of Business Development in the EMEAI region at Western Digital. Davide has been a pioneer in the Flash industry. In the early days of the flash boom, he managed business development for the NAND flash division at STMicroelectronics and later on, he had multiple roles at sTec, including VP of EMEA sales, when the company introduced the first enterprise SSD to the market.

Odie Killen, VP Hardware Engineering, Viking Technologies

Paper Title:

Balancing of HDD and SSD in large Scale Deployments

Paper Abstract:

Discussion of best use cases for SSD and HDD in larger scale system deployments. Includes ways to optimize SSD deployments for larger scale adoption and areas where each technology is better optimized for deployment.

Author Bio:

Manzur Rahman, Product Marketing Engineering Manager, Solidigm

Paper Title:

Optimizing Data Center TCO: An In-depth Analysis and Sensitivity Study

Paper Abstract:

Total Cost of Ownership (TCO) is crucial for data centers as it encompasses all costs related to acquiring, operating, and maintaining infrastructure over its lifecycle. Understanding TCO helps in making informed decisions about investments in technologies and operations that can significantly impact efficiency and cost-effectiveness. Due to intensive computing and storage demands of AI workloads, TCO increases by necessitating more powerful and expensive hardware, increased energy consumption, and enhanced cooling system. Our comprehensive TCO model encompasses Capital Expenditures (CAPEX), Operating Expenses (OPEX), maintenance, and other associated costs, providing a holistic view of data center investments. We've conducted a detailed analysis to understand TCO sensitivity and identify the major variables driving TCO. This analysis led to the development of low, base, and high cases for TCO, offering a spectrum of potential outcomes based on varying operational conditions and investment strategies.By examining these scenarios, stakeholders can better strategize on minimizing TCO while optimizing data center performance and capacity for wide range of workloads.

Author Bio:

I serve as the Product Marketing Engineering Manager at Solidigm, overseeing the Gen5 TLC product line, including the D7-P7500, known for its FDP and block modes. Prior to joining Solidigm, I contributed my skills to Oracle, MediaTek, and Intel. My academic background includes a PhD in Chip Design from the University of Texas at Austin and an MBA from Duke University.

Brian Dargel, Director of Technical Marketing, Solidigm

Paper Title:

Is It Too Early to Talk about Quantum Computing?

Paper Abstract:

Quantum Computing is starting to reach early commercialization, with multiple claims of quantum supremacy, the industry has moved from the lab to broad development of deployable systems, both stand alone and accessible through the cloud. As the focus shifts from the number of Qubits to error correction, decoherence and enabling a path to realizing the application of the increasing number of viable quantum algorithms the question of what role classical computing, and by default, classical storage may play in this evolving computing technology. This presentation aims to provide insight to the longer-range opportunities for storage in this developing market.

Author Bio:

Brian Dargel is currently the Director of the Technical Marketing Engineering group at Solidigm. A veteran of over two decades in the Flash Memory industry, Brian has held business development and marketing positions at Intel, LSI/SandForce, and Micron.

Paper Session Description:

Customer use of Artificial Intelligence (AI) and GenAI in their businesses is leading to vast amounts of scalable AI data that must be managed, protected and secured. This is a formidable challenge for IT organizations – and for the business units that use AI analytics to drive higher levels of corporate revenue and profits. This informative session, based on actual customer results, discusses large data resources – with petabytes of data – and shows how customers are working with them, while preventing cyberattacks and ransomware from slowing or stopping business operations. Presentations include: the selection of a fast-cache solution for a 100PB tape library; an in-depth analysis of Total Cost of Ownership (TCO) for data centers; and a presentation about optimizing investments for efficiency and cost-effectiveness in the data center – and in the hybrid cloud.

PRO CLDS-303-1: Cloud Solution/Technology Innovations

Ballroom E, Floor 1

Track: Cloud Storage and Applications

Paper Presenters:

Suresh Rajgopal, SENIOR TECHNOLOGIST, SYSTEMS ARCHITECT, Micron Technology

Paper Title:

What can Storage do for AI?

Paper Abstract:

With the increased business value that AI enabled applications can unlock, there is a need to support AI models at varying degrees of scale - for training, inference and even subsequent operational deployment (AIOps) in an enterprise production environment. Flash Storage and PCIe/NVMe storage in particular, can play an important role in enabling this. We highlight a few key AI growth areas in LLM and DLRM training and inference that are currently challenged and highlight how NVMe offload can alleviate. Enabling NVMe storage for AI requires a combination of careful ML model design and its effective deployment on a memory-flash storage tier. The latter requires an optimal software stack and flash storage that is not a bottleneck to model parameter and state retrieval. If done right the cost, power and scale-out benefits can be significant.

Author Bio:

Suresh Rajgopal is a Distinguished Member of Technical Staff at Micron Technology working on Enterprise SSD product architecture and storage deployment of AI solutions. He has been with Micron Technology since 2010, working in areas of SSD systems architecture, advanced power and packaging technology and ASIC development of flash controllers, for client, enterprise and managed NAND products. He has more than 25 publications to his credit and holds more than 20 patents. He received his Ph.D. in computer science from the University of North Carolina (Chapel Hill)

Jung Yoon, Distinguished Engineer and CTO, Supply Chain, IBM

Paper Title:

Infrastructure AI accelerated by advanced Memory and Flash tech

Paper Abstract:

This paper will provide unique technical insights into key driving forces that are supercharging exponential AI technology growth from an Infrastructure Hardware enablement perspective. We will focus on AI centric driving forces centered at Bandwidth, Latency, Packaging, Sustainability, and Resilience. This is becoming critical topic as the industry will need to ascertain technical roadmap in meeting customer needs focused on exponentially growing complex deep learning & AI workloads, across multi-Zeta byte big data. In this paper, we will focus on key AI centric infrastructure technical directions critical from an advanced memory and flash storage technology perspective.

Author Bio:

Jung Yoon is a Distinguished Engineer & CTO of IBM Supply Chain. He is a recognized industry leading expert in DRAM, 3D-NAND, SSDs, and semiconductor devices, and drives technology convergence between industry capabilities and IBM’s strategic product offerings. Jung has over 30 years of experience in the field of Semiconductor R&D, technology enablement and quality. He represents IBM as a member of the FMS Conference Advisory board. Jung earned his PhD in Materials Science from Columbia University, MS from University of California Berkeley, and a BS from Seoul National University.

Nilesh Shah, VP, Business Development, ZeroPoint Technologies

Paper Title:

Composable Memory Systems: Exploring innovations to Address adoption barriers

Paper Abstract:

This session delves into Composable Memory Systems (CMS) utilizing Compute Express Link (CXL) to overcome adoption barriers at Hyperscale. Supported by economic models illustrating Total Cost of Ownership (TCO) and driving technological innovations, the presentation begins with an analysis of the increasing demands in Hyperscale and AI workloads, necessitating CMS, and practical TCO arguments from Hyperscalers that hinder CMS adoption. We analyze CXL-attached Flash memory tiers and pools for large memory and non-blocking AI use cases. transformative enablers like Optical CXL interconnects, NVMe over CXL, and the OCP Hyperscale CXL Tiered Memory Expander Specification reshaping the Future of Memory and Storage. Identifying collaborative innovation opportunities within the CXL Community, we highlight areas for expediting software/hardware advancements for CXL Tiered Memory Expansion. We summarize unresolved challenges in Pooled deployment and open the discussion to the audience, seeking feedback and fostering a rich dialogue between presenters, panelists, and the audience, with the ultimate aim of making CXL adoption a "No Brainer" at Hyperscale.

Author Bio:

Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft

Paper Session Description:

Composable Memory Systems (CMS) are a game-changer for hyperscale environments, but adoption barriers exist. This session dives into using Compute Express Link (CXL) to overcome these hurdles, backed by Total Cost of Ownership (TCO) models. We explore demands in Hyperscale and AI workloads, driving the need for CMS. With CXL-attached Flash memory tiers and pools, along with transformative enablers like Optical CXL, NVMe over CXL, and OCP Hyperscale CXL Tiered Memory Expansion, the future of memory and storage is reshaped. Collaborative innovation within the CXL Community is key, with unresolved challenges in pooled deployment.

PRO DSEC-303-1: Addressing Device Exposures

Ballroom D, Floor 1

Track: Data Security/Ransomware Protection

Organizer + Chairperson:

Camberley Bates, VP and Practice Lead, Futurum Group

Paper Presenters:

Vishwas Saxena, Technologist, Firmware Engineering, Western Digital

Paper Title:

Secure Cross platform authentication of USB Self Encrypting Drives

Paper Abstract:

TCG Storage Security Opal specification for notebooks/portables storage lay down the guidelines for USB Self Encrypting Drives. Since the authentication key passed from host application unlocks the USB self-encrypting drive, one of the important aspects of TCG’s specification is managing the authentication keys (or passwords) thereby providing easy-to-use solutions for flexible management of these keys is vital. How¬ever, host application managing the authentication of USB SED uses a USB mass storage driver that is OS/platform dependent to communicate with the USB drive. Learn how we design HTTP application interface between the web browser and the USB SED for authentication. This approach greatly simplifies the application to USB SED communication and reduce the need for multiple OS-specific applications. Additionally, it leverages the security features inherent in web browsers, which are often sandboxed and designed to be secure. We also designed lwIP, and CDC-NCM based ethernet over USB driver from open-source software for memory constrained USB flash devices to provide the lightweight TCP/IP stack that enables this technology solution to lock/unlock the USB Drive

Author Bio:

Luis Freeman, Technical Project Manager, Technology and Strategy for Storage Devices, Supply Chain Engineering

Paper Title:

Staying ahead of Counterfeiters when using OEM Generic Drives for Enterprise

Paper Abstract:

As Hyperscalers demand for HDDs/SSDs grows representing more than 80% of the total demand, the HDD/SSD Suppliers have less incentives to do Custom Firmware for Enterprise Clients therefore forcing Enterprise Clients to transition to OEM Generic Firmware drives. The switch of Enterprise Clients to OEM Generic drives makes it easier for counterfeiters to take HDDs/SSDs from the black market and configure them to look like the enterprise drive because the barrier of Custom Firmware has been lifted. This paper explores ways to secure and verify authenticity of configured OEM Generic Firmware drives by adapting Public Key Infrastructure (PKI) concepts like Asymmetric Encryption Keys and Certificates in use today to secure web transactions and email communication to verify authenticity of configured OEM Generic Drives.

Author Bio:

Luis Freeman is a Technical Project Manager in the IBM Supply Chain Engineering Organization. Luis is responsible for the Selection and Qualification of Storage Devices used on IBM Systems. In this role, Luis is responsible to interlock with the Storage Devices Suppliers and IBM Brands Development teams to find the right storage devices to use on each Server and Storage System IBM sells. Luis is also the owner of the IBM Purchase Specification for NVMe Devices. Luis recently became a Member of the NVM Express Technical Committee and the SNIA Computational Storage TWG with the goal of helping shape the Data Storage Industry. Luis Freeman graduated from Universidad de Guadalajara, Mexico in 1996 with a Bachelor’s degree in Electronics Engineering. He started his career at IBM Guadalajara in 1996 as a Buyer for Electronic Card Assemblies for laptops/desktops and got a Master’s degree in Industrial Electronics in 1999 from ITESO in Guadalajara, Mexico. In 2000, Luis took an opportunity to work at IBM Raleigh, NC as a Global Commodity Manager for Electronic Assemblies and has worked since at IBM Raleigh in different Supply Chain roles.

Steve Chung, NYCU Chair Professor/UMC Chair Professor, National Yang Ming Chiao Tung University

Paper Title:

Embedded OTP Memory Solution Towards 3nm Generation: High Security Purposes

Paper Abstract:

Encryption, identification and security have become an indispensable part of portable devices, e.g., mobile phone, and high performance computing CPU, GPU, MCU etc. which require an embedded and compatible with logic-CMOS. In particular, we need high security functions to cope with design of logic memory IP in advanced technology nodes. For various generations of OTP(One-Time-Programming) development since early 2000, most of them used metal-fuse or anti-fused function with traditional breakdowns. They have the limitation in reducing the operating bias or instability in the gate dielectric of MOSFET, e.g., implementation in the scaling down to 3nm. We proposed a new type of OTP, named as dFuse (dielectric fuse) which used a completely different breakdown to broken the gate dielectric. First, a 4Mb MACRO OTP was successfully developed in a foundry 28nm HKMG CMOS and is readily available for MCU in mobile, and later a PUF(Physical Unclonable Function) in advanced 14nm FinFET technology node was developed, expected for down to 3nm generations. This paper will demonstrate the MACRO design as well as the for security applications in the IOT and 5G/6G era.

Author Bio:

Steve Chung received his Ph. D. from University of Illinois at Urbana-Champaign in 1985, under the supervision of world renowned CMOS co-Inventor C. T. Sah. He is the Chair professor of NYCU (former NCTU) with past administrative position in managing International Offi ce and Executive Director of the school's TOP-University plan funded by the government. He was a visiting prof. to both Stanford and UC-Merced, CA, in 2021 and 2008 respectively. He was also a consultant to the two world giants in foundry- tsmc and UMC. His current research interests include- nanoscale CMOS, flash memory, resistance Memory Technologies, from storage to AI applications. He was the first speaker (from Taiwan) to present the paper at VLSI Technology symposium in 1995, and has 35+ times presentations at IEDM/VLSI. He has more than 300+ publications and also holds more than 40 patents. He is an IEEE Life Fellow, US NAI Fellow, current IEEE Distinguished Lecturer, Senior Editor of Applied Physics-A (Springer), Executive Committee member of VLSI, and with past involvements as IEEE EDS Board of Governor for more than 12 years, EDS Regions/Chapters Chair, and Editor of IEEE J-EDS, EDL(2002-2008), guest editor of TDMR, Committee members of VLSI, IEDM, IRPS etc.. Among numerous awards, he has been a recipient of Three-time Outstanding Research Award (National Science Council), Pan Wen Yuan award (2013) to recognize outstanding researcher in Taiwan on semiconductors, Lifetime achievement award as National Inventors (2019) etc.

Paper Session Description:

Physical devices, memory, drives, USB’s all pose threats when introduced to systems, especially when the chain of custody may be cloudy. The speakers in this session will bring to light some of the latest threats and approaches to assure the devices are clean and non -threatening before they are introduced into the systems environment

PRO NETC-303-1: CXL and PCIe Memory Fabrics

Ballroom F, Floor 1

Track: Networks and Connections

Chairperson:

John Kim, Director of Storage Marketing, NVIDIA

John Kim is Director of Storage Marketing at NVIDIA

Paper Presenters:

Steve Scargall, Senior Product Manager/Software Archtect, MemVerge

Paper Title:

Fabric Attached CXL Memory Systems and Their Impact on Key Industries

Paper Abstract:

Join us for an insightful presentation by Charles Fan, where he delves into CXL technology, and the evolving landscape of fabric attached memory systems. Market research firm Yole forecasts an impressive $15.8 billion in CXL revenue by 2028, with a majority originating from fabric attached CXL memory systems. In this session, Charles Fan will guide the audience through the architectural evolution and timeline of these cutting-edge systems, focusing on CXL 2.0 specifications and providing a glimpse into the future including systems based on 3.x specifications. The presentation will highlight the collaborative efforts of MemVerge and its hardware partners, showcasing testing methodologies applied to the use of fabric attached CXL memory systems in various use cases. Charles will unveil the top 3 use cases, revealing compelling insights derived from testing in data-intensive AI, Financial Services, and Video Production applications. Attendees can expect to leave with a greater understanding of how fabric attached CXL memory systems are poised to revolutionize how memory will be used in the future.

Author Bio:

Steve Scargall is a Senior Product Manager/Software Architect at MemVerge. Before MemVerge, he was a Persistent Memory Software and Cloud Architect at Intel, where he supported the enabling and development effort to integrate persistent memory technology into software stacks, applications, and hardware architectures. He has written a popular book on “Programming Persistent Memory: A Comprehensive Guide for Developers”. Before joining Intel, he worked at Oracle and Sun Microsystems. He has over 19 years’ experience providing support and development of kernels, file systems, and performance analysis . He earned a BS in Computer Science and Cybernetics from the University of Reading (UK).

Brian Pan, General Manager, H3 Platform

Paper Title:

PCIe Gen5 fabric and management

Paper Abstract:

H3 implement the PCIe fabric by using 4 PCIe Gen5 switch (full mesh) to form a fabric with 4 different hosts and 16 nVidia GPUs. This is the very first disaggregate PCIe fabric implementation. The presentation will show the PCIe fabric topology, 16 nVidia GPU P2P operation, performance testing, and the management architecture.

Author Bio:

Chris Blackburn, Director of Field Applications Engineering, Astera Labs

Paper Title:

Scaling GPU Clusters & Low-Latency Memory Fabrics with Active PCIe®/CXL® Cabling

Paper Abstract:

The increasing size and complexity of AI workloads are driving the need for high-bandwidth, low-latency active cabling solutions to connect larger clusters of GPUs and low-latency memory fabrics. New AI infrastructure must scale these GPU clusters and expanded memory resources across server racks at greater physical distances as racks can only accommodate a limited number of GPUs or memory resources due to physical space, power, and thermal management constraints. This evolution faces challenges, notably the limitation of passive PCIe DAC solutions, which are constrained to a 3-meter reach at PCIe 5.0 speeds and lack critical data center management features. In addition to extended signal reach, new active PCIe/CXL cabling solutions must provide extensive link health monitoring, fleet management, and RAS features to optimize data center performance and total infrastructure uptime. Attendees will gain key insights into the challenges facing AI infrastructure, the benefits of an active PCIe/CXL cabling approach to scaling both GPU clusters and low-latency memory fabrics, and the need to provide advanced diagnostics capabilities to ensure high reliability and uptime for hyperscalers.

Author Bio:

Chris Blackburn is the Director of Field Applications Engineering at Astera Labs. He works closely with the leading hyperscalers and cloud builders on their interconnect technologies to enable next generation system architectures. His experience with PCIe, CXL, and Ethernet helps shape large scale hardware acceleration clusters being built to support generative AI. When Chris isn't on his PC he can be found adventuring throughout the great pacific northwest.

Paper Session Description:

This session will discuss a variety of CXL and PCIe memory fabrics. Traditional HPC architectures can be inefficient, with underutilized resources leading to wasted energy. Composable Disaggregated Infrastructure (CDI) offers a solution by dynamically composing servers with shared hardware resources. The OpenFabrics Alliance is developing Sunfish, an open-source management framework to control and monitor computing resources across different fabric types. Scaling GPU clusters and low-latency memory fabrics is crucial for AI workloads. Active PCIe/CXL cabling solutions are needed to connect larger clusters efficiently. Attendees will learn about the limitations of passive PCIe DAC solutions and the benefits of active cabling for scalability and reliability.Lastly, we will explore PCIe Gen5 fabric implementation and the impact of Fabric Attached CXL Memory Systems on key industries..

PRO OPSW-303-1: Memory Management Ecosystem

Ballroom C, Floor 1

Track: Open Source Software

Paper Presenters:

Davidlohr Bueso, Principal Software Engineer, Samsung Electronics

Paper Title:

State of the CXL Linux Ecosystem

Paper Abstract:

This presentation aims to provide a look into the current state-of-the art for Linux CXL support, for which, being fast paced, the audience can benefit in various ways. First, gain a better understanding on how the general ecosystem works across the software stack. Second, an overview of new relevant functionality that has been merged upstream in the recent past, along with a look ahead for upcoming features. And finally, being aware of some of the current challenges and open topics, such as in OS memory tiering and Fabric Management. Further, the presentation provides insights into the collaborative efforts within the Linux development community.

Author Bio:

Davidlohr Bueso is a Principal Engineer at Samsung Electronics, focusing on Linux kernel development, including CXL enablement. For over a decade, he has contributed many performance and scalability enhancements to core kernel subsystems for large SMP servers, as well as improving real-time computing capabilities. In the past he has worked at SUSE Linux and Hewlett-Packard.

Sergei Vinogradov, Middleware Architect, Intel

Paper Title:

Unified Memory Framework - unified API for diverse memory technologies

Paper Abstract:

Emergent memory technologies address the needs of modern data-intensive workloads. But, SW adoption is required to fully leverage new HW capabilities. OS and drivers are important in enabling new HW technologies. But there is a middleware layer between applications and system level that plays a significant role in getting benefits from modern HW. In this talk, we are going to present Unified Memory Framework (UMF) – an open-source project aimed at providing consistent mechanisms for SW developers to work with memory hierarchies and functions that operate on it. UMF is a successor of the Memkind library for constructing allocators and memory pools but in addition to CPU use cases also covers the GPU domain. It allows users to create and manage multiple memory pools characterized by different attributes, allowing certain allocation types to be isolated from others and allocated using different hardware resources as required. Flexible mix-and-match API takes full advantage of CXL memory and HBM on CPU and Unified Shared Memory on GPU. As a case study, we demonstrate how oneAPI SW stack benefits from UMF as an infrastructure layer and improves interop between higher-level runtimes.

Author Bio:

Sergei is a Senior Software Engineer at Intel working on runtime libraries and performance profiling tools. The current Sergey's focus is programming models for heterogeneous memory and software adoption for emergent memory technologies.

Javier Gonzalez, Principal Software Engineer, Samsung Electronics

Barrett Edwards, CEO, Jackrabbit Labs

Paper Title:

An Open Solution for CXL Fabric Management and Orchestration

Paper Abstract:

CXL technology is poised to transform computing by enabling remote pools of memory to be shared coherently among multiple compute nodes. With true shared memory, software applications can span multiple compute nodes just as they can span multiple cores and sockets. Despite this promising capability, two challenges exist that are limiting the adoption of CXL technology, which are the lack of a CXL software development environment and industry standard tools to configure, monitor, and orchestrate the memory fabric. We present an open source solution to these two challenges. First we present 'Jack' which is a tool compliant with the CXL Fabric Management API specification that enables the configuration of a CXL memory fabric. We also present a CXL software development environment that integrates fabric management with the virtual CXL 2.0 switch capabilities recently introduced in QEMU. Together these enable the development of shared memory software running within guest operating systems without requiring underlying physical CXL hardware.

Author Bio:

Barrett Edwards is the CEO of Jackrabbit Labs. He is responsible for setting product strategy and vision as the company seeks to reshape the future of computing and software design using shared coherent memory. Previously he was the CTO of the Platforms Business Unit at Western Digital and has held development management and product planning responsibilities at SanDisk and Fusion-io for PCIe storage products as well as software defined network appliances. Barrett earned Bachelor of Science and Master of Science degrees in Electrical and Computer Engineering and a Master of Business Administration degree from Brigham Young University.

Paper Session Description:

In the world of computing, CXL technology is set to revolutionize the way we think about memory management. With the ability to share memory coherently across multiple compute nodes, the possibilities for software applications are endless. However, the lack of a comprehensive software development environment and industry standard tools has been holding back the widespread adoption of CXL technology. Thankfully, we have developed an open source solution to address these challenges. With tools like 'Jack' for fabric management and a software development environment that integrates virtual CXL switch capabilities, we are paving the way for a future where shared memory software is the norm. Join us as we dive into the current state of the Linux CXL ecosystem and explore the benefits of a Unified Memory Framework, providing a unified API for diverse memory technologies. The future of computing is bright, and with these innovations, we are ready to embrace it head on.

PRO SSDT-303-1: Power Optimization & Telemetry Features for SSDs

Ballroom G, Floor 1

Track: SSD Technology

Organizer + Chairperson:

Erich Haratsch, Senior Director Architecture, Marvell

Paper Presenters:

Karthik Balan, Associate Director, Samsung Electronics

Paper Title:

NVMe Telemetry and Open Source Readiness

Paper Abstract:

The latest OCP Datacenter NVMeSSD specifications (version 2.5) introduces a series of improvements in Telemetry data management, particularly with the addition of an ASCII String log page for vendor-specific data and enhanced host control over the data area contained in the log page (reference TP4109a). This enables customers and SSD vendors to have better access to their telemetry data, while maintaining the uncompromising security policies in the Datacenter. In this presentation, we will provide an overview on the Telemetry enhancements in the OCP Datacenter 2.5 specification. In addition, we will present about the upstream support we have added to mainstream open-source tools in order to generate and validate telemetry data and string log pages as defined in the specification. This shall give an overview of how users can interact with these new telemetry logs and integrate them in their infrastructure.

Author Bio:

Karthik is a Associate Director at Samsung Electronics(SSIR), he has experience of 19 years in Embedded System Testing and last 12 years in Memory Solutions Tests for eMMC, NVMe, CXL, etc. He is currently works on architecting the test coverage and test solutions for NVMe Enterprise SSDs. Driving towards shift-left approach and open source enablement for NVMe SSD qualifications

Pitamber Shukla, Senior Technical Staff Engineer-Architect, Data Center Solutions

Paper Title:

Firmware Driven NAND Power Management for Improved SSD QoS

Paper Abstract:

Power consumption has been a major concern with the SSD (solid state drive) design, one that is often in contradiction to SSD lower performance requirements. Power token-based SSD power management has been used to determine if the power is available for the upcoming operation while the ongoing operation is consuming the power until it is finished. The firmware (FW) driven NAND power management solution will significantly improve the quality of service (QoS) in hyperscale SSD. The FW solution to be presented here will improve the QoS by the NAND power supply (Vcc), adjusting the latencies of NAND operations (erase/program/read), skewing NAND operation across different flash channels and intelligently implementing the suspend/resume operation for improving QoS on key workload. Many times, when the upcoming operation is performance critical or QoS critical, the ongoing operation’s power consumption is too high for the critical operations to start. This innovative method employs smarter algorithms in evaluating current state, managing the power tokens/credits, and adjusting the priority of operations real time to guarantee the QoS.

Author Bio:

Pitamber Shukla received a Bachelor of Technology degree in electronics and communication from SASTRA University, Tamil Nadu, India, in 2009 and a Ph.D. in electrical and computer engineering from the University of Illinois at Chicago, USA in 2014. He has more than 14 years of experience in research and development of semiconductor devices and applied machine learning. Shukla is currently, aSr. Technical Staff Engineer-Architect at Microchip Technology Inc. and ispart of the Flashtech® Architecture team that defines future product direction, guides NAND characterization effort and define new NAND features. He holds 32 U.S. patents, with 30 U.S. patents in application stage, 9 trade secrets, 8 publications (3 publications in the field of machine learning), 1 book chapter and 1 invited talk.

Ayberk Ozturk, Director, Microsoft

Paper Title:

The Telemetry Feature of VIHR SSDs

Paper Abstract:

Microsoft is actively involved in enhancing the quality of storage devices, minimizing capacity impact, and improving customer experience through the Vertically Integrated High Resilience (VIHR) SSDs, in line with OCP v2.5+ specification, in Azure. One of the key features of VIHR SSDs is telemetry. Telemetry data collected from storage devices is utilized for online monitoring, offline log collection, and root cause analysis. Both online monitoring and offline collection aid in predicting, detecting, and diagnosing failures, as well as analyzing root causes. Root cause analysis contributes to identify bugs in firmware and hardware components. By leveraging telemetry attributes, the health of storage devices can be proactively monitored, and preventative measures can be taken to minimize downtime. This, in turn, improves the overall reliability and performance of storage devices, resulting in a better customer experience.

Author Bio:

Ayberk Ozturk is an accomplished storage expert with a wealth of experience in the field. Throughout his 15-year career, Ayberk has held positions at several industry-leading corporations, where he has developed a reputation for his technical expertise and ability to design and deploy innovative storage solutions. Ayberk's technical prowess is particularly evident in his current role at Microsoft, where he leads a team in the Azure Memory & Storage organization. In this capacity, he is responsible for ensuring the stability, predictability, security, and reliability of the storage devices deployed within the Microsoft Azure. Ayberk's contributions to the field of storage have been numerous, and he has been awarded seven patents related to the development and deployment of cutting-edge storage solutions. He earned a Master of Science degree in Electrical Engineering from the University of Southern California, and a Bachelor of Science degree in Electrical Engineering from the Pennsylvania State University.

Jonmichael Hands, Sr Director Strategic Planning, Fadu

Paper Title:

Efficient by Design: The Role of SSD Controllers in Rack-level TCO

Paper Abstract:

Hyperscale data centers are increasingly leveraging NVMe power states to manage the Thermal Design Power (TDP) of SSDs, aiming to reduce cooling requirements and optimize Total Cost of Ownership (TCO). The cornerstone of SSD energy efficiency—gauged by performance per watt—lies in the synergy between innovative controller architectures and advanced NAND technology. PCIe 5.0 and 6.0 create an even larger challenge for SSDs as the performance expectations of SSDs increase. In this session, we delve into the cutting-edge design of SSD controllers, emphasizing the utilization of RISC-V architecture and a programmable control plane. This design is tailored to bypass the traditional bottlenecks imposed by CPU cores in the IO path. Such an architectural innovation not only propels power efficiency but also markedly elevates the performance of data processing and storage operations. We will explore how these advancements in energy efficiency can translate into significant TCO savings, fostering more sustainable and economically viable data center practices. Our discussion will underscore the strategic implications of adopting these energy-efficient storage solutions, highlighting their p

Author Bio:

Paper Session Description:

In this session we look at power optimization and telemetry features for SSD that have the potential to revolutionize the economics of data center operations. By optimizing the performance-to-power ratio through SSD controllers, data centers can achieve unparalleled levels of efficiency, resilience, and cost-effectiveness. Leveraging the latest advancements in controller design and NAND technology, data centers can unlock new levels of performance while minimizing their environmental footprint. This session will provide insights into the efficient design principles driving the next generation of storage solutions, and the pivotal role SSD controllers play in shaping the future of data center TCO.

01:25 PM to 02:30 PM

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Open AIML-304-1: Emerging Technologies for AI Chip and Generative AI Optimization

Ballroom B, Floor 1

Track: AI and ML Applications

Organizer + Moderator:

Russ Fellows, Head of Futurum Labs, Futurum Group

Russ brings over 25 years of diverse experience in the IT industry to his role at The Futurum Group. As a partner at Evaluator Group, he built the highly successful ;lab practice, including IOmark benchmarking. Prior to Evaluator Group he worked as a Technology Evangelist and Storage Marketing Manager at Sun Microsystems. He was previously a technologist at Solbourne Computers in their test department and later moved to Fujitsu Computer Products. He started his tenure at Fujitsu as an engineer and later transitioned into IT administration and management.

Paper Presenters:

Gary Grider, HPC Division Leader, Los Alamos National Laboratory

Gary Grider is the Leader of the High-Performance Computing (HPC) Division at Los Alamos National Laboratory (LANL). He is responsible for all aspects of high performance computing technologies and deployment. He also manages the R&D portfolio for providing HPC solutions to the Lab through funding of university and industry partners. Additionally, he is the US Department of Energy Exascale Storage, IO, and Data Management National Co-Coordinator, helping manage US government investments in data management, mass storage, and I/O. Gary has 30 active patents or applications in the data storage area and has been working in HPC and HPC related storage for over 30 years. Gary earned BSEE and MBA degrees at Oklahoma State University and has presented at many events, including the OpenFabrics Workshop, Usenix HotStorage Workshop, Storage Developer Conference, and past Flash Memory Summits.

Rohit Mittal, AI HW architect, Google

Rohit Mittal is Systems and Silicon Lead at Google, where he works on tensor processing units (TPUs) that power AI in Google. Before joining Google, he was director in Intel’s Cloud and Data Center Products Groups leading product development and management organizations for servers, silicon photonics and networking. He has deep expertise in AI, compute, interconnect, hyperscale, cloud and infrastructure technologies. Over the course of 25+ years Rohit held leadership roles as head of product development, as well as chief product officer. He earned an MSEE at Carnegie-Mellon University.

Trond Myklebust, CTO, Hammerspace

Trond Myklebust, co-founder and CTO, brings more than 20 years of experience with networked storage and Linux kernel development. As the maintainer and lead developer for the Linux kernel NFS client, Trond has nurtured the community to architect and develop several generations of networked filesystems. Before joining Hammerspace, Trond worked at NetApp and the University of Oslo. Trond also holds an MSc in quantum field theory and fundamental fields from Imperial College, London and worked in high-energy physics at the University of Oslo and CERN.

Raj Narasimhan, Senior VP and GM, Compute & Networking Business Unit, Micron

Andy Hsu, Founder & CEO, NEO Semiconductor

Paper Session Description:

Modern AI Chips have found a ‘killer app’ in generative AI (GenAI) and large language models (LLMs). Yet, innovation continues with new and emerging technologies driving product roadmaps and introductions at an accelerating pace. There are new chip architectures and software data architectures with standards-based parallel file systems to accelerate performance for AI. Led by an industry analyst, join invited speakers from influential processor, memory, generative AI companies, along with customers focused on AI as they present and discuss the hardware and software technologies driving the future of AI Chips and Generative AI customer implementations.

Open ACAD-304-1: Academic

GAMR 1 (Great America Meeting Room 1), Floor 2

Track: Academic

Organizer + Chairperson:

Joseph Wei, Director, IEEE

Joseph Wei is a Board member, IEEE Region 6 Director-Elect (2023-2024) Entrepreneurship, IEEE Santa Clara Valley Section. Chair, IEEE EMBS-SCV Treasurer, IEEE SFBA CTSoc Chapter

Paper Presenters:

Haocong Luo, PhD Student, SAFARI Research Group at ETH Zurich

Paper Title:

RowPress Vulnerability in Modern DRAM Chips

Paper Abstract:

RowHammer is a well-studied read-disturb phenomenon that significantly impacts system safety/security/reliability. This paper experimentally demonstrates and analyzes another read-disturb phenomenon, RowPress, in real DDR4 DRAM chips. RowPress breaks memory isolation by keeping a DRAM row open for a long period of time, causing bitflips in physically nearby victim cells. We show that RowPress amplifies DRAM's vulnerability to read-disturb attacks by significantly reducing the number of row activations needed to induce a bitflip by one to two orders of magnitude under realistic conditions. Our detailed characterization of 164 real DDR4 chips shows that RowPress 1) affects chips from all three major DRAM manufacturers, and 2) behaves differently from RowHammer as temperature and access pattern changes. We demonstrate that a user-level program induces bitflips in a real system much more effectively, in terms of the number of bitflips induced and the number of rows showing bitflips, using RowPress compared to conventional RowHammer. We discuss and analyze the implications of RowPress and propose a methodology to adapt DRAM read-disturbance mitigation mechanisms to mitigate RowPress.

Author Bio:

Haocong Luo is a PhD student in the SAFARI Research Group at ETH Zurich, advised by Prof. Onur Mutlu. His main research interests include the performance and reliability of memory systems, near (in) memory computing, and storage systems. Onur Mutlu is a Professor of Computer Science at ETH Zurich. He is also a faculty member at Carnegie Mellon University, where he previously held the Strecker Early Career Professorship. His current broader research interests are in computer architecture, systems, hardware security, and bioinformatics. A variety of techniques he, along with his group and collaborators, has invented over the years have influenced industry and have been employed in commercial microprocessors and memory/storage systems. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held various product and research positions at Intel Corporation, Advanced Micro Devices, VMware, and Google. He received the IEEE Computer Society Edward J. McCluskey Technical Achievement Award, the ACM SIGARCH Maurice Wilkes Award, the inaugural IEEE Computer Society Young Computer Architect Award, the inaugural Intel Early Career Faculty Award, US National Science Foundation CAREER Award, Carnegie Mellon University Ladd Research Award, faculty partnership awards from various companies, and a healthy number of best paper or "Top Pick" paper recognitions at various computer systems, architecture, and hardware security venues. He is an ACM Fellow "for contributions to computer architecture research, especially in memory systems", IEEE Fellow for "contributions to computer architecture research and practice", and an elected member of the Academy of Europe (Academia Europaea). His computer architecture and digital logic design course lectures and materials are freely available on YouTube, and his research group makes a wide variety of software and hardware artifacts freely available online. For more information, please see his webpage at https://people.inf.ethz.ch/omutlu/.

Geraldo Francisco De Oliveira Junior, PhD Candidate, ETH Zurich

Paper Title:

SimplePIM: A Software Framework for Productive & Efficient Processing-in-Memory

Paper Abstract:

Data movement between memory and processors is a major bottleneck in modern computing systems. The processing-in-memory (PIM) paradigm aims to alleviate this bottleneck by performing computation inside memory chips. Real PIM hardware (e.g., the UPMEM system) is now available and has demonstrated potential in many applications. However, programming such as real PIM hardware remains challenging for many programmers. To solve this issue, we present a new software framework, SimplePIM, to aid in programming real PIM systems. The framework processes arrays of arbitrary elements on a PIM device by calling iterator functions from the host and provides primitives for communication among PIM cores and between PIM and the host system. We implement SimplePIM for the UPMEM PIM system and evaluate it on six major applications. Our results show that SimplePIM enables a 66.5% to 83.1% reduction in lines of code in PIM programs. The resulting code leads to higher performance (between 10% and 37% speedup) than hand-optimized code in three applications and provides comparable performance in three others. SimplePIM is fully and freely available at https://github.com/CMU-SAFARI/SimplePIM.

Author Bio:

Paper Session Description:

This session highlights academic work from graduate students at ETH Zurich. RowPress is a newly discovered read-disturb phenomenon that poses a significant threat to system safety and security by breaking memory isolation in DDR4 DRAM chips. This phenomenon keeps a DRAM row open for an extended period, causing bitflips in nearby victim cells. A summary of mechanisms to counteract the impact of RowPress will be discussed. Data movement between memory and processors is a major bottleneck in modern computing systems. The processing-in-memory (PIM) paradigm aims to alleviate this bottleneck by performing computation inside memory chips. Real PIM hardware (e.g., the UPMEM system) is now available and has demonstrated potential in many applications. However, as programming such as real PIM hardware remains challenging for many programmers, this session will discuss a new approach to programming real PIM systems.

PRO AUTO-304-1: Vehicle to Everything NEW

Ballroom A, Floor 1

Track: Automotive Applications

Organizer + Chairperson:

Bill Gervasi, Principal Systems Architect, Wolley Inc

Paper Presenters:

Darren Lin, Product Marketing Manager, Silicon Motion

Paper Title:

Driving into the Future: Advancement of Automotive Storage Technology

Paper Abstract:

Along with the trend of autonomous and V2X technologies in the automotive industry, much more data and information are stored and transferred in future vehicles. This surge underscores growing need for automotive storage solutions with higher speed and capacity. Beyond data storage and transfer, security and safety emerge as critical focal points. As future vehicles are connected and have tons of data, ensuring the data is secured and safe is an important topic. In addition, future automotive architecture trend is migrating to domain and centralized architectures. To align with this evolving trends, the presentation will introduce advanced SSD technology which brings benefit for SSD resource allocation and enhances efficiency of information sharing in the vehicle.

Author Bio:

Darren Lin is the automotive product marketing manager at Silicon Motion. He has solid experiences in product marketing, planning and project management. He also has comprehensive knowledge and practical experiences in automotive development processes as well as certifications.

Chris Lien, Senior Manager, ATP Electronics

Paper Title:

Automotive V2X storage implementation

Paper Abstract:

V2X plays high important role in next generation of automotive, storage requirement in car will change accordingly. Audience would expect to learn what V2X standards have adopted, what is storage trend to implement and data/process security requests.

Author Bio:

Chris Lien is a BU Director at ATP Electronics Inc, where he leads product planning, marketing, and launching for NAND-based storage devices in automotive and industrial applications, including SSD/BGA Managed Storage. He focuses on long-term product strategy, team build-up, and new business engagement. He has over 20 years’ experience in the memory industry, and has worked on many successful OEM customers projects over his career.

Joe Ohare, Marketing Director, Everspin

Paper Title:

MRAM Enables Next Gen Energy-Efficient Compute in Automotive Applications

Paper Abstract:

MRAM has become the most prolific emerging memory in embedded applications and is set to enable next-generation energy-efficient compute at the edge including automotive applications. Whether intertwined with logic on the same chip or integrated as a wide I/O non-volatile working memory through heterogeneous packaging integration it enables instant on as well as power-fail protection and helps minimize data movement, the most energy-intensive part of compute. This overview provides new architectural choices including connectivity that are poised to advance automotive compute architectures.

Author Bio:

Joseph O'Hare has over 35 years of experience in the technology industry. Joseph began their career in 1985 at Texas Instruments, Inc. as an Engineering Manager of Memory Products, and then moved up to Business Unit Manager of Memory Products Division. In 1998, they joined Lucent Technologies, Bell Labs as a General Manager. In 2001, they joined Agere Systems, Inc. as Vice President and General Manager, and then was promoted to Executive Vice President and General Manager of the Storage Division. In 2010, they became an Adviser for Hie Electronics, and then in 2011 they joined Everspin Technologies as a Consultant, Director of Product Marketing, Director of Sales for North America East, and Senior Director of Marketing. Joseph O'Hare received a Bachelor of Science (BS) in Electrical and Computer Engineering from Clarkson University in 1978.

Durlov Khan, Product Engineer, Cadence Design System

Paper Title:

SPI NAND Flash Octal DDR verification challenges and solution

Paper Abstract:

Recently memory vendors added the Octal SPI interface to the SPI NAND Flash devices that enables 8-bit wide high bandwidth synchronous data transfers at manageable clock speeds. In several cases, the Octal SPI interface is combined with double data rate capabilities. The changes in device architecture and design have presented SoC validators with scant options for rapid and effective verification of the feature within the high-demand and high-volume automotive application space. Automotive SoC and Flash Controller Silicon IP requires a proven and reliable solution for the recent Octal DDR update to their controller. Cadence in partnership with Memory Vendor(s) crafted a solution to add Octal DDR Verification support. This paper delves into the implementation and usage details of this solution and demonstrates methods to verify Octal SPI NAND capabilities using a highly configurable user interface and Memory Model Advanced Verification (MMAV).

Author Bio:

After receiving his Bachelor of Science in Electrical Engineering from WPI in 2001 with a concentration in Hardware Security, Durlov spent five years as Consulting Engineer for Paradigm Works on projects at Avici, Mercury Computer Systems, Agere, and Intel, among others. He was a Senior Design Engineer at MIT startup Tilera Corporation, working on the next generation architecture of the multicore Tile Processor. Durlov received his Master of Science in Computer Science from Harvard University in 2008. Durlov joined Cadence Design Systems in 2008 as part of the Verification IP group focusing on Ethernet, before moving back into the Hardware Security space at AMD for the Microsoft Xbox One and the Sony Playstation 4 game console platform security processors. Most recently Durlov had moved to Intel to become Security Technical Lead for the Xeon server processors, from where he has returned to Cadence after about 12 years away. Today, Durlov leads the Product Engineering team for the Cadence Denali Memory Models and DFI VIP at Cadence Design Systems. He has published multiple conference papers at IEEE, ISLPED, ISQED and ISSCC. In his spare time, Durlov loves running, reading and spending time with his wife and two sons.

Paper Session Description:

As we drive into the future of automotive technology, advancements in storage solutions are key to meeting the demands of autonomous and V2X vehicles. With the increasing amount of data being stored and transferred in vehicles, higher speed and capacity are essential. Security and safety of this data are also critical considerations in this connected environment. The industry is moving towards domain and centralized architectures, and the presentation will highlight the benefits of advanced SSD technology in enhancing efficiency and resource allocation. Additionally, the adoption of CXL in automotive applications presents new opportunities for next-generation car designs. Stay ahead of the curve with the latest trends in automotive storage implementation and verification challenges. Explore how MRAM is revolutionizing energy-efficient computing in automotive applications, providing new architectural choices and connectivity options for future vehicles.

PRO DCTR-304-1: Enterprise Storage Part 2

Ballroom D, Floor 1

Track: Data Center Applications

Organizer + Chairperson:

Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft

Paper Presenters:

Sayali Shirode, Systems Performance Engineer, Micron Technology

Paper Title:

SSD Power efficiency for NoSQL Database

Paper Abstract:

Efficient power management in SSDs is crucial for mitigating environmental impact, reducing operational costs, and enhancing overall system sustainability. Ideally, we seek SSDs that deliver optimal performance while minimizing power consumption. This data is particularly useful when combined with real world application performance data because applications typically do a variety of block sizes and a mix of random and sequential input / output operations at any given time. This abstract explores power efficiency considerations in SSDs for the RocksDB NoSQL database. RocksDB is maintained by Meta and is a representative workload for cloud environments. This presentation will demonstrate the importance of power efficiency in a QoS focused application and the differences between a variety of PCIe Gen4 and Gen5 SSDs.

Author Bio:

Sayali received M.S. in Electrical and Computer Engineering from Colorado State University in 2015. She is currently a Storage Performance Engineer at Micron Technology, Inc. Sayali worked as Firmware Test Engineer prior to this role at Micron. She is currently focused on analyzing the performance for data center applications.

Krishna Kumar, Solutions Architect, Intel

Paper Title:

High availability Flash architecture using CXL

Paper Abstract:

High availability flash architectures require special hardware to synchronize flash arrays for access between multiple hosts. Flash modules require a single master and flash updates from one host cannot be synchronized to another without explicit side band signals. Architectures that require High availability, usually have 2 systems with one being primary system serving data and the other in standby mode waiting for takeover when the primary system fails. To keep both of them in sync, the redundancy related data is synchronized between the 2 using side band protocols. With advent of CXL, Flash architecture can be created with cache coherent CXL memory and flash controllers which provide online high availability with very little take over time and synchronization. The flash controller can provide CXL connectivity to 2 hosts providing a memory mapped interface for the flash array below along with offloading all caching to the device. When the primary system goes down, the secondary system can take over R/W client requests with minimal downtime as the cache updates are hot and already accessible to the secondary host and vice versa.

Author Bio:

A solutions architect working on multiple domains like telecom and storage, providing innovative solutions for solving customer needs.

Paper Session Description:

In the world of NVMe Over CXL, the game-changing CXL protocol revolutionizes controller memory buffers. By overcoming the limitations of PCIe bus, CXL enables efficient memory accesses with CXL.mem protocol while maintaining legacy NVMe functionalities with CXL.io protocol. SSDs utilizing NVMe Over CXL offer significant advantages, particularly in resolving race conditions through storage and memory integration. Additionally, the merging of storage and memory in High availability flash architectures using CXL results in online high availability with minimal takeover time and synchronization. Power efficiency in SSDs is crucial for optimizing performance and reducing environmental impact, particularly in applications like RocksDB NoSQL database.

PRO INVT-304-1: Invited Talk with David Flynn

Ballroom F, Floor 1

Track: Invited Talks

Organizer + Chairperson:

Leah Schoeb, Sr. Developer Relations Manager, AMD

Paper Presenters:

David Flynn, CEO, Hammerspace

Paper Title:

Advancing Infrastructure and Storage Standards in AI Architectures

Paper Abstract:

In the landscape of artificial intelligence, architectural complexities of large-scale computing - spanning hundreds to thousands of processors and storage nodes, accessed by a myriad of researchers for debugging and code adjustments - present a formidable challenge. Yet, it is within these environments that the future of AI is being forged. Central to unlocking this potential is embracing open standards, which empower enterprises to harness specialized capabilities previously reserved for Hyperscaler and High-Performance Computing (HPC) environments. This session illuminates the pioneering advancements spearheaded by Meta and Hammerspace in revolutionizing the parallel network file system (NFS), a cornerstone for AI endeavors. Our focus zeroes in on contributions to the Linux NFS kernel, incorporating robust data protection mechanisms into the pNFS with the FlexFiles NFS client. These enhancements are not merely technical milestones; they represent a leap forward in enabling unparalleled data protection, alongside parallel and shared data access across any Linux client and storage node. 2nd Speaker: Paul Saab: Meta, Software Engineer

Author Bio:

Hammerspace co-founder and Chief Executive Officer David Flynn is a recognized leader in IT innovation who has been architecting disruptive computing platforms since his early work in supercomputing and Linux systems. David pioneered the use of flash for enterprise application acceleration as founder and former CEO of Fusion-io, which was acquired by SanDisk in 2014. He served as Fusion-io President and CEO until May 2013 and board member until July 2013. As Fusion-io CEO, David was responsible for the company's strategic direction, oversaw all operations and was the visionary behind the company's innovative technology and market strategy. Preceding his position as CEO, David was Fusion-io technical found and CTO, where he created the company's foundational research and development efforts, as well as the development of short- and long-term technological roadmaps. Previously, David served as Chief Architect at Linux Networx where he was instrumental in the creation of the OpenFabrics stack and designed several of the world's largest supercomputers leveraging Linux clustering, InfiniBand, RDMA-based technologies. Also, David served as Project BlackDog's Chief Scientist and Vice President of Engineering. He has also held positions Network Computer, Inc. and Liberate Technologies, a spin-off of Oracle Corporation, developing thin-client solutions. David holds more than 100 patents in areas across web browser technologies, mobile device management, network switching and protocols to distributed storage systems. He earned a bachelors degree in computer science at Brigham Young University and serves on boards for several organizations and startup companies.

Paper Session Description:

In the landscape of artificial intelligence, architectural complexities of large-scale computing - spanning hundreds to thousands of processors and storage nodes, accessed by a myriad of researchers for debugging and code adjustments - present a formidable challenge. Yet, it is within these environments that the future of AI is being forged. Central to unlocking this potential is embracing open standards, which empower enterprises to harness specialized capabilities previously reserved for Hyperscaler and High-Performance Computing (HPC) environments. This session illuminates the pioneering advancements spearheaded by Meta and Hammerspace in revolutionizing the parallel network file system (NFS), a cornerstone for AI endeavors. Our focus zeroes in on contributions to the Linux NFS kernel, incorporating robust data protection mechanisms into the pNFS with the FlexFiles NFS client. These enhancements are not merely technical milestones; they represent a leap forward in enabling unparalleled data protection, alongside parallel and shared data access across any Linux client and storage node

PRO OPSW-304-1: AI Open-Ecosystem NEW

Ballroom C, Floor 1

Track: Open Source Software

Chairperson + Speaker:

Prasad Venkatachar, Solutions Director, Pliops

Organizer:

Javier Gonzalez, Principal Software Engineer, Samsung Electronics

Paper Presenters:

Yann Collet, Lossless Compression Open Source Lead, Meta

Yann Collet is currently Tech Lead of Data Compression at Meta, He is in charge of developing, maintaining, and supporting the deployment of lossless data compression solutions across both Infrastructure and Clients. In the open-source community, Yann is better known for the development of LZ4 and Zstandard, two lossless data compression algorithms frequently used in data centers.

Eric Kern, Distinguished Engineer and AI COE Lead, Lenovo

Eric Kern is a Distinguished Engineer and Executive Director at Lenovo. I have been working with Lenovo for the last 8 years.. He is founding member of Lenovo’s AI Center of Excellence and lead a team of AI engineers at Lenovo. He holds 125 patents in ground-breaking technologies in data storage, testing, machine efficiency in cloud computing environments, and many other technologies. He has more than 28 years of experience in High Tech including roles at Lenovo, IBM, and founder and CTO at Amari.ai startup.

Akshay Subramaniam, Senior AI Developer, NVIDIA

Akshay Subramaniam is a Senior AI Developer Technology Engineer at NVIDIA. He has been working on problems at the intersection of physics and deep learning. He has also been working on algorithm development and performance optimization in deep learning, machine learning and data compression applications on the GPU. He is a core developer of the Modulus and nvCOMP software packages and deeply involved with the Earth-2 initiative. Prior to working at NVIDIA, Akshay got his PhD from Stanford University working on problems in turbulent flows, computational physics, numerical algorithms, high performance computing and deep learning.

Nilesh Shah, VP, Business Development, ZeroPoint Technologies

Paper Title:

Enabling AI Advancements with Open Source Storage Accelerators

Paper Abstract:

The explosion of AI deployments and accelerators at Hyperscale has given rise to "FOMO" arms race to deploy AI clusters at Hyperscale, typically outfitted with hundreds of thousands of GPUs, interconnected via a mix of proprietary and standardized, open links to achieve near linear scaling. To feed these hyperscale clusters, streaming data from storage devices is the "genesis block" for AI training and inference. Hyperscalers have reported relatively low utilization of precious compute Accelerator / GPU resources when clustering at scale interconnecting accelerators with memory and storage pools. The industry has responded via a mix of proprietary and open source data/memory compression, networking and chiplet innovations as well as custom accelerators distributed across processors, storage and memory. We discuss the role of open source solutions to bring diverse components together, remove adoption barriers and ease programming paradigm shifts by integration into upstream kernel code.

Author Bio:

Sandy Ghai, , Google Cloud

Paper Session Description:

Join us as we explore the future of AI technology in this exciting session. We begin with an in-depth exploration of the impact of Open Source LLMs and Vector Databases on Generative AI. We dive into the world of building Gen AI applications from scratch, including prompt engineering and fine tuning and learn how to maximize performance and accuracy with open-source vector databases. We will discover the crucial design parameters for storage accelerators in AI clusters, and the role of open source solutions in driving innovation. Lastly we will look at open source ecosystems for GenAI.

PRO QLCP-304-1: QLC and PLC

Ballroom E, Floor 1

Track: QLC and PLC

Organizer + Chairperson:

Brian Berg, President, Berg Software Design

Paper Presenters:

David Verburg, SSD/HDD Sr Technical Staff Member, IBM

Paper Title:

Will QLC SSDs Displace Near-Line Hard Disk Drives?

Paper Abstract:

There has been a lot of hype around SSDs displacing Hard Disk Drives (HDDs) for several years, and indeed it has happened in some areas - but when will it happen with Near-Line HDDs? This talk will examine some of the factors needed to make the transition, including retention, reliability, density, and cost. We will also look at some of the industry trends that could accelerate or delay the transition, along with workloads or customer use cases that may transition sooner because of factors that are favorable to leveraging QLC workloads.

Author Bio:

Dave Verburg is a Senior Technical Staff Member at IBM responsible for storage device strategy and quality. He has been with IBM since 1991, starting in disk drive manufacturing, and spending the last 15 years of his career working with HDD and SSD quality and technology. Dave has presented to IEEE, at conferences including FMS, and at the Manufacturing Leadership Council while receiving an ML100 award in 2019. Dave received a MS in Electrical Engineering from the University of Minnesota in 1996 and received a BS in both Electrical Engineering and Computer Science from the South Dakota School of Mines and Technology in 1991. Dave is an active volunteer, helping with computer systems and mentoring for the youth at his church and teaching robotics to school children. Dave also can speak both Spanish and Mongolian and uses his language skills to help Samaritan's Purse Children's heart project as they provide life changing surgery for children.

Wei Min Lai, Project Deputy Manager, Silicon Motion

Paper Title:

Advancing QLC NAND Flash: Innovations and Challenges

Paper Abstract:

This presentation explores the dynamic landscape of QLC NAND Flash technology, delving into its current state and future prospects. We elucidate the characteristics of present QLC implementations, focusing on their structure and operational features. Furthermore, we examine the intricate relationship between capacity and read/write performance, particularly in specialized applications, and strategies to optimize performance while maximizing storage capacity. Additionally, we investigate various program schemes and associated Power Loss Protection (PLP) technologies to enhance data integrity and reliability. We also address the critical challenge of reducing error recovery latency on QLC, presenting innovative approaches to mitigate latency issues and improve system efficiency. This was redirected by Eric Haratsch to this Track, and I then accepted the talk.

Author Bio:

Wei-Min Lai holds a Ph.D. in Electrical Engineering from National Tsing Hua University in Taiwan, specializing in error correcting codes and wireless communication systems. Being a member of the Storage Research Department at Silicon Motion, he focuses on solving NAND reading issues, developing retry strategies, analyzing NAND flash characteristics and optimizing read/write task performance to advance storage solutions.

Bill Panos, Product Marketing Manager, Solidigm

Paper Title:

QLC in the Datacenter: Making the Optimal Choices

Paper Abstract:

As data centers are evolving to handle a wider range of workloads - including big data analytics, machine learning, and artificial intelligence - the demand for cost-effective, high-capacity storage solutions continues to grow. This talk will discuss why QLC SSDs continue to advance by helping solve many of these memory storage bottlenecks. Several areas will be reviewed, including reliability, cost efficiency, evolving workload requirements, and vendor acceptance/readiness. This analysis is intended to help those who architect and deploy datacenter infrastructures, and will help them make optimal choices for their storage needs. Original title: "The Unavoidable Appeal of QLC: Why It Is Now Entering the Mainstream"

Author Bio:

Bill Panos serves as Solidigm’s Product Marketing Manager for the D5-P5430 data center product since 2021. Prior to joining Solidigm, Bill held the role of program management of data center SSDs at Micron as the Business Line Manager within the mainstream NVMe SSD portfolio. He has been in the memory and storage business for over 13 years. He has B.S. degree in chemistry from UC Davis and an M.S. in Electrical Engineering from San Francisco State University.

Javier Gonzalez, Principal Software Engineer, Samsung Electronics

Paper Title:

Enabling New Use Cases with High-Capacity QLC SSDs

Paper Abstract:

QLC NAND is gaining mainstream acceptance in cloud and enterprise environments. While past NAND technology evolution resulted in a high percentage of turnover (i.e., SLC to MLC to TLC), the characteristics of QLC makes it suitable to cover new use cases involving High-Capacity SSDs. It has also prompted the opportunity to enhance QLC adoption further. In order to transparently enable these SSDs in existing applications, we need changes at the operating system level. In this talk, we will present the three main challenges when introducing QLC-based High-Capacity SSDs in existing applications: Scalability, Endurance and Performance. We will report how we are preparing the ecosystem to address these challenges using open standards and open-source. Specifically, we will cover our progress on (i) enabling and enhancing QLC drives with larger Indirection Units (IUs) by supporting larger block sizes, (ii) increasing QLC endurance through Flexible Data Placement (FDP), and (iii) improving performance in mainstream databases by leveraging the atomicity associated with larger IUs.

Author Bio:

I lead Samsung Memory Solutions' Global Open-Source Team (GOST), where I take care of our open-source activities and manage a distributed team of highly talented engineers. This includes defining our vision, strategy, internal / external communication, and day-to-day execution. I am also the founder and site manager for Samsung Semiconductor Denmark Research (SSDR) - Samsung’s Memory Solutions first R&D center in Europe and fifth worldwide. I am a Ph.D in operating systems with a strong background in technical leadership, experimental research, and Linux Kernel development. My interests lay primarily in the hardware / software co-design space, where systems, hardware architecture, and open-ecosystem meet. I am dedicated to defining safe environments for motivated software engineers to be creative and get things done. I am a contributor to a wide range of open source projects including the Linux Kernel, as well as to the NVMe Specification. I am a regular speaker at several top industry and academic conferences.

Paper Session Description:

In the fast-evolving world of storage technology, the question of whether QLC SSDs will eventually displace Near-Line HDDs is a hot topic. This session will delve into the factors influencing this transition, such as retention, reliability, density, and cost. Industry trends and customer use cases will also be explored to determine when this shift may take place. We will highlight the innovations and challenges of QLC NAND Flash technology, including capacity optimization, performance enhancement, and data integrity. Lastly, the session will address how QLC SSDs are enabling new use cases in cloud and enterprise environments, as well as the strategic choices data center architects can make to leverage QLC technology effectively in their infrastructure.

PRO SSDT-304-1: New Form Factors and Interfaces for SSDs

Ballroom G, Floor 1

Track: SSD Technology

Organizer + Chairperson:

Erich Haratsch, Senior Director Architecture, Marvell

Panel Members:

Ilya Cherkasov, Sr. Product Manager, Enterprise SSD, KIOXIA America, Inc.

Ilya Cherkasov has been an SSD product line manager, performance analyst, and technical marketing manager for the past 10 years.

Carlos Franco, Principal Engineer, Micron

Principal Engineer, Signal and Power Integrity Research Group

Tahmid Rahman, Product Marketing Director, Solidigm

Product/Technical Marketing Professional with experience in disruptive technology driven innovation. Key player in a technical marketing/product development team to meet customer and end user demands with strong customer orientation, strategic planning and leadership skills.

Kenichiro Yoshii, Staff Engineer, Hagiwara Solutions

Kenichiro Yoshii is a Principal Engineer in the Core Technology Development Group at Hagiwara Solutions. He started his carrier working on NAND flash memory based SSD at Toshiba, where he was in charge of designing many products over 10 years including the company’s first-generation enterprise SSD. He joined Hagiwara Solutions in 2019, and his current role involves R&D of advanced SSD technology. He earned BE and ME from Waseda University, Japan.

Panel Session Description:

This session discusses new form factors and interfaces for SSDs. As use cases evolve, the need for differentiated SSD solutions becomes apparent. From data centers to edge applications, SSDs must be tailored to meet specific demands, offering enhanced endurance and intelligent telemetry. The E3.S form factor is reshaping the landscape for NVMe applications, offering superior performance and density over traditional 2.5" drives. The advent of PCIe Gen6 brings new challenges for SSD deployment, requiring careful electrical validation and testing to ensure optimal performance at scale. CFexpress 4.0, utilizing PCIe 4.0 and NVMe 1.4, has revolutionized the high-end camera market with its impressive bandwidth capabilities. But its potential extends beyond photography, making waves in the industrial sector.

02:40 PM to 03:40 PM

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Open SPEC-305-1: Memory-Intensive Storage Solutions for AI: Pushing the Limits !!!

Ballroom G, Floor 1

Track: AI and ML Applications

Organizer + Chairperson:

Jean Bozman, President, Cloud Architects Advisors

Panel Session Description:

Description Not Available