Speaker List - FMS: the Future of Memory and Storage

Speaker List

Speaker	Affiliation	Title
Wayne Adams SNIA Chairman Emeritus SNIA	SNIA	SNIA Chairman Emeritus
Wednesday @ 03:15 PM: Energy Efficiency In this session, we will delve into the critical intersection of energy consumption, technological advancement, and environmental sustainability within the rapidly evolving landscape of AI and data infrastructure. As AI applications and cryptocurrency mining drive significant increases in global energy demand, the pressure on data centers to prioritize power efficiency has never been greater. Presentations will explore the intricate balance between performance and energy efficiency, focusing on advancements in CPU, GPU, and memory technologies, as well as innovative data center designs that optimize power usage. We will discuss the implications of these power consumption trends on environmental sustainability, highlighting strategies for mitigating the impact of technology on climate change. Additionally, we will examine emerging SSD form factors and server innovations aimed at achieving high-density performance while minimizing energy use. This session will provide a comprehensive overview of how industry leaders are spearheading efforts to align technological progress with ecological responsibility, ensuring that digital transformation contributes positively to a sustainable future. Thursday @ 12:10 PM: Sustainable Data Centers In this dynamic session, we explore the intersection of sustainability and technological advancement within the storage industry, highlighting emerging practices and strategic innovations. As AI propels the growth of power-intensive systems, the need for sustainable storage solutions becomes paramount. Presentations will delve into sustainable measures for HDD and SSD, emphasizing energy-efficient production, operation, and end-of-life strategies, with a focus on the circular economy. Data centers are encouraged to adopt a holistic, lifecycle-oriented approach to enhance sustainability without compromising performance, underscoring the importance of consolidating storage arrays. The session will also spotlight the Circular Drive Initiative's upcoming Data Sanitization Best Practices Guide, which provides essential guidance on balancing security, compliance, and sustainability for enterprise drive reuse. Attendees will gain insights into the latest tools and methodologies for secure, sustainable drive reuse, ultimately reducing e-waste and fostering a more circular economy. Wayne Adams has over 35 years of IT industry experience spanning business development, technical product/solution management, and partner ecosystems. Wayne has been involved in SNIA leadership roles since 2002. Wayne has served on the SNIA Board of Directors since 2003 including roles as Chair, Chair Emeritus, Treasurer in addition to a number of leadership roles for forums and initiatives, conferences, and strategic alliances. He has spoken at numerous industry forums and events. Over his career, Wayne M. Adams was a Senior Technologist and Director of Standards within the Office of the CTO at EMC, technical alliances partner manager, and a manager of product managers for its portfolio of SRM products. Prior to EMC, Wayne was responsible for product marketing and business development for several strategic software and hardware products at Digital Equipment Corporation. He started his high-tech career at Eastman Kodak as a system designer of real-time control systems. Wayne has been involved in many industry associations including serving on the DMTF Board of Directors, serving as Advisory Committee member of W3C, contributing to the Industrial Internet Consortium for IoT/big data test-beds, leadership of the Fibre Alliance, and participating with various committees within INCITS, OASIS, Cloud Security Alliance, and TheGreenGrid. Wayne holds a Bachelor of Science degree with a dual major in Computer Science and Mathematics from the University of Pittsburgh.
Richelle Ahlvers Vice Chair SNIA	SNIA	Vice Chair
Wednesday @ 03:15 PM: SNIA Technical Activities Come hear about all of the developments in SNIA technical activities and our communities. You will learn how SNIA is working together with other industry organizations to enable higher performance for AI applications. Hear updates on what is going on in the areas of DNA data storage for long term data retention, Cloud Object Storage to provide for better interoperability of cloud applications with cloud service providers, and Connectors and Form Factors to support 400G. Also hear from our communities that provide education in the areas of SCSI, Storage Management, Green, Compute, Storage, and Persistent Memory. You will get a brief taste of all the work that is going on and an invitation to join us in our technical work groups to participate. Richelle Ahlvers runs Technology Initiatives and Ecosystem Enabling for the Datacenter / AI business for Intel, promoting and driving enablement of new technologies and standards strategies. Richelle has spent over 30 years in Enterprise R&D teams in a variety of technical roles, spanning architecture, design and development of software, firmware, and hardware, for everything from enterprise storage solutions to CPUs. Richelle has been engaged with industry standards initiatives for many years and is actively engaged with many groups including SNIA, DMTF, NVMe, OFA and UCIe. She is Vice-Chair of the SNIA Board of Directors, Chair of the Storage Management Initiative, leads the SSM Technical Work Group developing the Swordfish Scalable Storage Management API, and is a former SNIA Technical Council Chair. She serves on the DMTF Board of Directors as the VP of Finance and Treasurer.
Mike Allison Senior Director - NAND Product Planning - Standards Samsung	Samsung	Senior Director - NAND Product Planning - Standards
Tuesday @ 09:45 AM: Hyperscale Applications 2 This session delves into the forefront of storage technology, highlighting innovations and challenges in the realm of data management. The presentations collectively explore the evolving landscape of storage solutions, from cutting-edge NVMe mechanisms that enhance live migration transparency in virtual environments, to breakthroughs in flash storage that address the complexities of hyperscale operations. Central themes include the drive for increased efficiency, reliability, and performance, underscored by a need to navigate the inherent trade-offs of advanced storage systems. Attendees will gain insights into overcoming latency issues, optimizing endurance, and managing workload variability, equipping them with strategies to leverage these innovations for enhanced data management and operational excellence. Mike Allison is a Sr. Director in the Samsung DSA Product Planning team focusing on standards for existing and future products. Mike is active in the many standards organizations that includes SNIA, NVM Express™, PCI Express™, DMTF, and OCP. He is the chair of the NVM Express Errata Task Group and the Representative on the OCP Steering Committee for the OCP Storage Project. He was the main author of the NVM Express TP4159 PCIe Infrastructure for Live Migration and TP4193 PCIe NVM Export Subsystem Migration which are associated with his presentation. For over 41 years, Mike has been an embedded firmware engineer and architect working on products for laser beam recorders, fighter aircraft, graphics cards, high end servers, and is now focusing on Solid State Drives. He holds 35 patents in graphics, servers, and storage. He has earned a BSEE/CS at University of Colorado, Boulder.
Ju Jin An Senior Technical Staff Member IBM	IBM	Senior Technical Staff Member
Wednesday @ 03:15 PM: DRAM: Future Research In this insightful session, we delve into innovative advancements in DRAM and hybrid storage systems aimed at addressing critical challenges in performance, cost, and security. From Chronus, a mechanism enhancing the state-of-the-art RowHammer solution by reducing performance overhead and fortifying against wave attacks, to Harmonia's reinforcement learning approach optimizing data placement and migration in Hybrid Storage Systems, these presentations highlight the integration of cutting-edge technology for efficiency. Sectored DRAM introduces a low-overhead technique for fine-grained data transfers, promoting energy efficiency and high performance, while Self-Managing DRAM shifts maintenance responsibilities in-DRAM to accelerate architectural adoption. Additionally, addressing the fluctuating read disturbance threshold in modern DRAM chips, the session underscores the need for robust profiling mechanisms to enhance security. Collectively, these innovations signify strides toward more reliable, efficient, and secure memory systems for future technological landscapes. Thursday @ 08:30 AM: 3D DRAM Technology Now and Future This session explores the forefront of memory technology advancements with a focus on High Bandwidth Memory (HBM) and its pivotal role in meeting the increasing demands of AI and semiconductor applications. The presentations converge on the innovative strides being made in HBM, emphasizing the transition to more complex stacking configurations—8hi to potentially 20hi—enabled by cutting-edge techniques like TSV and hybrid bonding. With an eye on enhancing bit density and packaging efficiency, the talks highlight the criticality of thermal, latency, and power characterization, underscoring the importance of architecture in optimizing performance. The discussions also delve into the implications of 2.5D and 3D architectures, especially in the context of AI SoCs, where HBM4 is poised to redefine bandwidth capabilities. Complementary to these developments is the evolution in DRAM technology, as it embraces three-dimensional designs through nanosheet transistors and innovative patterning strategies, promising further integration and efficiency. Attendees will gain a comprehensive understanding of how these advancements collectively drive the future of memory technologies, addressing the needs of burgeoning AI models and semiconductor innovations. Thursday @ 09:45 AM: HBM: DRAM's Bright Future This session delves into the rapidly evolving landscape of memory technologies in the context of AI and high-performance computing, highlighting the interplay between existing standards and emerging innovations. A common theme across presentations is the transformative role of High Bandwidth Memory (HBM) in fueling the AI boom, with both its robust growth and impact on the DRAM market thoroughly examined. Discussions underscore the significant influence of AI processor architectures on memory access, particularly in light of developments in quantization and sparsity. The session explores the promise of novel techniques such as in-memory and near-memory computing, alongside the critical importance of addressing sustainability and energy consumption. Key insights into market dynamics, including future forecasts and supply chain implications, offer a comprehensive view of how these memory technologies are set to redefine the industry. From 3D DRAM advancements to potential processing-in-memory innovations, this session provides a forward-looking perspective on how these technological inflections will shape the future of memory and processor interactions. Thursday @ 12:10 PM: High Performance DRAM Technology In a rapidly evolving technological landscape, the search for efficient, high-performance memory solutions has never been more critical, as highlighted by recent advancements in memory technologies. This session explores the intersection of power efficiency and performance enhancement across various high-demand environments, from data centers to edge computing. Presentations showcase the transformative potential of Low-Power DDR memory, as exemplified by the NVIDIA GH200 platform, which integrates LPDDR5X to optimize power and performance in high-performance computing (HPC) workloads. Similarly, the emergence of Multiplexed Rank DIMMs (MRDIMMs) addresses the growing memory bandwidth demands posed by AI and real-time analytics, offering substantial improvements in latency and scalability despite their power requirements. Furthermore, the transition to GDDR7 memory, developed collaboratively by Rambus and Cadence, provides a pathway for handling the escalating bandwidth needs of AI/ML inference models at the edge. Finally, the innovative IO-DIMM architecture presents a compelling alternative to traditional PCIe and CXL interfaces, delivering low-latency, power-efficient near-memory processing suitable for AI and real-time data applications. Together, these advancements underscore a common theme: the relentless pursuit of memory technologies that not only meet the demands of modern applications but also push the boundaries of power efficiency and performance. Thursday @ 01:25 PM: DRAM and NAND Technology Deep Dive In the rapidly advancing landscape of artificial intelligence and high-performance computing, the demand for reliable and efficient memory systems is more critical than ever. This session delves into the intersection of cutting-edge memory technologies and AI-driven applications, highlighting common themes such as memory reliability, scalability, and innovation. Presentations will explore the challenges of DRAM and NAND failures in AI applications, emphasizing the importance of error correction and system-level optimizations to enhance memory resilience. The session will also examine the latest advancements in DRAM technologies, including processing-in-memory (PIM) and hybrid bonding, which promise to enhance performance and reduce data movement inefficiencies. Furthermore, the emergence of new memory tiers like CXL addresses increasing memory capacity demands, albeit with challenges in energy consumption and software complexity. Attendees will gain insights into the transformative potential of 3D DRAM, high-bandwidth memory (HBM), and second-tier memory solutions, which are poised to redefine the landscape of memory architectures essential for the next wave of AI and data-intensive applications. Ju Jin An is a Senior Technical Staff Member in IBM's Infrastructure Supply Chain Organization. Ju Jin has a background in silicon fabrication process R&D and manufacturing process integration through 20 years of career in the semiconductor industry. She is responsible for enabling memory sub-system for IBM power and z system. She holds a MS/Ph.D. degree in Chemical Engineering from MIT and a BS from Seoul National University.
Pravallika Anchuri Senior Applications Engineer Synopsys	Synopsys	Senior Applications Engineer
Tuesday @ 08:30 AM: Hardware Trust Building Blocks for Secure Systems In an era marked by escalating cybersecurity threats, our session delves into the transformative strategies reshaping data security across memory and interconnect technologies. The presentations collectively spotlight a paradigm shift towards hardware-anchored and community-driven security models, emphasizing the integration of AI and post-quantum cryptography to fortify data integrity and confidentiality. Central to this evolution is the implementation of Security Protocol and Data Model (SPDM) standards, alongside Secure Boot and Measured Boot mechanisms, which are increasingly becoming mandatory across memory and controller technologies. The sessions explore advanced encryption protocols such as Integrity and Data Encryption (IDE) and Transaction Layer Packet (TLP) security measures, highlighting their roles in countering physical attacks and ensuring data resilience against corruption and unauthorized access. Through collaborative efforts like the Community Root of Trust and industry-wide standardization initiatives, these presentations advocate for a future where security is embedded at the silicon level, paving the way for a fortified digital infrastructure ready to meet tomorrow’s challenges. Pravallika Anchuri – Senior Applications Engineer, Synopsys, Inc. Pravallika Anchuri is a Senior Applications Engineer at Synopsys, specializing in hardware verification and emulation workflows. She has hands-on experience with PCIe bring-ups, utilizing virtual host solutions and speed adapters to validate and optimize system performance. Her background includes work on PCIe and CXL link validation, focusing on LTSSM state analysis and Gen6 configuration. Pravallika holds a Master’s degree in Electrical Engineering and brings expertise in RTL design, SystemVerilog verification, and a wide range of EDA tools.She is known for her problem-solving abilities and her contributions to high-performance hardware development environments.
Eric Anderson Director of Data Science R&D Lam Research	Lam Research	Director of Data Science R&D
Thursday @ 08:30 AM: Data Analytics This session explores the innovative intersections of AI, data management, and technology scalability, highlighting the transformative impact of strategic resource optimization across industries. A recurring theme is the disentanglement of traditional system architectures, as seen in the separation of compute and storage to enhance query performance in AI analytics, and the development of a Data Eco-System at SK hynix for superior SSD quality management. These strategies underscore the importance of modular, scalable systems capable of addressing the growing demands of modern data centers and AI applications. Additionally, the session delves into the role of AI in centralizing and optimizing talent data management, as exemplified by One Resume's integrated system that harmonizes professional profiles for improved connectivity. Further expanding on the theme of efficiency and scalability, the semiconductor industry's shift towards three-dimensional logic illustrates the necessity of human-machine collaboration to navigate increased process complexity and drive rapid innovation. Together, these presentations offer a comprehensive view of how decoupled architectures and AI-driven solutions are reshaping the landscape of data storage, talent management, and technological advancement. I head the data science organization within the Semiverse(r) Solutions organization within Lam Research. We develop machine learning solutions for process development, AI/Physical model hybrid models, and deep learning models for a variety of semiconductor specific applications.
Khayam Anjam Sr Systems Performance Engineer Micron	Micron	Sr Systems Performance Engineer
Thursday @ 12:10 PM: High Performance DRAM Technology In a rapidly evolving technological landscape, the search for efficient, high-performance memory solutions has never been more critical, as highlighted by recent advancements in memory technologies. This session explores the intersection of power efficiency and performance enhancement across various high-demand environments, from data centers to edge computing. Presentations showcase the transformative potential of Low-Power DDR memory, as exemplified by the NVIDIA GH200 platform, which integrates LPDDR5X to optimize power and performance in high-performance computing (HPC) workloads. Similarly, the emergence of Multiplexed Rank DIMMs (MRDIMMs) addresses the growing memory bandwidth demands posed by AI and real-time analytics, offering substantial improvements in latency and scalability despite their power requirements. Furthermore, the transition to GDDR7 memory, developed collaboratively by Rambus and Cadence, provides a pathway for handling the escalating bandwidth needs of AI/ML inference models at the edge. Finally, the innovative IO-DIMM architecture presents a compelling alternative to traditional PCIe and CXL interfaces, delivering low-latency, power-efficient near-memory processing suitable for AI and real-time data applications. Together, these advancements underscore a common theme: the relentless pursuit of memory technologies that not only meet the demands of modern applications but also push the boundaries of power efficiency and performance. I am a Sr. Systems Performance engineer at Micron working on characterizing AI workloads in a datacenter environment.
Bryan Ao Analyst TrendForce	TrendForce	Analyst
Thursday @ 09:45 AM: Storage for AI: Markets and Technologies This session delves into the transformative impact of AI on the storage and connectivity landscape, highlighting the critical role of NAND Flash, SSDs, and PCIe technologies in meeting increasingly complex AI-driven demands. As AI workloads evolve, they necessitate rapid data transfer, high-performance storage solutions, and innovative interconnect strategies to manage massive datasets effectively. Presentations underscore the pivotal advancements in NAND technology that cater to AI's escalating performance needs, including the emergence of PCIe Gen6 and storage-class memory technologies poised to revolutionize market dynamics. The strategic interplay between AI accelerators, enterprise SSDs, and PCIe switches is dissected to reveal how these elements collectively enhance storage efficiency, scalability, and power performance. Attendees will gain insights into the supply-demand dynamics, pricing trends, and strategic maneuvers by industry leaders, equipping them with the foresight to navigate the next wave of technological innovation in AI-centric environments. • TrendForce Research Manager Bryan Ao focuses on demand trends of NAND Flash storage solutions used by server OEMs, data center operators, and AI or edge computing service provider. He previously worked in an electronic component distributor specializing in mobile device memory solutions and SSD controller ICs.
Paul Armijo President and CEO Armijo Innovations	Armijo Innovations	President and CEO
Wednesday @ 09:45 AM: Aerospace and Outer Space Data This session delves into the intricate challenges and innovative solutions surrounding data storage and micro-electronic systems in the demanding environment of outer space. Common themes across the presentations include the resilience and longevity of storage systems, particularly solid-state drives (SSDs), amidst the harsh conditions of space such as intense radiation and extreme temperature fluctuations. Emphasis is placed on the integration of hardware, firmware, and software tools to enhance error correction and self-healing capabilities, ensuring data reliability and device durability. The session also explores the latest advancements in radiation-tolerant materials and the evolving business landscape of space micro-electronics, highlighting opportunities for future developments, including the ambitious concept of data centers on the moon. Through expert insights and a panel discussion, this session provides a comprehensive overview of current technologies, their limitations, and the potential for groundbreaking advancements in space data storage. Paul Armijo is the President & CEO at Armijo Innovations. He has senior leadership in roles including CTO in space and technology development industry at General Dynamics Mission Systems, Northrop Grumman, BAE Systems Space & Mission Systems, Frontgrade Technologies, GSI Technology, Secure Quantum Services, and Avalanche Technology. He has had the privilege of leading numerous flagship programs and technology development efforts over his career to further enable the space community. He has served various technical and session chairs as well as presented at various conferences in the space, memory, and AI community like SEE/MAPLD, ODSC, SPWG, HEART, NSREC, Space Computing, RHET, among many others. Paul received his B.S. in electrical engineering from Arizona State University.
Heetashi Arora Lead Member Consulting Staff Siemens EDA	Siemens EDA	Lead Member Consulting Staff
Thursday @ 01:25 PM: CXL Verification This session delves into the intricacies of Compute Express Link (CXL) technology, focusing on the critical aspects of error handling, data integrity, and security. Across multiple presentations, the common themes emerge around enhancing CXL's reliability, availability, and serviceability (RAS) through innovative firmware solutions and protocol enhancements. The discussions outline the implementation of Firmware First error handling, highlighting the use of GUID and UUID in error notification and the challenges of maintaining low SMI latency in a complex ecosystem. The session also explores the introduction of Extended Meta Data (EMD) in the CXL 3.1 specification, addressing the limitations of previous encoding schemes and proposing comprehensive verification strategies to ensure robust error reporting and interaction with features like Late-Poison. Furthermore, the session addresses the verification challenges associated with CXL Integrity and Data Encryption (CXL IDE) and Trusted Service Providers (TSPs), emphasizing the importance of coherence, access control, and encryption in maintaining secure and efficient CXL operations. Collectively, these presentations offer a nuanced perspective on optimizing CXL's performance and security, providing attendees with valuable insights and practical solutions for advancing their CXL implementations. Heetashi Arora is a Lead Member of Consulting Staff for CXL VIP Development at Siemens, bringing over 11+ years of experience in the EDA industry. She has extensive expertise in CXL and PCIe generations, as well as background of simulation-to-emulation VIPs. Prior to her work in VIP development, Heetashi focused on emulation solutions and its performance aspects. She holds a Bachelor's degree in Electronics and Communication
Veera Venkata Sri Harsha Badam Senior Manager Samsung semiconductor India research	Samsung semiconductor India research	Senior Manager
Tuesday @ 09:45 AM: Vehicle to Everything This session delves into the transformative landscape of automotive technology, emphasizing the critical role of advanced memory solutions in supporting next-generation applications such as autonomous driving and robo-taxis. Presentations converge on the necessity for high endurance, nonvolatile memory systems capable of withstanding the rigorous demands of real-time data processing and storage in automotive environments. Key themes include the adaptation of NAND Flash-based storage for enhanced reliability and safety, the challenges of high write cycles on flash memory, and the strategic development of chipsets that meet the elevated computing and temperature requirements. Additionally, the efforts towards standardizing high-bandwidth memory across legacy systems reflect an industry-wide push for efficiency and longevity in automotive applications. These insights collectively underscore the need for innovative approaches by memory semiconductor companies to align with the evolving automotive ecosystem. The Presenter is currently Working as a Senior Manager in Samsung Semiconductor India Research (SSIR) under Flash memory domain. Current role involves product qualification of UFS devices across Mobile and Automotive applications and spans along with test development and spec validation. His Prior experience involves Firmware development in USB based Portable SSDs at Western Digital, along with 11 years of experience in developing Firmware for safety critical Aviation based cockpit Display applications and controllers in Honeywell Technology Solutions. One of the major achievements was Outstanding Engineer Award (2022), for introducing a new product line of touch screen controllers with display applications in cockpit by replacing legacy controllers. Have a master's in computer science engineering from VIT Vellore.
Andres Baez Software Engineer Solidigm	Solidigm	Software Engineer
Wednesday @ 08:30 AM: NVMe State of the Union, Configurable Device Security and Quality of Service (QoS) NVM Express® (NVMe®) technology has become the language of storage and is now synonymous with high-performance storage and with widespread adoption in client, cloud, enterprise and event AI applications. Although initially developed for direct-attached PCIe® SSDs, NVMe architecture is now widely used in both direct-attached and fabric-attached applications. This session will provide an overview of the NVMe standards roadmap and reviews the newest NVMe features like NVM Subsystem Migration, Quality of Service, Fabric Resiliency and more. We will also discuss how NVMe technology will continue to support Cloud and Enterprise Applications and emerging applications like AI. The session will also provide two deep dive presentations into new NVMe features Configurable Device Security and Quality of Service (QoS). The Configurable Device Security presentation will discuss how this new feature will add value to SKU reduction and secure specific NVM subsystem configurations for end customer engagements, and how OEMs and platform providers will be able to better manage inventories and prepare products for delivery in a more efficient way using this new NVMe capability. The QoS presentation will discuss how to implement QoS on an SSD and provide clarity on the standardized modes for QoS control, including key parameters and simplified control knobs. Through example use cases and scenarios, the presentation will explore reasonable settings for meeting customer requirements, as well as situations where "best effort" approaches may be necessary. Andres Baez is a Software Engineer at Solidigm with extensive experience as firmware engineer and software architect for SSD storage devices. Andres collaborates with customers to define new and innovative features and capabilities to enhance the NVMe standard. Andres has a B.S. in Computer Engineering and a MS in Computer Science from the University of Arkansas.
Karthik Balan Associate Director Samsung Electronics	Samsung Electronics	Associate Director
Thursday @ 12:10 PM: Simulation and Failure Analysis This session delves into innovative methodologies and technologies aimed at enhancing the reliability and performance of modern data storage and processing systems. A common theme across the presentations is the integration of advanced testing and validation frameworks, with a particular emphasis on machine learning and open-source tools, to optimize resource allocation and expedite issue detection. The utilization of real-time checkers and telemetry data for predictive maintenance exemplifies the proactive approach to system health management. Additionally, the session highlights the transformative potential of CXL (Compute Express Link) technologies, showcasing tools like OpenCXL that facilitate scalable, high-performance interconnects essential for handling demanding workloads. Siemens' CXL VIP framework further streamlines verification processes, reducing time and complexity by offering lightweight simulation environments. Collectively, these presentations underscore the importance of robust validation infrastructures and telemetry in achieving reliable, efficient, and cost-effective technology ecosystems. Karthik is a Associate Director at Samsung Electronics(SSIR), he has experience of 20 years in Embedded System Testing and last 12 years in Memory Solutions Tests for NVMe, SAS, CXL, etc. He is currently works on architecting the test coverage and test solutions for NVMe Enterprise SSDs. Driving towards shift-left approach and open source enablement for NVMe SSD qualifications
Stephen Bates Fellow, AI Storage Architecture and Software AMD	AMD	Fellow, AI Storage Architecture and Software
Wednesday @ 01:10 PM: Keynote 9: MaxLinear: “Accelerated” Software-Defined Storage Transforming Data Storage at Enterprise Data Centers The data storage market is experiencing enormous growth, driven largely by AI adoption. According to Fortune Business Insights, the global cloud storage market is projected to grow six folds from 100B$ to 600B$+ over next 5 years. This growth is creating significant challenges: • Rising power consumption even beyond current 2% of global energy consumption • Increasing storage costs as data volumes expand • Performance bottlenecks with traditional storage solutions • Security concerns with distributed data This keynote will address these challenges suggesting novel methods using combination of high-performance CPU Cores (performance per watt) and storage acceleration SoC (System-on-a-Chip) drastically reduce the power consumption over traditional methods. Several architectural trade-offs involving off-load, in-line and a hybrid method along with accelerated data services like deep compression for hot and cold data, encrypted data and providing quantum resilience with an achievable scale-out at 1Tb per second will be discussed. These methods can improve effective storage by factors up-to 1:20. Wednesday @ 03:15 PM: NVMe SSD Virtualization Ecosystem - A Panel This session delves into the pivotal advancements and collaborative efforts in the realm of SSD virtualization, with a particular focus on standardizing Live Migration in NVM Express® to enhance the efficiency of Virtual Machine migrations with direct-attached PCI Express® storage. Through a series of presentations and panels, experts explore the intricacies of NVMe® SSD Virtualization, discussing how hypervisors and Virtual Machine Managers can leverage open-ecosystem host software stacks to manage data and state migration. Key themes include the coordination required between hosts and devices, the challenges of tracking host memory modifications, and the strategic trade-offs in abstraction and complexity when implementing virtualization across different layers of the technology stack. Additionally, the session highlights the implications of these innovations for cloud service providers, underscoring the importance of flexibility and effective resource management in response to evolving virtualization demands. Stephen Bates is an AMD Fellow focusing on AI storage architectures and software in the AI Group. He is a renowned expert on topics like NVMe, RDMA, TCP/IP and NVM. He has worked on a range of complex storage and communication systems including NVMe controllers and PCIe switches. He enjoys working at the interface between hardware and software and is an active contributor to the Linux kernel and other open-source software projects. He has spent time as an academic as an Assistant Professor in Computer Engineering at The University of Alberta. He holds a PhD degree from The University of Edinburgh, Scotland and is a Senior Member of the IEEE.
Shimon Ben-David CTO WEKA	WEKA	CTO
Wednesday @ 09:45 AM: Data Center Consumer Panel: Storage Needs for the AI Era Artificial intelligence is changing the world of storage at the speed of light. With a growing focus on higher capacities, performance, QoS, form factors, and lower power, it can be challenging to translate those needs into specific use cases, system architectures, or even specific product selections. Join us for an enlightening panel discussion moderated by Jeremy Werner, SVP and GM of Micron's Core Data Center Business Unit. He will lead industry luminaries from various technology domains in exploring the future of storage in an AI-driven world. Come and learn from these technology leaders what it takes for your storage solutions to thrive in that world! Shimon Ben-David, WEKA's CTO, engages with customers and partners to gather feedback and insights for the Engineering and Product Management teams, leveraging his extensive enterprise IT experience from leadership roles at companies like Primary Data, XtremIO, IBM, and XIV Storage. He previously led customer success and sales engineering at WEKA and studied Computer Science and Philosophy.
Brian Berg President Berg Software Design	Berg Software Design	President
Tuesday @ 11:30 AM: FMS Lifetime Achievement Award The FMS Lifetime Achievement Award recognizes individuals who have shown outstanding leadership in promoting the development and use of memory, storage, and/or associated or related technologies, including one or more of the following: Founding a leading memory or storage company Driving the adoption of initiatives and/or standards in the memory and storage industries Bringing memory or storage to a new application, including supplanting older technologies Demonstrating exceptional leadership, including defining new architectures Wednesday @ 08:30 AM: Multi-Level Cells Part 1 This session brings together a diverse range of presentations that delve into the evolving landscape of SSD technology and storage solutions, driven by the surging demand for data capacity and efficiency. A common theme is the pursuit of enhanced storage solutions to meet the exponential growth in data and the increasing power efficiency requirements. The discussions highlight the potential of larger Indirection Units (IUs) and Large Block Sizes (LBS) in SSDs, enabling seamless adoption of high-capacity drives, and the strategic role of QLC technology as a middle tier between traditional HDDs and TLC SSDs. The session also addresses the challenges in optimizing technologies for petabyte-scale SSDs, such as overcoming NAND flash density limitations and DRAM bottlenecks through hardware-accelerated compression and CXL-enabled memory expansion. Moreover, the presentations explore the impact of AI on storage demands, emphasizing the need for cost-effective, high-performance solutions like QLC to support AI applications. Together, these insights provide a comprehensive view of the future of data storage, highlighting innovative strategies and technologies poised to transform storage capabilities by 2030. Wednesday @ 03:15 PM: Flash Architectures and Provisioning This session converges on the transformative potential of Flexible Data Placement (FDP) and Zoned Namespaces (ZNS) in enhancing data management, performance, and efficiency across diverse computational environments. The presentations collectively underscore FDP's ability to optimize data placement on SSDs, yielding notable reductions in write amplification and power consumption without necessitating software modifications. Real-world applications, such as CI/CD workflows and GPU checkpointing, illustrate FDP's capacity to streamline processes and mitigate bottlenecks, significantly enhancing performance and scalability. Meanwhile, the exploration of ZNS SSDs highlights architectural innovations required to handle unique constraints like append-only modes and zone management, while maximizing file system performance. Together, these insights reveal a cohesive narrative of data-centric strategies driving efficiency and innovation in storage technologies. Thursday @ 01:25 PM: Multi-Level Cells Part 2 This session cohesively explores the progressive advancements and applications of Quad Level Cell (QLC) NAND technology across various platforms and its implications for efficiency, reliability, and capacity. Presentations converge on the theme of optimizing QLC performance, addressing challenges such as reduced programming efficiency due to smaller cell sizes and thicker tunnel oxides, and proposing algorithms suited for Multi-Level Cell operations. The session also delves into the deployment of high-capacity QLC NVMe SSDs, with a focus on minimizing drive rebuild time and write amplification factor (WAF), ensuring endurance and reliability in mission-critical applications through robust data protection schemes. Furthermore, the adoption of QLC NAND in smartphones, particularly through Universal Flash Storage (UFS), is highlighted, emphasizing its potential to deliver higher capacity without performance trade-offs, thus meeting the expanding demands of advanced mobile applications. Collectively, these presentations underscore the transformative impact of QLC technology in enhancing storage solutions across diverse domains. Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley Section, Director and past Chair of the Consultants Network of Silicon Valley, Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for Outstanding Service to the Consulting and Electrical Engineering profession, and the 2012 Outstanding Leadership and Professional Service Award for Region 6.
Simone Bertolazzi Principal Analyst Yole Group	Yole Group	Principal Analyst
Tuesday @ 08:30 AM: Market Analyst Panel The fast-moving markets for memory and storage cause rapid changes in the business environments surrounding them, making it difficult for customers and consumers to see the “patterns in the data.” Industry analysts around the world are tracking these market dynamics – with data and reports that describe this era of rapid change. In this session, analysts from North America, Europe (EMEA) and Asia/Pacific will show the data and trends that are shaping the marketplace – affecting the pricing and availability for memory and storage products worldwide. As this session concludes, a brief question-and-answer (Q&A) session will follow this series of industry analyst presentations. Thursday @ 09:45 AM: HBM: DRAM's Bright Future This session delves into the rapidly evolving landscape of memory technologies in the context of AI and high-performance computing, highlighting the interplay between existing standards and emerging innovations. A common theme across presentations is the transformative role of High Bandwidth Memory (HBM) in fueling the AI boom, with both its robust growth and impact on the DRAM market thoroughly examined. Discussions underscore the significant influence of AI processor architectures on memory access, particularly in light of developments in quantization and sparsity. The session explores the promise of novel techniques such as in-memory and near-memory computing, alongside the critical importance of addressing sustainability and energy consumption. Key insights into market dynamics, including future forecasts and supply chain implications, offer a comprehensive view of how these memory technologies are set to redefine the industry. From 3D DRAM advancements to potential processing-in-memory innovations, this session provides a forward-looking perspective on how these technological inflections will shape the future of memory and processor interactions. Simone Bertolazzi, PhD, is a Principal Technology & Market analyst, Memory, at Yole Intelligence, part of Yole Group. As member of Yole’s memory team, he contributes on a day-to-day basis to the analysis of memory markets and technologies, their related materials, device architecture and fabrication processes. Simone obtained a PhD in physics in 2015 from École Polytechnique Fédérale de Lausanne (Switzerland) and a double M. A. Sc. degree from Polytechnique de Montréal (Canada) and Politecnico di Milano (Italy).
Kiran Bhat Product Manager Solidigm	Solidigm	Product Manager
Thursday @ 09:45 AM: AI Workloads and Data Placement Techniques This session delves into the evolving landscape of storage solutions tailored for AI workloads, focusing on optimizing data placement and enhancing performance both at the edge and in enterprise environments. A central theme is the critical role of understanding AI model IO characteristics and the deployment of storage technologies like Dataset Management Commands and Flexible Data Placement (FDP) to meet the demands of real-time AI applications. Presentations will explore the strengths and limitations of various technologies such as ZNS and FDP, with practical demonstrations of their implementation in PCIe 5.0 SSD controllers, showcasing improved performance and reduced write amplification factor (WAF). The session will also highlight industry alignment efforts, including SNIA's guidance on FDP configurations, aiming to standardize practices and reduce market variability. Additionally, strategies to ensure guaranteed performance in dynamic application environments, such as those involving mobile devices and drones, will be examined. Attendees will gain insights into selecting appropriate storage solutions and configuring them to optimize AI applications both at the network edge and in enterprise settings. Kiran is an experienced Product Manager. He has been in storage industry for the last 7 years. He started working on client SSDs and now works as a Data center SSD product manager on on the Data center. Kiran worked as Technical Maketing Engineer at Intel's PC client division for more than a decade before moving to storage. Kiran has a masters degree in Electrical Engineering.
Rory Bolt Senior Fellow KIOXIA America	KIOXIA America	Senior Fellow
Monday @ 01:00 PM: KIOXIA AiSAQ™ OSS: Scaling RAG Beyond DRAM Limits with SSD Open source software (OSS) project AiSAQ provides a new approach to scaling AI, especially for Retrieval-Augmented Generation (RAG). RAG can improve accuracy for AI models that use Approximate Nearest Neighbor Search (ANNS)) of vector databases. DiskANN was developed to store some elements of the vector database on SSDs, which enables a larger database. KIOXIA AiSAQ™ open-source technology allows all of the vector database elements to be stored in SSDs. This enables a number of capabilities, including a limitless vector database size, faster time-to-ready, and can connect to multiple AI host systems simultaneously. The end result is a better RAG implementation for the AI system utilizing KIOXIA AiSAQ technology. Learn about graph-based ANNS vs. cluster-based ANNS, how to deploy and utilize KIOXIA AiSAQ, the advantages for RAG/vector administrators and service providers, and an introduction to the SSD-based ANN algorithm. Wednesday @ 08:30 AM: SSD Technologies for AI and the Data Center This session delves into the transformative role of storage technologies in optimizing AI workloads across various platforms, from high-demand AI applications to mobile computing devices. The presentations collectively highlight the critical advancements in storage solutions designed to meet the unique demands of AI, including the development of extremely performant SSDs and innovative storage technologies that enhance user experience in AI-driven PCs. A common thread is the emphasis on bridging the performance gaps in storage efficiency and effectiveness, as demonstrated by the Transparent Host Memory Buffer (THMB) technology, which significantly elevates the performance of DRAMless SSDs to rival that of DRAM-based solutions. Attendees will explore how these cutting-edge storage innovations are reshaping the landscape of AI applications, offering enhanced performance, reduced latency, and cost-effective solutions that are essential for sustaining the rapid evolution of AI technologies. Wednesday @ 03:15 PM: Flash Architectures and Provisioning This session converges on the transformative potential of Flexible Data Placement (FDP) and Zoned Namespaces (ZNS) in enhancing data management, performance, and efficiency across diverse computational environments. The presentations collectively underscore FDP's ability to optimize data placement on SSDs, yielding notable reductions in write amplification and power consumption without necessitating software modifications. Real-world applications, such as CI/CD workflows and GPU checkpointing, illustrate FDP's capacity to streamline processes and mitigate bottlenecks, significantly enhancing performance and scalability. Meanwhile, the exploration of ZNS SSDs highlights architectural innovations required to handle unique constraints like append-only modes and zone management, while maximizing file system performance. Together, these insights reveal a cohesive narrative of data-centric strategies driving efficiency and innovation in storage technologies. Thursday @ 11:00 AM: Special Presentation: Executive AI Panel: Memory and Storage Scaling for AI Inferencing Raw bandwidth is important for AI training workloads, but AI inference needs that and more. It also needs distributed solutions with AI optimized low latency networking, and intelligent memory and storage for optimum performance. This panel explores how ultra-high performance AI optimized storage networking, and GPU enhanced AI storage solutions can dramatically accelerate data transfers between memory and local and remote storage tiers. This enables dynamic resource allocation, significantly boosting AI inferencing request throughput. We will explore how this combination addresses the challenges of scaling inference workloads across large GPU fleets moving beyond traditional bottlenecks. We have assembled a panel of experts from inside NVIDIA and across the storage and memory industry to provide insight on how to maximize the number of AI requests served, while maintaining low latency and high accuracy. Rory Bolt is a senior fellow at KIOXIA America and leads the forward-looking technology and storage pathfinding group for SSDs. He has more than twenty-five years of experience in data storage systems, data protection systems, and high-performance computing with a pedigree from marquee storage companies. Rory has been granted over 12 storage related patents and has several pending. Rory has a BS in Computer Engineering from UCSD.
Paul Borrill Founder and CEO DAEDAELUS	DAEDAELUS	Founder and CEO
Wednesday @ 08:30 AM: CTO Panel AI workloads are growing exponentially, and energy consumption has become the defining challenge in data center operations. According to the International Energy Agency (IEA), electricity demand from data centers worldwide is expected to more than double by 2030, surpassing the total electricity consumption of Japan today. As NVIDIA Chief Scientist Bill Dally notes, it now costs over 1,000× more energy to move a byte of data than to compute on it. This simple reality is forcing a fundamental rethinking of architectures across compute, memory, storage, and networking. In modern AI clusters, as much as 80% of the power budget is consumed by data movement and communication—rather than computation itself. This CTO-Vision Panel brings together some of the industry’s most influential technology leaders to explore the existential question facing hyperscalers and enterprises alike: How can we break the energy ceiling? The stakes are high. Without a fundamental redesign in how we move and process data, AI infrastructure and cloud-scale architectures will hit energy ceilings long before their full potential is realized. Thursday @ 08:30 AM: Networks and Links 1: Foundations In the rapidly evolving landscape of computer architecture, this session delves into the transformative potential of emerging technologies such as Data Processing Units (DPUs), PCIe advancements, Unified Addressing Layer (UAL), and Atomic Ethernet. Presentations will explore the integration of DPUs in storage systems, highlighting their role in optimizing data management and enhancing scalability. This is complemented by discussions on PCIe 6 and 7 technologies, which are paving the way for more flexible and accelerated infrastructures, ultimately supporting diverse application needs. The session will also showcase UAL as an open standard for AI/ML and HPC workloads, emphasizing its role in fostering an open ecosystem through transparent and interoperable networking solutions. Lastly, the dialogue on Atomic Ethernet will underscore the shift towards viewing networking as a core component of system design, advocating for open specifications to support the next generation of computing. Together, these presentations offer a comprehensive view of the innovations driving the future of high-performance computing and networking. Thursday @ 01:25 PM: Networks and Links: Advanced Topics The Link Wars Debate: Proprietary, Open and Atomic Fabrics in AI Networking}. AI-scale infrastructure is moving past traditional switches and routers. The future lies in high-speed links: NVLink, UALink, AELink, PCIe/CXL and Ultra-Ethernet -- delivering memory semantics, programmability, and deterministic messaging. Join this high-energy debate as experts square off on proprietary vs open vs atomic link fabrics, debating which model should power next-generation AI systems--and why it matters for scalability, correctness, and vendor choice. Paul Borrill is founder and CEO of DÆDÆLUS and is a leading industry expert on the foundations of resilient network and storage infrastructures
Jean Bozman President Cloud Architects Advisors	Cloud Architects Advisors	President
Tuesday @ 08:30 AM: Market Analyst Panel The fast-moving markets for memory and storage cause rapid changes in the business environments surrounding them, making it difficult for customers and consumers to see the “patterns in the data.” Industry analysts around the world are tracking these market dynamics – with data and reports that describe this era of rapid change. In this session, analysts from North America, Europe (EMEA) and Asia/Pacific will show the data and trends that are shaping the marketplace – affecting the pricing and availability for memory and storage products worldwide. As this session concludes, a brief question-and-answer (Q&A) session will follow this series of industry analyst presentations. Tuesday @ 09:45 AM: AI + Storage: AI and the Enterprise Business In this session, we delve into the transformative impact of AI on data infrastructure and memory storage, as enterprises increasingly harness advancements in generative AI and large language models. Central to these discussions are the architectures necessary for managing and processing vast quantities of both structured and unstructured data, with a focus on the implementation of high-performance data lakes and lakehouses utilizing both high-capacity disk-based and All-Flash storage solutions. The session further explores the burgeoning demand in the memory and storage sectors catalyzed by AI-driven NeoCloud data centers. Through expert panel insights, we will examine the evolution of AI model requirements, including foundational models and memory-bound inference, and their implications for infrastructure investments and economic strategies. Additionally, the growing demand for High Bandwidth Memory (HBM) will be analyzed, highlighting innovations in memory stacking and bandwidth efficiency amidst potential risks like oversupply and economic fluctuations. Attendees will gain a comprehensive understanding of the strategic considerations necessary for leveraging AI advancements while maintaining robust and scalable data infrastructures. Wednesday @ 09:45 AM: Data Intensive Customer Solutions: Customer Experience This session with presentations followed by a panel discussion, delves into the transformative impact of innovative storage solutions on both financial and technical dimensions within enterprise environments. Across the presentations, a common thread emerges: the imperative of optimizing storage to meet the escalating demands of modern data-intensive applications, such as AI and large-scale databases. Highlighting the ability to dramatically enhance storage efficiency, reduce CAPEX and OPEX, and deliver rapid ROI, the session underscores the importance of selecting vendors that align with organizational needs for value, performance, and certainty. Complementing this, we discuss how AI-powered predictive memory technology is showcased as a breakthrough in achieving DRAM-class performance using Flash storage, offering significant cost-efficiency and scalability. Additionally, the session addresses the architecture of AI NeoClouds, emphasizing the necessity for a multi-tiered storage approach that balances bandwidth, endurance, and total cost of ownership (TCO) to future-proof AI applications. Collectively, these insights provide a comprehensive framework for architects and executives alike to enhance storage strategies, ensuring their infrastructure is both economically viable and technically robust. Thursday @ 08:30 AM: Memory Markets In this session, we delve into the evolving landscape of data storage and memory technologies, exploring their critical roles in meeting the burgeoning demands driven by generative AI and data center growth. Across the presentations, a recurring theme is the balance of performance and total cost of ownership (TCO) among storage solutions such as HDD, SSD, and emerging semiconductor technologies. While HDDs currently dominate due to their cost advantage, the rise of enterprise-grade SSDs is highlighted as a key factor in addressing the need for faster and higher-capacity storage. The discussion extends to the memory market, focusing on DRAM and NAND dynamics influenced by global economic and strategic factors, including China's growing influence. Furthermore, the potential for adopting a foundry model in the memory sector, akin to the success seen in CMOS logic, is explored, emphasizing the opportunities and challenges posed by trends like processing in memory (PiM). This session offers a comprehensive overview of how technological advancements and market forces are shaping the future of data storage and memory, providing strategic insights into navigating these complex environments. Thursday @ 02:30 PM: "Ask Anything" Closing Session FMS: the Future of Memory and Storage, will wrap up with a dynamic and engaging Closing Session on Thursday, August 7 at 2:30 PM, offering attendees an exciting interactive opportunity to exchange ideas with leading experts who spoke at FMS and reflect on the key themes and insights from this year's record-breaking event. Held in Ballroom E of the Santa Clara Convention Center, the 90-minute "Ask Anything" style session will feature thought leaders from across the memory and storage ecosystem. Attendees can expect to hear candid reflections, an interactive exchange of ideas, and valuable takeaways that tie together the week's technical sessions, panels, and keynotes, including Tom Coughlin, who will reflect on his worldwide travels as presented in keynote session #12: "Where in the World is Tom Coughlin." Jean S. Bozman is President of Cloud Architects Advisors, a market research and consulting firm focused on hardware and software for enterprise and hybrid multi-cloud computing. She analyzes the markets for servers, storage, and software related to datacenters and cloud infrastructure. A highly-respected IT professional, she has spent many years covering the worldwide markets for operating environments, servers, and server workloads. She was a Research VP at IDC, where she focused on the worldwide markets for servers and server operating systems. She is a frequent conference participant as a speaker, chairperson, and organizer at such events as Flash Memory Summit, OpenStack, and Container World. She is often quoted in a variety of publications including BusinessWeek, Investor’s Business Daily, the Los Angeles Times, CNET, Bloomberg, and Reuters. Ms. Bozman has also been VP/Principal Analyst at Hurwitz and Associates and Sr Product Marketing Manager at Sandisk. She earned a master’s degree from Stanford.
Cameron Brett Director KIOXIA America, Inc	KIOXIA America, Inc	Director
Wednesday @ 08:30 AM: NVMe State of the Union, Configurable Device Security and Quality of Service (QoS) NVM Express® (NVMe®) technology has become the language of storage and is now synonymous with high-performance storage and with widespread adoption in client, cloud, enterprise and event AI applications. Although initially developed for direct-attached PCIe® SSDs, NVMe architecture is now widely used in both direct-attached and fabric-attached applications. This session will provide an overview of the NVMe standards roadmap and reviews the newest NVMe features like NVM Subsystem Migration, Quality of Service, Fabric Resiliency and more. We will also discuss how NVMe technology will continue to support Cloud and Enterprise Applications and emerging applications like AI. The session will also provide two deep dive presentations into new NVMe features Configurable Device Security and Quality of Service (QoS). The Configurable Device Security presentation will discuss how this new feature will add value to SKU reduction and secure specific NVM subsystem configurations for end customer engagements, and how OEMs and platform providers will be able to better manage inventories and prepare products for delivery in a more efficient way using this new NVMe capability. The QoS presentation will discuss how to implement QoS on an SSD and provide clarity on the standardized modes for QoS control, including key parameters and simplified control knobs. Through example use cases and scenarios, the presentation will explore reasonable settings for meeting customer requirements, as well as situations where "best effort" approaches may be necessary. Thursday @ 09:45 AM: NVMe New Features The pervasive era of Artificial Intelligence and Machine Learning, demands high performance secured storage mechanisms. NVM Express® (NVMe®) technology has become the storage backbone for AI, ML and beyond and this session will feature multiple presentations from industry experts discussing important technology updates and use cases. In the first presentation, attendees will receive an overview of the latest and upcoming drivers updates for Windows. The next presentation will discuss the Live Migration feature. The host-managed live migration allows maintenance without interrupting a workload, rebooting an instance, or modifying any instance's properties like IP addresses, metadata or network settings. To ensure thorough verification and overcoming the challenges, the solution must be agile to validate track and migration commands, suspend and resume, data transfers to and from different regions, controller data queues management and memory scoreboarding across power cycles. We will discuss the important characteristics of the solution from planning to closure. We will explore how using common APIs, data structures, migration with existing/updating queues and data structures, utilizing UVM features like callbacks and analysis components will make the solution highly adaptable by keeping the high-level stimulus same. We will also delve into strategies for making the solution reusable for new features like NVM Subsystem Migration. We will see a case study on how these techniques, along with an exhaustive compliance test suite and efficient debug mechanism, helped our NVMe customers thoroughly verify the intricacies of live migration-enabled SSD designs and achieve a shorter time to market. Cameron Brett is the Director of Enterprise SSD Marketing at Kioxia, where he manages a team of product line managers to drive product strategy and revenue growth. Cameron has over 18 years of product marketing and management experience in storage technology and has previously held managerial positions at QLogic, PMC-Sierra, Broadcom and Adaptec. Throughout his career in high-tech product marketing, he has focused on storage for enterprise and small/medium business servers and worked to bring new generations of storage technology to market. His area of expertise includes Flash/SSD storage, virtualization, convergence and cloud technologies
Randy Brown Senior Principal Engineer Marvell	Marvell	Senior Principal Engineer
Wednesday @ 03:15 PM: High Capacity SSDs and Optimizations for QLC Flash Storage This session will delve into the transformative advancements in Solid State Drives (SSDs) as they cater to the evolving demands of modern applications and hyperscale environments. A recurring theme is the balance between performance, endurance, and power efficiency, particularly as SSDs increase in capacity. Presentations will explore innovative techniques such as utilizing pseudo SLC (pSLC) namespaces to enhance high-frequency metadata access while maintaining system resilience and flexibility. As SSDs scale, optimizing write amplification and managing power consumption become critical, offering opportunities for both hardware and software enhancements. The integration of larger Indirection Units (IUs) demands a reassessment of host software to ensure seamless adoption and optimal performance of high-capacity SSDs. Additionally, the session highlights the collaboration with hyperscalers to develop QLC storage solutions that combine hardware innovations and intelligent software management, delivering high throughput, scalability, and cost benefits crucial for AI/ML workloads and beyond. Through these discussions, attendees will gain insights into the strategies for optimizing SSD deployment in a rapidly changing technological landscape. Thursday @ 12:10 PM: New Form Factors and Interfaces for SSDs This session will delve into the dynamic evolution of SSD technologies, focusing on power efficiency, compliance, and form factor advancements essential for modern storage solutions. Central to the discussions is the challenge of balancing increased PCIe link speeds, as seen in Gen5 and forthcoming Gen6 SSDs, with power efficiency, highlighting innovative adaptive link speed management strategies that align with real-time workload demands and host power policies. Complementing this is an exploration of rigorous testing frameworks led by the University of New Hampshire InterOperability Laboratory, which ensure NVMe SSDs meet the highest standards of interoperability and reliability. As the industry shifts from traditional U.2 to EDSFF form factors, the session will also address the mechanical and power considerations pivotal for future system designs. Finally, a comprehensive overview of advanced power optimization techniques—from design to retirement phases—underscores the critical role of efficient SSD controller architectures and component scaling in reducing total cost of ownership and environmental impact, ultimately driving the next wave of sustainable storage innovation. Randy Brown, a graduate of Carnegie Mellon University with a degree in Computer Science, is currently a Senior Principal Engineer in the Architecture team of Marvell’s Custom, Compute and Storage Group. Randy has over 30 years of experience in the storage industry. His experience spans filesystems, advanced storage stacks including snapshot and replication, RAID, and iSCSI. He has also managed and contributed to firmware teams that have shipped multiple SATA and NVMe based SSDs.
Suresh Bysani Venkata Naga Director of Engineering Eightfold.ai	Eightfold.ai	Director of Engineering
Thursday @ 08:30 AM: Data Analytics This session explores the innovative intersections of AI, data management, and technology scalability, highlighting the transformative impact of strategic resource optimization across industries. A recurring theme is the disentanglement of traditional system architectures, as seen in the separation of compute and storage to enhance query performance in AI analytics, and the development of a Data Eco-System at SK hynix for superior SSD quality management. These strategies underscore the importance of modular, scalable systems capable of addressing the growing demands of modern data centers and AI applications. Additionally, the session delves into the role of AI in centralizing and optimizing talent data management, as exemplified by One Resume's integrated system that harmonizes professional profiles for improved connectivity. Further expanding on the theme of efficiency and scalability, the semiconductor industry's shift towards three-dimensional logic illustrates the necessity of human-machine collaboration to navigate increased process complexity and drive rapid innovation. Together, these presentations offer a comprehensive view of how decoupled architectures and AI-driven solutions are reshaping the landscape of data storage, talent management, and technological advancement. Suresh Bysani, an IEEE Senior Member, CNSV member, and FMS CAB member, leads the core SaaS and AI infrastructure at Eightfold.ai, managing the platform for a B2B2C product with 100 million active users. He oversees search, data, OLAP, serving stack, and AI infrastructure, bringing over a decade of experience in scaling systems. Before joining Eightfold, he was an early engineer at Cohesity, a distributed data platform. Throughout his career at both Cohesity and Eightfold, Suresh has collaborated with Fortune 100 and 500 companies to address complex infrastructure challenges at scale.
Greg Campbell Chief Technology Officer VergeIO	VergeIO	Chief Technology Officer
Wednesday @ 01:40 PM: Keynote 10: VergeIO: AI Infrastructure for Everyone: Flattening the Pipeline, Simplifying Deployment Today, the complexity of artificial intelligence demands specialized skills, sophisticated tools, and robust infrastructure, rendering it both inaccessible and costly for many organizations. IT teams encounter significant learning curves and operational challenges when developing AI solutions on fragmented infrastructures. Current solutions fail to address the core issue: the ecosystem’s overwhelming complexity. Innovations in AI infrastructure must flatten the AI pipeline and reduce integration burdens. This talk will examine how streamlining the AI ecosystem facilitates the privatization of AI for organizations and sovereign entities, enabling the creation of secure, self-managed AI environments. These advancements will promote broader AI adoption, leading to faster returns on GPU investments and justifying the use of high-capacity SSD technology within AI processes. During the keynote, VergeIO will showcase a live demonstration of VergeIQ, and provide a peek at what integrated, sovereign AI looks like in practice. Greg Campbell is the architect behind VergeOS and a veteran in scalable system design. With a background in distributed computing and a passion for eliminating infrastructure bottlenecks, he leads VergeIO’s engineering efforts to integrate advanced capabilities like AI into the core of the operating system. Greg earned a degree from University of Michigan - Dearborn.

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