Program at a Glance
07:30 AM to 07:30 PM
Open
REG:
Registration
Main Lobby (Santa Clara Convention Center, First Floor)
Track:
General Events
General Event Description:
Registration for August 5-7, 2025 FMS Conference.
08:00 AM to 08:30 AM
Open
BRK:
Wednesday Continental Breakfast
Foyer - Main Lobby (Santa Clara Convention Center, First Floor)
Track:
General Events
General Event Description:
Description Not Available
08:30 AM to 09:35 AM
PRO
AIML-201-1:
Generative AI Part 1
Ballroom A (Santa Clara Convention Center, First Floor)
Track:
AI and ML Applications
Chairperson:
Kapil Sethi, Director, New Business Planning , Samsung Semiconductor
Kapil is currently Director in the DRAM New Business Planning team at Samsung Semiconductor where he leads product planning, customer enablement and business development for Samsung’s CXL® technology based products. He has been at Samsung Semiconductor for more than 4 years. Previously, Kapil has worked as Technical Product Manager leading multi-million dollar product lines.
Organizer:
David McIntyre, Director Product Planning, Samsung Electronics
David McIntyre focuses on computational storage acceleration solutions development and strategic business enablement for cloud to edge applications including AI inference/video analytics, database processing and blockchain networks. He has held senior management positions with IBM, Samsung, Xilinx, Intel (formerly Altera) and at Silicon Valley startups. He has consulted for institutional investors including Fidelity, Goldman Sachs and UBS. David is a frequent presenter and chairperson at the Flash Memory Summit and other technical conferences including SNIA.
Presenters:
Presentation Session Description:
Deepankar Kansal, Senior Engineer, Sandisk
Presentation Title:
Flash-powered Mixture of Language Models Inference on Edge Devices
Presentation Abstract:
Generative AI models are rapidly getting deployed on client or edge devices. They aid in diverse applications like virtual assistance, content creation, and data analysis. However, their substantial computational and memory demands pose significant challenges, particularly for edge devices with limited GPU VRAM. During token generation, vector data navigates various LLM blocks which need not reside concurrently in VRAM.
We introduce SHARAG (Storage Hardware Accelerated Retrieval Augmented Generation), a software stack extending SSD capabilities, enabling inference from mixture of language models, thereby mitigating VRAM constraints. Our method dynamically loads transformer-based models from SSD to GPU VRAM, reducing memory requirements associated with model size. This facilitates local execution of LLMs exceeding available GPU VRAM and the simultaneous operation of multiple models enhancing, inference outcomes. Learn our novel inference techniques – interleaving models and leveraging reasoning tokens improve response quality. Quantitative analysis on the MMLU dataset demonstrates this enhancement compared to traditional methods under identical VRAM constraints.
Author Bio:
Deepankar Kansal is a Senior Engineer at SanDisk, where he brings hands-on expertise in machine learning, blockchain, and firmware technologies for storage devices. He holds a Master's degree in Artificial Intelligence and Machine Learning from IIIT Delhi (2022),India and a Bachelor's degree in Computer Science and Engineering from Guru Nanak Dev University, Amritsar (2020),India. Deepankar is currently exploring the intersection of AI/ML and storage technologies, with a focus on leveraging storage devices in the AI inference space to improve performance and efficiency in next-generation systems.
Moshe Twitto, CTO and Founder, Pliops.com
Presentation Title:
LLM KV Cache Offloading
Presentation Abstract:
Large language models are extremely powerful, but their scale comes with significant computational and memory challenges. One critical component in this puzzle is the KV cache. As these models grow larger, managing the KV cache effectively has become a key factor for improving performance and reducing costs.
Author Bio:
Moshe is an expert in advanced data management and coding algorithms. Prior to co-founding Pliops, Moshe served as CTO of Samsung’s SSD Controller Development Center in Israel, holds MSEE, BSEE degrees from Technion University, Summa Cum Laude and served in the Unit 8200 Intelligence Division of the Israel Defense Corps.
Pliops Team Member
Aryeh Mergi
FOUNDER
Co-founder of three successful startups, M-Systems, XtremIO and ActivePath and an active Chairman at Pliops. Received FMS2018 Lifetime
Pratik Mishra, Senior Staff Researcher, AMD
Presentation Title:
Flexible, Efficient, Resilient Training on AMD GPUs with DeepSpeed UCP.
Presentation Abstract:
Existing GenAI distributed training systems struggle to reconfigure parallelism during training across GPUs, slowing down progress during hardware failures or GPU re-allocation. This is due to tight coupling between distributed checkpoints and specific model parallelism and hardware configurations, preventing training jobs from efficiently adapting to resource elasticity.
We present Universal Checkpointing (UCP), a novel checkpointing system that enables flexible and efficient GenAI training with reconfigurable parallelism. Enabling reconfigurable parallelism across GPUs, poses non-trivial challenges to storage and memory performance, which requires careful hardware and software architecture considerations. Through under-the-hood analysis, we adapt UCP for optimal performance between large-scale AMD GPU clusters and high-performance remote storage systems. Through our optimizations, UCP enables reconfiguration for broad set of popular parallelism strategies and varying GenAI models, while incurring minimal reconfiguration costs, enhancing flexibility and resilience. Our evaluations show high checkpointing efficiency on AMD GPUs.
Joint ppt: Minjia Zhang (UIUC) & Pratik Mishra (AMD).
Author Bio:
Dr. Pratik Mishra is a Sr. Staff Researcher at AMD, responsible towards path-finding efforts for incubating full-stack deployable AI Infrastructure@scale. Primarily focusing on the intersection of dense GPU AI servers and distributed storage. Dr. Mishra serves as primary voting representative at Ultra-Ethernet Consortium (UEC) - Storage Workgroup . Prior to joining AMD, Pratik was at Samsung Semiconductors, San Jose, CA, where he was responsible for R&D efforts for adapting emerging high-performance "intelligent" NVMe storage device architectures in cloud/data-centric environments. Dr. Mishra holds a PhD in Computer Engineering with the primary focus on reducing the redundancies of the software storage IO stack of Hadoop deployments and developing near-data computation capabilities. Dr. Mishra has several core publications and patents in the filed of storage and memory sub-systems, and constantly servers as Char, Editorial Board and Program Member for highly distinguished conferences and journals. Interests: GPUs, DPUs, OS, file-systems (local and distributed), object-storage, DB, AI Training, etc.
Vishwas Saxena, Senior Technologist, Firmware Engineering, Sandisk
Presentation Title:
Flash-powered Mixture of Language Models Inference on Edge Devices
Presentation Abstract:
Generative AI models are rapidly getting deployed on client or edge devices. They aid in diverse applications like virtual assistance, content creation, and data analysis. However, their substantial computational and memory demands pose significant challenges, particularly for edge devices with limited GPU VRAM. During token generation, vector data navigates various LLM blocks which need not reside concurrently in VRAM.
We introduce SHARAG (Storage Hardware Accelerated Retrieval Augmented Generation), a software stack extending SSD capabilities, enabling inference from mixture of language models, thereby mitigating VRAM constraints. Our method dynamically loads transformer-based models from SSD to GPU VRAM, reducing memory requirements associated with model size. This facilitates local execution of LLMs exceeding available GPU VRAM and the simultaneous operation of multiple models enhancing, inference outcomes. Learn our novel inference techniques – interleaving models and leveraging reasoning tokens improve response quality. Quantitative analysis on the MMLU dataset demonstrates this enhancement compared to traditional methods under identical VRAM constraints.
Author Bio:
Vishwas is Senior Technologist in Firmware Engineering at Sandisk/Western Digital, Vishwas has spearheaded innovative products across Machine Learning, Security, Blockchain, Networking, and Wireless technologies. His key contributions include WD Crypto HW Wallet, Encrypted Content Search, Wireless Storage Drives, Edge Analytics-based Video Surveillance Systems, and Semantic Image Retrieval. With over 24 years of industry experience, he holds 30+ Patents and Trade Secrets along with 12 publications. Vishwas earned his Master’s in Machine Learning & AI from Liverpool John Moores University (2021) and a bachelor’s in computer engineering from Netaji Subhas Institute of Technology (2000)
This session delves into the critical challenges and innovative solutions associated with the deployment and efficient operation of large-scale generative AI models. A common theme across the presentations is the significant computational and memory challenges faced by these models, particularly as they scale. Effective management of key components such as the KV cache and the development of advanced systems like Universal Checkpointing (UCP) are emphasized as pivotal in optimizing performance and reducing costs. UCP, in particular, addresses the limitations of existing GenAI distributed training systems by allowing reconfigurable parallelism across GPUs, thus improving flexibility and resilience in the face of hardware constraints. Meanwhile, the SHARAG approach highlights strategies for deploying generative AI on edge devices, tackling memory limitations by dynamically managing model storage between SSDs and GPU VRAM. Together, these presentations underscore the importance of innovative architectural and software solutions to enhance the efficiency and adaptability of large language models in diverse, resource-constrained environments.
PRO
ASIA-201-1:
Asia Memory and Storage Markets
Ballroom B (Santa Clara Convention Center, First Floor)
Track:
Asia Memory and Storage Markets
Organizer:
Janet Liu Erickson, Project Manager, SAGE Micro
Janet Liu Erickson is Project Manager at SAGE Micro.
Chairperson:
Chris Tsu, Co-Founder/President, Sage Micro
Chris Tsu has over 30 years of engineering and management experience in mass storage, video processing, networking and telecommunications. He spent more than 10 years with Quantum and IBM as hard drive servo and DSP engineer/manager. and as major designer for multimedia and Fiber optical communication ASIC with Oak, Divio and Sytera, founded of Baleen System in 2002, as an industrial pioneer in NAND Flash and SSD ASIC, Chris has more than 20 patents Chris holds an MS in Electrical Engineering from San Jose State University. He also holds another MS degree from Stanford University where he worked toward Ph.D degree in Automatic Control and Machine Intelligence.
Presenters:
Presentation Session Description:
Peter Cheng, Senior Project Manager, Silicon Motion
Presentation Title:
Driving Edge AI Innovation with PCIe SSDs
Presentation Abstract:
We are the global leader in supplying NAND flash controllers for solid state storage devices and the merchant leader in supplying SSD controllers. We have the broadest portfolio of controller technologies and our controllers are widely used in embedded storage products such as SSDs and eMMC+UFS devices, which are found in smartphones, PCs and commercial and industrial applications. We have shipped over six billion NAND controllers in the last ten years, more than any other company in the world. We also supply customized high-performance hyperscale data center and industrial SSD solutions. Our customers include most of the NAND flash vendors, storage device module makers and leading OEMs.
Author Bio:
Peter Cheng has over 12 years of experience in the SSD industry, as well as almost 10 years in product marketing. He has collaborated with many NAND manufacturers around the world and participated in numerous projects. Currently, he focuses on the technical marketing of new Gen4/Gen5 SSD controllers and is dedicated to providing technologically advanced solutions.
Nilesh Shah, VP Business Development, ZeroPoint Technologies
Presentation Title:
Sovereign Computing: Reshaping the Global Memory and Storage Ecosystem
Presentation Abstract:
The rise of sovereign computing, driven by Asian governments mandating local data centers and chip manufacturing, is radically transforming the memory and storage industry. This shift extends to designing and manufacturing silicon chips and memory fabs locally, with examples like SK Hynix in Korea and new fabs in India. These changes are reshaping supply chain dynamics and investment landscapes, fueled by government subsidies and strategic access to resources. The influx of venture capital, especially from Asian family offices and U.S. funds, highlights a significant shift in investor profiles and strategies. This panel discussion will feature VCs in deep tech, memory suppliers, accelerator manufacturers, and datacenter operators, offering insights into how sovereign computing is influencing global technology and market dynamics, discussing strategic responses for navigating this evolving landscape.
Author Bio:
Nilesh Shah is VP Business Development, ZeroPoint Technologies. Additionally. He participates and contributes regularly at standards bodies like SNIA, OCP, JEDEC, RISC-V, CXL Consortium. He is regularly invited to speak at conferences, and has led multiple panels and is featured in Analyst/ Press interviews, focused on AI and memory technologies. Previously, Nilesh led Strategic Planning at Intel Corporation's Non Volatile Memory Solutions Group, where he was responsible for the product planning and launch of the Data Center SSD products and Pathfinding innovations. Nilesh advises GPU and memory Chiplet startups.
Pankaj Goel, Associate Director, Siemens EDA
Presentation Title:
Revolutionizing Memory for AI/ML’s Future: MRDIMM
Presentation Abstract:
As AI/ML applications continue to evolve, the demand for higher computational power and memory bandwidth is growing exponentially. To address these challenges, the industry is developing innovative solutions, with Multiplexed Rank DIMM (MRDIMM) emerging as a key breakthrough. MRDIMM offers superior bandwidth, reduced latency, higher capacity, and improved energy efficiency while ensuring stability and reliability. These advancements make MRDIMM a crucial enabler for the seamless execution of complex AI algorithms and efficient large-scale data management. This presentation will explore how MRDIMM addresses AI memory bottlenecks and why it is poised to shape the future of AI-driven computing.
Author Bio:
I am an Associate Director at SIEMENS EDA, responsible for managing the Memory and Network VIP portfolio. With 19 years of industry experience in VIP development, worked on a wide range of VIPs, including AMBA, PCIe, Memory, Flash, Ethernet, and more.
Dingsen Shi, Technical Director, Initio Corporation
Presentation Title:
ZKPU - Make ZK ASIC Decentralized, Scalable and Open Source
Presentation Abstract:
Zero-Knowledge Proofs (ZKPs) are becoming a foundational technology for scalable and privacy-preserving blockchain systems, especially through applications like zkRollups. In particular, ZK is emerging as a key pillar of Ethereum’s scaling roadmap, which dominates the stablecoin ecosystem and facilitates a large share of on-chain financial activity. However, the computational intensity of proof generation continues to limit real-world deployment. We present ZKPU, a hardware-software co-designed ZK accelerator that combines native NVMe integration—ensuring seamless compatibility across existing server and edge infrastructure—with a modular RISC-V System-on-Chip (SoC) architecture that opens the path to eliminating host–device communication bottlenecks. ZKPU is designed to flexibly support a wide range of ZK workloads; in this work, we demonstrate its capabilities by implementing and optimizing multi-scalar multiplication (MSM), a core bottleneck in many zk-SNARK systems. We also highlight how the integration of on-chip flash storage can further enhance ZK performance by enabling persistent, low-latency access to large proving data structures.
Author Bio:
Dingsen Shi is the Technical Director at Initio Corp., where he leads the ZKP-NVMe project—an initiative focused on accelerating zero-knowledge proof (ZKP) generation through computational storage. He architects hardware-software co-design solutions that integrate cryptographic accelerators directly into NVMe-based storage devices, bridging the gap between secure computation and scalable infrastructure. Dingsen holds a Master’s degree in Computer Science from the University of Illinois Urbana-Champaign and is currently pursuing a Ph.D. in Computer Science at the University of North Texas. His research interests lie at the intersection of AI infrastructure, trusted computing, and data-centric system design.
In an era marked by the rapid evolution of computing technologies, this session delves into transformative trends reshaping the landscape of AI, storage, and blockchain systems. We explore the pivotal role of advanced storage solutions like PCIe Gen5 SSDs and Multiplexed Rank DIMM (MRDIMM) in addressing the burgeoning demands of edge AI and large-scale AI/ML applications, offering unprecedented speed, density, and energy efficiency. Simultaneously, the rise of sovereign computing, propelled by local data center mandates and chip manufacturing initiatives in Asia, is altering supply chain dynamics and investment strategies, with far-reaching implications for the global tech industry. Moreover, Zero-Knowledge Proofs (ZKPs) are emerging as a cornerstone for scalable blockchain solutions, with innovations such as the ZKPU accelerator enhancing performance and privacy in blockchain applications. These presentations collectively underscore the significance of integrating cutting-edge hardware and strategic policy shifts to navigate and capitalize on the opportunities within this rapidly transforming digital landscape.
Open
BMKT-201-1:
CTO Panel
GAMR-1 & 2 (Great America Meeting Rooms, SCCC 2nd Floor)
Track:
Business Strategies & Memory Markets
Organizer:
Jay Kramer, Founder, Network Storage Advisors
Jay Kramer, founder at Network Storage Advisors, is a dynamic results-oriented strategic marketing leader and creator of world-class marketing teams with a proven track record of building company brand and demand generation initiatives that accelerate sales.
He has over 25 years of repeated marketing success with industry leading Fortune 500 companies (Unisys, Seagate) as well as early and late stage emerging companies. His industry knowledge spans cloud, virtualization, software defined storage (SDS), hyper convergence, data protection, SAN, NAS, and object storage solutions plus network storage technologies including Fibre Channel, iSCSI, VTL, dedup, backup, and replication.
He has served as board member to technology industry associations and event development/professional conference companies.
Chairperson:
Paul Borrill, Founder and CEO, DAEDAELUS
Paul Borrill is founder and CEO of DÆDÆLUS and is a leading industry expert on the foundations of resilient network and storage infrastructures
Panel Members:
Panel Session Description:
Alex Veprinsky, Chief Technologist, HPE
Alex Veprinsky is the Chief Architect for HPE Storage, responsible
for end-to-end architecture and design across the business unit’s
product portfolio. He joined HPE’s 3PAR division in 2016 as a Distinguished
Technologist, following a role as Distinguished Engineer
at Dell/EMC, where he helped develop and architect major storage
platforms. Earlier in his career, Alex worked at Comverse Technology
on enterprise telecom services. A prolific inventor, he holds numerous
patents in storage and computer science, and is deeply engaged
in mentoring technical teams and driving foundational research. Alex
holds a BSc in Electrical Engineering from Technion — Israel Institute
Sven Oehme, CTO, DDN
Sven began his career at IBM in 1993, and has worked in multiple
disciplines over the last 30 years. From Linux Virtualization, and
Storage Virtualization to Filesystems, Sven led the team driving most
of the performance improvements on Spectrum Scale (GPFS) over the
last 10 years. As part of the core architecture team, Sven was responsible
for metadata, streaming IO and specific analytics optimizations.
Sven joined DDN in 2018 as Chief Research Officer driving innovation
across DDN’s existing and future product portfolio.
Hannah Earley, CTO, Vaire
Dr. Hannah Earley is the Chief Technical Officer and Co-Founder of
Vaire Computing, a startup pioneering near-zero-energy, reversible computing
chips for AI infrastructure. She earned her PhD in Applied
Mathematics & Theoretical Physics from the University of Cambridge,
where her thesis explored reversible molecular computation
and scaling laws for physical computing systems. Joining Vaire in
2022, she leads hardware architecture and foundational research to
dramatically reduce energy dissipation in silicon chips. Dr. Earley
also serves as an Affiliate Lecturer at Cambridge, teaching computational
biology and biodesign. An innovator and community builder,
she co-founded the Molecular Programming Interest Group and has
authored multiple publications on reversible computing.
Michael Kagan, CTO, NVIDIA
Michael Kagan is the CTO (Chief Technology Officer) at NVIDIA
since May 2020. He joined NVIDIA through the Mellanox acquisition.
Michael was previously the CTO and co-founder of Mellanox,
which was founded in April 1999. From 1983 to April 1999, Michael
held a number of architecture and design positions at Intel Corporation.
While at Intel, Michael was the architect of the i860XP vector
processor, managed Pentium MMX design and managed the architecture
team of the Basic PC product group. Michael holds a BSc. in
Electrical Engineering from Technion – Israel Institute of Technology.
John Colgrove, Co-Founder and Chief Visionary Officer, Pure Storage
John Colgrove (Coz) is the Founder and Chief Visionary Officer of Pure Storage, where he drives the company's global technical strategy. Coz was one of the founding engineers at Veritas Software, which merged with Symantec in 2005, where his 20-year career culminated as Fellow and Chief Technology Officer for the Data Center Management Group. He was the primary architect for the hugely successful Veritas Volume Manager (VxVM) and Veritas File System (VxFS) and later served in various other engineering, management, and consultative roles. Prior to Veritas, Coz worked for Amdahl Corporation where he was a key contributor to the development of the UTS mainframe UNIX operating system kernel. He holds over 450 patents in the areas of computer system and reliable data storage design. Coz is a board member of Cerabyte, a pioneer of ceramic-based
data storage solutions. He has a Bachelor of Science degree from Rutgers University.
University.
Figure 1: John Colgrove – Pure Storage
John Colgrove (Coz) is the Founder and Chief Visionary Officer
of Pure Storage, where he drives the company’s global technical
strategy. He co-founded Pure Storage in 2009 after serving as Entrepreneur in Residence at Sutter Hill Ventures, where he saw enterprises beginning to embrace solid-state storage. Coz spent 20 years
at Veritas Software (later Symantec), rising to Fellow and CTO of the
Data Center Management Group. He was the primary architect of
the Veritas Volume Manager (VxVM) and File System (VxFS). Before
Veritas, he contributed to Amdahl’s UTS mainframe UNIX operating
system kernel. He holds over 450 patents in computer systems and
data storage and earned a B.S. from
AI workloads are growing exponentially, and energy consumption has become the defining challenge in data center operations. According to the International Energy Agency (IEA), electricity demand from data centers worldwide is expected to more than double by 2030, surpassing the total electricity consumption of Japan today. As NVIDIA Chief Scientist Bill Dally notes, it now costs over 1,000× more energy to move a byte of data than to compute on it. This simple reality is forcing a fundamental rethinking of architectures across compute, memory, storage, and networking. In modern AI clusters, as much as 80% of the power budget is consumed by data movement and communication—rather than computation itself. This CTO-Vision Panel brings together some of the industry’s most influential technology leaders to explore the existential question facing hyperscalers and enterprises alike: How can we break the energy ceiling? The stakes are high. Without a fundamental redesign in how we move and process data, AI infrastructure and cloud-scale architectures will hit energy ceilings long before their full potential is realized.
PRO
DSEC-201-1:
Data Defense: Advanced Protection Strategies and Compliance
Ballroom C (Santa Clara Convention Center, First Floor)
Track:
Data Security/Ransomware Protection
Organizer:
Rohan Puri, Staff Engineer, Samsung Seminconductor
"Rohan Puri serves as a Staff Engineer at Samsung Semiconductor Inc, bringing over 14 years of expertise in systems software development with a focus on file systems, storage technologies, and distributed systems. His technical leadership spans prestigious organizations including Veritas Technologies, Oracle, and various storage technology companies, where he has optimized file system performance, enhanced storage reliability, and designed advanced distributed storage solutions. Currently serving on the Conference Advisory Board for FMS'25 and as Co-industry Chair for MSST'24, he's also an active reviewer for ACM Transactions on Storage Journal and sits on Artifact Evaluation Committees for FAST'25 and OSDI'25. Rohan holds a Master's degree in Computer Science & Engineering from Pennsylvania State University and a Bachelor's in Information Technology from the University of Pune, India.
Presenters:
Presentation Session Description:
Eric Herzog, CMO, Infinidat
Presentation Title:
Next-Generation Data Protection: Building Cyber Resilience for the Modern Era
Presentation Abstract:
Cyber threats are escalating, and the numbers tell a stark story. In 2024, Fortune 500 CEOs ranked cybersecurity as the second-largest risk to their organizations and the stakes have never been higher. Is your organization prepared for these evolving risks? Does your cybersecurity strategy fully account for your enterprise storage? Did you know that a next-generation cyber-resilient storage solution can play a critical role in detecting and recovering from attacks? If you're uncertain about these answers, this session is designed for you. Discover:
● The essential features your enterprise storage infrastructure needs to ensure comprehensive cyber resilience
● Why immutable snapshots and logical air gaps are key to defending against attacks
● How near-instantaneous recovery can minimize downtime and financial loss
● Ways to strengthen your overall cybersecurity strategy and recover with confidence after an attack
Join us to explore how next-generation data protection can secure your enterprise against today’s most pressing cyber threats.
Author Bio:
Eric Herzog is the Chief Marketing Officer at Infinidat. Prior to joining Infinidat, Herzog was CMO and VP of Global Storage Channels at IBM Storage Solutions. His executive leadership experience also includes: CMO and Senior VP of Alliances for all-flash storage provider Violin Memory, and Senior Vice President of Product Management and Product Marketing for EMC’s Enterprise & Mid-range Systems Division.
Paul Suhler, Principal Engineer, SSD Standards, KIOXIA America, Inc.
Presentation Title:
Sanitization: Product Requirements and Legal Requirements
Presentation Abstract:
The need to eradicate recorded data on storage devices and media is well understood, but the technologies and methodologies are evolving. At the same time, technical standards and legal requirements intended to protect the privacy and integrity of data are also evolving. This talk will present an overview of sanitization technology, the standards environment, and the legal and other motivations for ensuring that sanitization of data is performed correctly.
Author Bio:
Paul Suhler has been active in the data storage world for thirty years, working for companies which include KIOXIA, Micron, WD/HGST, and Quantum. He is a software and firmware engineer, and has managed the development of storage devices for companies such as Quantum and Adaptec. He is the chair of the IEEE Security in Storage Working Group, and has contributed to standards developed by organizations such as NVM Express, SNIA, and the INCITS SCSI (T10) and Fibre Channel (T11) committees. He served as the Deputy Director of the USC Advanced Computer Architecture Laboratory, and commanded US Army combat engineer companies in Korea and California. He holds a PhD in computer engineering from the University of Texas at Austin. He is a Life Senior Member of IEEE and a member of ACM.
Rakesh Nadig, Ph.D. Student, SAFARI Research Group at ETH Zurich
Presentation Title:
CIPHERMATCH Homomorphic Encryption-Based String Matching via In-Flash Processing
Presentation Abstract:
Prior string matching algorithms that use homomorphic encryption are limited by high computational latency caused by the use of complex operations and data movement bottlenecks due to the large encrypted data size. In this work, we provide an efficient algorithm-hardware codesign to accelerate HE-based secure exact string matching. We propose CIPHERMATCH, which (i) reduces the increase in memory footprint after encryption using an optimized software-based data packing scheme, (ii) eliminates the use of costly homomorphic operations (e.g., multiplication and rotation), and (iii) reduces data movement by designing a new in-flash processing (IFP) architecture.
We demonstrate the benefits of CIPHERMATCH using two case studies: (1) Exact DNA string matching and (2) encrypted database search. Our software-based CIPHERMATCH implementation that uses our memory-efficient data packing scheme improves performance and reduces energy consumption by 42.9x and 17.6x, respectively, compared to the state-of-the-art software baseline. Integrating CIPHERMATCH with IFP improves performance and reduces energy consumption by 136.9x and 256.4x, respectively, compared to software-based CIPHERMATCH.
Author Bio:
Rakesh Nadig is a fourth-year Ph.D. student in the SAFARI Research Group at ETH Zurich, advised by Prof. Onur Mutlu. His main research areas are storage systems, heterogeneous storage/memory systems, near-data processing and machine learning in computer architecture. Prior to joining SAFARI, Rakesh worked as a Senior Staff Engineer at Samsung Semiconductor Research Labs in Bangalore, India. Rakesh obtained a master’s degree in Electrical and Computer Engineering from the University of California at Irvine.
David Schwaderer, CEO, ShapeShift® Ciphers
Presentation Title:
Permanently End Ransomware Attack Liabilities Easily and Simply
Presentation Abstract:
Relentless Quantum Computing advances threaten to undermine current mathematics-based encryption methods and are driving extensive global Public Key Infrastructure changes. Unfortunately, replacement Post Quantum Cryptography methods are also mathematics-based, and therefore vulnerable to algorithmic mathematical attacks. What is clearly needed is a non-mathematical, ubiquitous data encryption framework that neutralizes both classical and Quantum attacks while complementing and fortifying standards in a hybrid, crypto-agile manner. Deterministic Chaos Cryptography provides a singular opportunity to achieve this.
Based on evolutionary principles that have existed for over 500 years, Deterministic Chaos Cryptography is an overlooked solution to today's pressing data security vulnerabilities in the age of Ransomware. It can provide unsurpassed encryption strength, encryption/decryption performance, crypto-agility, processing efficiency, scalability, and simplicity.
Because of its high throughput performance, this protection can be retrofitted onto many vulnerable applications without changing them. This general audience technology presentation shows how.
Author Bio:
W. David Schwaderer is ShapeShift® Ciphers CEO. He has developed the first practical Deterministic Chaos Data Encryption methods that neutralize both classical and Quantum Computing decryption attacks. Before his current role, he supported Samsung's San Jose Memory Solutions Lab's (MSL's) Advanced Research and Development initiatives for over four years where he invented and co-invented several pending Samsung patent filings related to Machine Learning/Artificial Intelligence, advanced SSD firmware technologies, and data recovery technologies.
David has authored 11 technical books and personally created six commercial software programs. He has delivered presentations and tutorials at Usenix FAST’14 and FAST’16, Flash Memory Summit, Google, Oracle, Sun Labs, Symantec, Stanford, MIT, the Naval Post Graduate School, Samsung, and at Silicon Valley startups and public libraries.
David has a Masters Degree in Applied Mathematics from Cal Tech and a MBA from the University of Southern California. David's personal advocacy is the reason today's ZIP files have 32-bit CRC checking.
He is the IEEE Northern Nevada Section Chair and Northern Nevada Mensa First Vice Secretary.
In an era where quantum computing and escalating cyber threats challenge the very fabric of data security, our session brings together pioneering solutions to fortify information integrity and privacy. Uniting themes of innovation and resilience, we explore groundbreaking approaches such as Deterministic Chaos Cryptography, which offers a robust alternative to traditional mathematics-based encryption, safeguarding against both classical and quantum incursions. Complementing this, CIPHERMATCH introduces a novel algorithm-hardware co-design that transforms the landscape of homomorphic encryption, significantly enhancing performance and energy efficiency in secure data processing. As data sanitization technologies evolve alongside legal standards, we highlight the critical importance of comprehensive data erasure methodologies to ensure privacy compliance. Furthermore, in response to the escalating cyber risks identified by Fortune 500 CEOs, we delve into the critical role of cyber-resilient storage solutions, emphasizing the necessity of features like immutable snapshots and logical air gaps for rapid recovery post-attack. Together, these presentations offer a comprehensive framework for achieving next-generation data protection and cyber resilience.
Open
INDA-201-1:
NVMe State of the Union, Configurable Device Security and Quality of Service (QoS)
Ballroom D (Santa Clara Convention Center, First Floor)
Track:
Industry Associations
Chairperson:
Cameron Brett, Director, KIOXIA America, Inc
Cameron Brett is the Director of Enterprise SSD Marketing at Kioxia, where he manages a team of product line managers to drive product strategy and revenue growth. Cameron has over 18 years of product marketing and management experience in storage technology and has previously held managerial positions at QLogic, PMC-Sierra, Broadcom and Adaptec. Throughout his career in high-tech product marketing, he has focused on storage for enterprise and small/medium business servers and worked to bring new generations of storage technology to market. His area of expertise includes Flash/SSD storage, virtualization, convergence and cloud technologies
Presenters:
Presentation Session Description:
Daniel Helmick, Principal SSD Architect, Samsung
Presentation Title:
Unlocking QoS Potential – Optimizing SSD Performance for Emerging Standards
Presentation Abstract:
Building on the momentum of Live Migration and Flexible Data Placement, NVM Express® (NVMeTM) is ratifying TP4176 Quality of Service for PCIe Bandwidth and IOPS for a Controller. However, implementing this standard in real-world SSDs can be complex. This presentation will provide clarity on the standardized modes for QoS control, including key parameters and simplified control knobs. Through example use cases and scenarios, we will explore reasonable settings for meeting customer requirements, as well as situations where "best effort" approaches may be necessary. This talk aims to initiate a conversation on intelligent QoS parameter setting on the host side, with a focus on achieving specific goals and exploring the potential for consistency across SSD vendors and generations.
Author Bio:
Dan is a Principal Architect focusing on future generation NVMe SSDs for Samsung Semiconductor. A strong background in HDD Control Systems has folded into performance FW in SSDs and future product architectures for storage products of several different medias. Dan has worked closely with customers to understand future requirements, develop industry leading standards to achieve those requirements, and design the product feature for servicing the new standardized feature. He has been a primary SSD Architect shaping features such as Zoned Namespaces (ZNS), Flexible Data Placement (FDP), Live Migration (LM), Quality of Service (QoS), and many more industry leading features.
Andres Baez, Software Engineer, Solidigm
Presentation Title:
How easy is it to manage your NVM subsystem’s personality?
Presentation Abstract:
The NVM Express working group has been working on finding solutions to allow NVM subsystems to have configurable personalities. This talk will give details on TP4163 Configurable Device Personality and how this new feature is going to add value to SKU reduction and secure specific NVM subsystem configurations for end customer engagements. OEMs and platform providers will be able to better manage inventories and prepare products for delivery in a more efficient way using this new NVMe capability. The talk will also cover how personalities may be protected from further changes by an owner unless the personality supports authentication, and the host is authorized to make changes.
Author Bio:
Andres Baez is a Software Engineer at Solidigm with extensive experience as firmware engineer and software architect for SSD storage devices. Andres collaborates with customers to define new and innovative features and capabilities to enhance the NVMe standard. Andres has a B.S. in Computer Engineering and a MS in Computer Science from the University of Arkansas.
Fred Knight, Principal Engineer, KIOXIA America, Inc
Presentation Title:
NVMe® Technology: The Command Set for the Modern Virtualized World
Presentation Abstract:
This presentation provides an overview of the NVMe® standards roadmap and reviews the newest NVMe features like NVM Subsystem Migration, Quality of Service, Fabric Resiliency, and more. Our technical experts will also review how NVMe technology will support storage virtualization applications for AI workloads in addition to how it continues to support cloud and enterprise applications.
NVMe technology is the language of storage, synonymous with high-performance storage and widespread adoption in client, cloud, enterprise and even AI applications in the modern virtualized world. The NVMe architecture consists of a set of features that are all able to work together to support multiple forms of virtualized, configurable infrastructure for modern applications.
Author Bio:
Fred is a Principal Engineer at KIOXIA. Fred has over 45 years of experience in the computer and storage industry. He currently represents KIOXIA in several US national standards bodies, international standards bodies and several Industry Associations, including SNIA, NVM Express, Trusted Computing Group (TCG), INCITS SCSI (T10), and INCITS ATA/ACS (T13). Previously, Fred was the chair of the SNIA Hypervisor Storage Interfaces working group, the primary author of the SNIA HSI White Paper, the author of the IETF iSCSI update RFC, and the editor for the SCSI SAM-6 standard and SCSI SES-3 standard.
Fred received several awards for excellence and innovation while at NetApp. He also received the INCITS Technical Excellence Award for his contributions to both T10 and T11 as well as the INCITS Merit Award for his longstanding contributions to the international work of INCITS. He also received the prestigious IEC 1906 award in 2022 for his work on international standards through IEC. Fred is also the holder of several US Patents.
He contributes to technology and product strategy and serves as a consulting engineer to product groups across the company. Prior to joining KIOXIA, Fred was a Principal Engineer at NetApp, and a Consulting Engineer with Digital Equipment Corporation, Compaq, and HP where he worked on clustered operating system and I/O subsystem design.
Festus Hategekimana, Storage Security Architecture, Solidigm
Festus Hategekimana, Ph.D., is a storage security engineer at Solidigm Technology, where he designs cryptographic protocols for SSD data-at-rest protection and platform attestation features. He earned his Ph.D. in computer engineering from the University of Arkansas, specializing in isolation security architectures that enable secure FPGA sharing in multi-tenant cloud environments.
Festus is a published author in multiple IEEE conferences and journals, and currently serves as a technical contributor to several industry standards bodies—including the Trusted Computing Group (TCG), NVM Express (NVMe), the Open Compute Project (OCP), and the Distributed Management Task Force (DMTF)—where he helps define specifications that advance platform security and trusted storage technologies.
NVM Express® (NVMe®) technology has become the language of storage and is now synonymous with high-performance storage and with widespread adoption in client, cloud, enterprise and event AI applications. Although initially developed for direct-attached PCIe® SSDs, NVMe architecture is now widely used in both direct-attached and fabric-attached applications.
This session will provide an overview of the NVMe standards roadmap and reviews the newest NVMe features like NVM Subsystem Migration, Quality of Service, Fabric Resiliency and more. We will also discuss how NVMe technology will continue to support Cloud and Enterprise Applications and emerging applications like AI.
The session will also provide two deep dive presentations into new NVMe features Configurable Device Security and Quality of Service (QoS). The Configurable Device Security presentation will discuss how this new feature will add value to SKU reduction and secure specific NVM subsystem configurations for end customer engagements, and how OEMs and platform providers will be able to better manage inventories and prepare products for delivery in a more efficient way using this new NVMe capability.
The QoS presentation will discuss how to implement QoS on an SSD and provide clarity on the standardized modes for QoS control, including key parameters and simplified control knobs. Through example use cases and scenarios, the presentation will explore reasonable settings for meeting customer requirements, as well as situations where "best effort" approaches may be necessary.
PRO
OMEM-201-1:
Emerging Memory Architectural Advancements
Ballroom E (Santa Clara Convention Center, First Floor)
Track:
Other Memory Technologies
Organizer + Chairperson:
Dave Eggleston, Sr Business Development Manager, Microchip Technology
Dave Eggleston is Sr. Business Development Manager at Microchip. Dave's extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at Sandisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.
Presenters:
Presentation Session Description:
Jim Handy, General Director, Objective Analysis
Presentation Title:
Is the World Ready for New Memories?
Presentation Abstract:
When will today’s memory technologies give way to some new technology? FRAM has been around since 1952, and PCM since 1969, but they are still waiting in the corners, along with MRAM and ReRAM, OR ARE THEY? Today the market is at the cusp of great change, with these memories vying to fill an enormous void left by embedded NOR flash which can’t scale beyond 28nm, soon to be followed by embedded SRAM, which is also running into its own scaling issues. This presentation outlines these technologies and others, and lays out a roadmap shows how today’s technologies will give way to new memories in today’s applications as well as new ones in AI and chiplets. Join Jim Handy and Tom Coughlin for a fun exploration of where new memory technologies are going, and explain how these memories will change the memory business landscape, bring persistence at memory speeds to the world of CXL, and even simplify AI processors while lowering their enormous energy consumption through novel in-memory computing architectures, including data-centric computing approaches like neural networks.
Author Bio:
Jim Handy of Objective Analysis is a 35-year semiconductor industry executive and a leading industry analyst. Following marketing and design positions at Intel, National Semiconductor, and Infineon he became highly respected as an analyst for his technical depth, accurate forecasts, industry presence, and numerous market reports, articles, white papers, and quotes. He posts blogs at www.TheMemoryGuy.com, and www.TheSSDguy.com.
Younghoon Min, Research Principal Engineer, SK hynix
Presentation Title:
Indirect Memory Access Acceleration on HBM for AI Applications
Presentation Abstract:
Indirect memory access is a critical bottleneck for AI, graph analysis and sparse linear algebra applications, where the values of one data array are used to generate the fetching addresses of another array. It often causes irregular data accesses with poor temporal and spatial locality that are difficult to be captured by conventional hardware prefetchers. If only one-eighth of every cache line fetched from memory is used, then the memory bandwidth and power are wasted resulting in poor performance. These applications often manipulate complex, linked data structures, leading to random access patterns and high latency due to cache pollution and inefficient utilization of memory bandwidth. To address these challenges, we propose the Acceleration of Indirect Memory Access (AIA) feature, which aims to alleviate the memory bottleneck associated with indirect memory access in traditional applications. We adopt AIA functions to the HBM for performance and power efficiency.
By leveraging HBM and the parallelizable streaming access patterns of graph processing workloads, AIA can significantly enhance the performance of various indirect memory access patterns and sparse matrix multiplicati
Author Bio:
Younghoon Min is a principal engineer of Memory Solution Research at SK hynix in San Jose CA. He is currently interested in storage and memory solutions for AI and HPC such as optimized storage systems for LLM training and efficient memory architecture for irregular memory accesses. Prior to joining SK hynix, he had developed the S/W platform and middleware of Smart phones and led some major projects in Samsung for more than 15 years.
Nika Mansouri Ghiasi, Ph.D. Student, SAFARI Research Group at ETH Zurich
Presentation Title:
RevaMp3D: Architecting the Processor Core and Caches in Monolithic 3D Systems
Presentation Abstract:
Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple memory and logic layers in a single chip with fine-grained connections, which significantly alleviates main memory bottlenecks. We show for a variety of workloads on a state-of-the-art M3D system that the performance/energy bottlenecks shift from main memory to the processor core and caches. Hence, there is a need to revisit current core and cache designs that have been conventionally tailored to tackle the memory bottleneck. However, no prior work comprehensively examines the implications of M3D integration of logic and memory layers on the core and cache design.
Our goal is to redesign the core and cache hierarchy, given the fundamentally new trade-offs of M3D. To this end, we (i) conduct a rigorous design space exploration of the processor core and caches to understand the implications of the shifted bottlenecks on system design, and (ii) based on these implications and by leveraging the unique opportunities of M3D, design a new M3D system, RevaMp3D. On a wide range of real-world workloads, RevaMp3D provides 81% average speedup and 35% average energy reduction over the baseline M3D system.
Author Bio:
Nika Mansouri Ghiasi is a Ph.D. student in the SAFARI Research Group at ETH Zurich, working with Professor Onur Mutlu. Her current research interests are in computer architecture and computational biology, focusing on 1) storage systems, large-scale bioinformatics applications, and their interactions, and 2) emerging technologies such as ultra-dense 3D integrated systems.
Ismail Emir Yuksel, Ph.D. Student, SAFARI Research Group at ETH Zurich
Presentation Title:
Understanding the Computational Capabilities of COTS DRAM Chips
Presentation Abstract:
Processing-using-DRAM (PuD) is an emerging paradigm that leverages the analog operational properties of DRAM circuitry to enable massively parallel in-DRAM computation. PuD has the potential to reduce or eliminate costly data movement between processing elements and main memory.
We experimentally demonstrate various previously-unknown computational capabilities of unmodified commercial off-the-shelf (COTS) DRAM chips: COTS DRAM chips are capable of 1) performing functionally-complete bulk-bitwise Boolean operations: NOT, NAND, and NOR, 2) executing up to 16-input AND, NAND, OR, and NOR operations, and 3) copying the contents of a DRAM row (concurrently) into up to 31 other DRAM rows.
We evaluate the robustness of these operations across data patterns, temperature, and voltage levels. Our results show that COTS DRAM chips can perform these operations at high success rates (>94%). These findings demonstrate the fundamental computation capability of DRAM, even when DRAM chips are not designed for this purpose, and provide a foundation for building new and robust PuD mechanisms into future DRAM chips and standards.
Author Bio:
Ismail Emir Yuksel is a 2nd year PhD student at the SAFARI Research Group in ETH Zurich, working with Prof. Onur Mutlu. His current broader research interests include processing-in-memory, computer architecture, and DRAM robustness.
This session delves into the transformative potential of emerging memory technologies and architectures, highlighting how they are poised to redefine the landscape of computing. Presenters explore a range of advancements, from innovative memory technologies like FRAM, PCM, MRAM, and ReRAM, to cutting-edge solutions like the Acceleration of Indirect Memory Access (AIA) that target bottlenecks in AI and graph processing applications. The session also examines the implications of Monolithic 3D (M3D) integration, which shifts performance and energy challenges from memory to processor cores, prompting a redesign of core and cache architectures. Additionally, the Processing-using-DRAM (PuD) paradigm is showcased, unveiling the computational capabilities of commercial DRAM chips to perform complex operations in-memory, reducing the need for costly data movement. Together, these presentations underscore a common theme: leveraging novel memory architectures and technologies to enhance computational efficiency, power performance, and open up new possibilities in AI and data-centric applications.
PRO
QLCP-201-1:
Multi-Level Cells Part 1
Ballroom F (Santa Clara Convention Center, First Floor)
Track:
QLC and PLC
Organizer + Chairperson:
Brian Berg, President, Berg Software Design
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley Section, Director and past Chair of the Consultants Network of Silicon Valley, Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for Outstanding Service to the Consulting and Electrical Engineering profession, and the 2012 Outstanding Leadership and Professional Service Award for Region 6.
Presenters:
Presentation Session Description:
Hadi Sayed, Senior Solutions Engineer, DapuStor
Presentation Title:
Petabyte-Capacity SSDs by 2030: Is It Possible, and How?
Presentation Abstract:
Current projections suggest petabyte-scale SSDs may not arrive until 2035. However, optimizing technologies could make this feasible by 2030. Key hurdles include the slowing of NAND flash density growth, and the impracticality of relying on DRAM for L2P mapping at petabyte scales due to bottlenecks created by high DRAM requirements and space constraints.
To overcome these challenges, we propose two innovations: (1) hardware-accelerated compression boosts storage density without expanding flash memory, achieving 2x to 3x compression ratios while maintaining performance, and (2) CXL-enabled memory expansion offloads L2P index management to external modules like DRAM or PCM, alleviating DRAM bottlenecks and enhancing scalability.
Preliminary tests show that (a) compression adds only ~2µs latency, with negligible impact on throughput, and (b) CXL memory expansion, with latencies under 300ns, has no measurable effect on SSD performance.
By 2030, these technologies could enable scalable, petabyte-class SSDs to meet the demands of AI and big data, transforming data storage and processing.
Author Bio:
Hadi Sayed is a Senior Solutions Engineer at DapuStor, specializing in enterprise SSD solutions and NAND flash technologies. He leads technical sales efforts across the Americas and brings deep industry expertise in storage architecture and customer-driven solution design from previous roles at Swissbit and CNEX Labs.
Luis Chamberlain, Principal Engineer, Samsung
Presentation Title:
Enabling Large Block Sizes to Facilitate Adoption of Large Capacity QLC SSDs
Presentation Abstract:
The size of SSD Indirection Units (IUs) is expected to increase proportional to SSD capacity, and current market trends suggest capacity requirements keep exploding. Originally a 17-year old R&D effort, support for Large Block Sizes (LBS) means having the ability to support filesystem block sizes larger than your system page size. Historically pursued to help with testing compatibility, this R&D effort also allows for seamless adoption of SSDs with large IUs. Although Linux specific, there are important lessons learned to facilitate the adoption of large IUs on non-POSIX environments.
This presentation will discuss the evolution of considering larger LBA formats to embracing larger atomics which databases also profit from. Emphasis will be put on the implications of Atomic Write Unit Power Fail (AWUPF) >= Namespace Preferred Write Granularity (NPWG) for storage minimum IOs.
Author Bio:
Luis is a Principal Engineer at Samsung focusing the development and adoption of future Samsung NVMe storage & memory solutions on open ecosystems. Luis has been working on the Linux kernel for over 17 years, and his fields of interest has changed over time, from Wireless, Bluetooth, Ethernet, to virtualization and lately with storage and memory technologies. He has also helped spearhead different new automation open source projects such as the Linux kernel backports project and as of late the kdevops project.
Sumit Gupta, Software Engineer, Meta Platforms
Presentation Title:
QLC storage: balancing power, cost and performance
Presentation Abstract:
The explosive growth of data and increasing concern for power efficiency have created a pressing need for innovative storage solutions. QLC technology addresses these challenges by forming a middle tier between HDDs and TLC SSDs providing higher density, improved power efficiency, and cost-effectiveness.
While directionally a QLC tier seems to be the right path given that the HDDs are getting colder with increasing density (decreasing BW/TB) and NAND prices also dropping with increasing deployment, there still remain many challenges in both software and hardware space for QLC adoption. The presentation dives into some of these challenges and how Meta is looking to solve them.
Author Bio:
Sumit has been in the storage industry for 30 years, and he has been deeply involved in flash-based storage as part of industry efforts including FDP. He has been in Meta since 2020 where he has been working on the server side of the Tectonic stack to improve it for flash and AI. Previously, he worked at Sun Microsystems as part of the open source COMSTAR framework, as well as at Google, VMware, and HPE.
David Verburg, System Technical Staff Member, Storage Technology, IBM
Presentation Title:
QLC Considerations in the Age of AI
Presentation Abstract:
The explosion of AI applications has led to a sudden shift in customer appetite for large, low cost, SSD drives. We will examine some of the drivers causing customers to consider in pivoting to QLC for AI applications, including density, performance, reliability, and cost. We will also look at some of the industry trends that may accelerate or delay the transition, along with workloads or customer use cases that may transition sooner because of factors that are favorable in leveraging QLC workloads. We will also look at the tradeoffs with HDD, including sustainability, cost factors, quantum safe, and market trends.
Author Bio:
Dave Verburg is a Senior Technical Staff Member at IBM responsible for storage device strategy and quality. He has been with IBM since 1991, starting in disk drive manufacturing, and spending the last 15 years of his career working with HDD and SSD quality and technology. Dave has presented to IEEE, at conferences including FMS, and at the Manufacturing Leadership Council while receiving an ML100 award in 2019. Dave received a MS in Electrical Engineering from the University of Minnesota in 1996 and received a BS in both Electrical Engineering and Computer Science from the South Dakota School of Mines and Technology in 1991. Dave is an active volunteer, helping with computer systems and mentoring for the youth at his church and teaching robotics to school children. Dave also can speak both Spanish and Mongolian and uses his language skills to help Samaritan's Purse Children's heart project as they provide life changing surgery for children.
This session brings together a diverse range of presentations that delve into the evolving landscape of SSD technology and storage solutions, driven by the surging demand for data capacity and efficiency. A common theme is the pursuit of enhanced storage solutions to meet the exponential growth in data and the increasing power efficiency requirements. The discussions highlight the potential of larger Indirection Units (IUs) and Large Block Sizes (LBS) in SSDs, enabling seamless adoption of high-capacity drives, and the strategic role of QLC technology as a middle tier between traditional HDDs and TLC SSDs. The session also addresses the challenges in optimizing technologies for petabyte-scale SSDs, such as overcoming NAND flash density limitations and DRAM bottlenecks through hardware-accelerated compression and CXL-enabled memory expansion. Moreover, the presentations explore the impact of AI on storage demands, emphasizing the need for cost-effective, high-performance solutions like QLC to support AI applications. Together, these insights provide a comprehensive view of the future of data storage, highlighting innovative strategies and technologies poised to transform storage capabilities by 2030.
PRO
SSDT-201-1:
SSD Technologies for AI and the Data Center
Ballroom G (Santa Clara Convention Center, First Floor)
Track:
SSD Technology
Organizer + Chairperson:
Erich Haratsch, Senior Director Architecture, Marvell Semiconductor
Erich Haratsch is the Senior Director of Architecture at Marvell, where he leads the architecture definition of SSD and storage controllers. Before joining Marvell, he worked at Seagate and LSI, focusing on SSD controllers. Earlier in his career, he contributed to multiple generations of HDD controllers at LSI and Agere Systems. Erich began his career at AT&T and Lucent Bell Labs, working on Gigabit Ethernet over copper, optical communications, and the MPEG-4 video standard. He is the author of over 40 peer-reviewed journal and conference papers and holds more than 200 U.S. patents. A Senior Member of IEEE, Erich earned his MS and PhD degrees from the Technical University of Munich, Germany.
Presenters:
Presentation Session Description:
Rory Bolt, Senior Fellow, KIOXIA America
Presentation Title:
High IOPS SSD for AI Applications
Presentation Abstract:
The increasing demands of artificial intelligence on storage have created use cases requiring extremely high random read IOPS. This presentation will touch on these use cases as well as progress on investigations into extremely performant SSDs leveraging low latency flash. The general attributes of a proposed device and its benefits for GPU local storage will be covered, as well as some impacts to the design of SSD controllers.
Author Bio:
Rory Bolt is a senior fellow at KIOXIA America and leads the forward-looking technology and storage pathfinding group for SSDs. He has more than twenty-five years of experience in data storage systems, data protection systems, and high-performance computing with a pedigree from marquee storage companies. Rory has been granted over 12 storage related patents and has several pending. Rory has a BS in Computer Engineering from UCSD.
Rahul Mitchell Jairaj, Director, Technical Product Management Client SSD, Micron Technology
Presentation Title:
Storage Optimizations for the AI PC
Presentation Abstract:
With the proliferation of AI tools and language models across PCs and other connected edge devices there is an ever growing need to optimize our hardware for driving enhanced user experience. Micron has been pioneering key innovations with industry partners on client storage technology for host direct intelligent data placement that allows for improved user experience for the whole industry. This presentation dives into the role of storage in AI PCs and the feature enhancements that are planned to optimize storage for AI workloads on the edge.
Author Bio:
Rahul Mitchell Jairaj is the Director of Technical Product Management for Micron's Client SSD Business Unit. He has spent his career working on NAND flash storage at Micron from components engineering to SSD product management. He holds a Masters degree in Semiconductor Device Physics from Clemson University and a bachelor's in electrical engineering. Outside work, Rahul is passionate about collecting fossils and amateur microscopy.
Oleg Kragel, Sr Technologist, Sandisk Flash Products Group
Presentation Title:
Transparent Host Memory Buffer (THMB): DRAM-Free Path to High-Performance SSDs
Presentation Abstract:
Transparent Host Memory Buffer (THMB) bridges the performance gap between DRAM-based and DRAM less SSDs that are used in mobile computing devices. Unlike conventional HMB (CHMB) solutions, THMB embeds minimal L2P mapping data (LBA + version) directly into IO commands, thus reducing SSD controller, Firmware and PCIe overheads. This approach enables DRAMless SSDs using HMB to achieve performance comparable to DRAM-based SSDs.
Attendees will gain insights into the THMB's approach, explore benchmark data demonstrating its >80% performance gains over CHMB, and discover the core innovations that make THMB a cost-effective, high-performing solution for DRAMless SSDs.
Author Bio:
Oleg has been with Sandisk/Western Digital for 13 years, focusing on systems architecture, performance analysis, and developing algorithms for NAND flash management. Prior to joining Sandisk, he worked at Softeq Development as firmware engineer.
This session delves into the transformative role of storage technologies in optimizing AI workloads across various platforms, from high-demand AI applications to mobile computing devices. The presentations collectively highlight the critical advancements in storage solutions designed to meet the unique demands of AI, including the development of extremely performant SSDs and innovative storage technologies that enhance user experience in AI-driven PCs. A common thread is the emphasis on bridging the performance gaps in storage efficiency and effectiveness, as demonstrated by the Transparent Host Memory Buffer (THMB) technology, which significantly elevates the performance of DRAMless SSDs to rival that of DRAM-based solutions. Attendees will explore how these cutting-edge storage innovations are reshaping the landscape of AI applications, offering enhanced performance, reduced latency, and cost-effective solutions that are essential for sustaining the rapid evolution of AI technologies.
09:35 AM to 09:45 AM
Open
BRK:
Wednesday AM Refreshment Break
Main Lobby/Great America Lobby (SCCC, First Floor/Great America Meeting Rooms, Second Floor)
Track:
General Events
General Event Description:
Description Not Available
09:45 AM to 10:50 AM
PRO
AERO-202-1:
Aerospace and Outer Space Data
Ballroom B (Santa Clara Convention Center, First Floor)
Track:
Aerospace and Outer Space Data
Organizer + Chairperson:
Paul Armijo, President and CEO, Armijo Innovations
Paul Armijo is the President & CEO at Armijo Innovations. He has senior leadership in roles including CTO in space and technology development industry at General Dynamics Mission Systems, Northrop Grumman, BAE Systems Space & Mission Systems, Frontgrade Technologies, GSI Technology, Secure Quantum Services, and Avalanche Technology. He has had the privilege of leading numerous flagship programs and technology development efforts over his career to further enable the space community. He has served various technical and session chairs as well as presented at various conferences in the space, memory, and AI community like SEE/MAPLD, ODSC, SPWG, HEART, NSREC, Space Computing, RHET, among many others. Paul received his B.S. in electrical engineering from Arizona State University.
Presenters:
Presentation Session Description:
Crystal Chang, Director, ATP Electronics., Inc
Presentation Title:
Enhance Radiation Tolerance and SSD recovery strategies
Presentation Abstract:
When satellites operate in orbit, there is no way to replace components. Unlike radiation-hardened components, which are built to withstand intense radiation, radiation-tolerant SSD drives rely on error correction and self-healing to manage the effects of radiation. We will share methods combining hardware, firmware, and software tools to prolong the life of SSDs in space missions.
Author Bio:
With 15 years of experience in product development and segment enablement at ATP, Crystal specializes in exploring new technologies and industry requirements, including the Aerospace and LEO satellite markets. Crystal also holds an MBA from the University of Newcastle Upon Tyne, UK.”
George Williams, Chief AI Officer, Armijo Innovations
Presentation Title:
Space Age Memories for the Modern Space Age
Presentation Abstract:
We propose a panel consisting of 3-5 subject matter experts in researching, deploying, and maintaining micro-electronic memory systems in satellites, lunar, and deep space systems. Each presenter will get about 15-20 of slide content and then we propose about 20 minutes of panel Q&A. The agenda will be as follows:
* An introduction to the challenges of micro-electronics in space
* A review of currently available technology, limitations and cost
* A review of novel material science research in radiation tolerant memories
* A presentation on the current business landscape of space micro-electronics and opportunities in the next decade
* A presentation/discussion on the practicality/possibility of data centers on the moon and space
Author Bio:
George Williams is Chief AI Officer at Armijo Innovations. He has held senior leadership roles in data science and artificial intelligence in industry at GSI Technology and Apple's New Product Architecture, as well as in academia at New York University's Courant Institute. He can talk on a broad range of topics at the intersection of e-commerce, machine learning, cybersecurity, computer hardware, computer science, and cognitive computing. He is an author of several research papers in computer vision and deep learning, published at NeurIPS, CVPR, ICASSP, ICCV, and SIGGRAPH. George is regularly invited to present at meetups and technology conferences, including recent seminars at Blackhat, Open Data Science Conference, Apache Spark Summit, JupyterCon, AnacondaCon, and Caltech’s Space Computing. He served as organizer and track chair for the Valleyml.ai conference and as a workshop program manager for the Vector Search Challenge at NeurIPS.
Shiuan-Hao Kuo, Project Manager, Silicon Motion Inc.
Presentation Title:
SSD Controller for Space Applications
Presentation Abstract:
Modern data storage is expanding exponentially, encompassing a wider range of applications than ever anticipated. The environments in which data is stored are becoming increasingly challenging. This talk addresses the unique challenges of storage in outer space applications, focusing on two critical aspects.
Outer space is characterized by extreme temperature fluctuations, which can accelerate wear and degradation in NAND flash memory. To address this, SSD controllers must employ advanced algorithms to effectively monitor and maintain the health of storage devices.
The data / control path integrity is also challenging. High-energy particles passing through circuits can cause soft errors, a phenomenon that occurs even on Earth. Without the protective shield of the ionosphere, these errors pose a significant threat to data reliability in space.
Author Bio:
Shiuan-Hao Kuo is an experienced project manager with 9 years at Silicon Motion, specializing in NAND interface architecture and pioneering research in LDPC (Low-Density Parity-Check) code algorithms. He played a key role in SMI’s early-stage development of the SCA interface, working closely with NAND vendors to explore its potential and build strategic partnerships.
Dr. Kuo has presented at multiple FMS events, delivering insights on industry-leading LDPC topics and providing in-depth analysis of SCA NAND interfaces. He holds a PhD in error correction coding from National Taiwan University and an MSEE from National Tsinghua University, both in Taiwan.
This session delves into the intricate challenges and innovative solutions surrounding data storage and micro-electronic systems in the demanding environment of outer space. Common themes across the presentations include the resilience and longevity of storage systems, particularly solid-state drives (SSDs), amidst the harsh conditions of space such as intense radiation and extreme temperature fluctuations. Emphasis is placed on the integration of hardware, firmware, and software tools to enhance error correction and self-healing capabilities, ensuring data reliability and device durability. The session also explores the latest advancements in radiation-tolerant materials and the evolving business landscape of space micro-electronics, highlighting opportunities for future developments, including the ambitious concept of data centers on the moon. Through expert insights and a panel discussion, this session provides a comprehensive overview of current technologies, their limitations, and the potential for groundbreaking advancements in space data storage.
PRO
AIML-202-1:
Generative AI Part 2
Ballroom A (Santa Clara Convention Center, First Floor)
Track:
AI and ML Applications
Chairperson:
Kapil Sethi, Director, New Business Planning , Samsung Semiconductor
Kapil is currently Director in the DRAM New Business Planning team at Samsung Semiconductor where he leads product planning, customer enablement and business development for Samsung’s CXL® technology based products. He has been at Samsung Semiconductor for more than 4 years. Previously, Kapil has worked as Technical Product Manager leading multi-million dollar product lines.
Organizer:
David McIntyre, Director Product Planning, Samsung Electronics
David McIntyre focuses on computational storage acceleration solutions development and strategic business enablement for cloud to edge applications including AI inference/video analytics, database processing and blockchain networks. He has held senior management positions with IBM, Samsung, Xilinx, Intel (formerly Altera) and at Silicon Valley startups. He has consulted for institutional investors including Fidelity, Goldman Sachs and UBS. David is a frequent presenter and chairperson at the Flash Memory Summit and other technical conferences including SNIA.
Presenters:
Presentation Session Description:
Jongseok Jung, Data Engineer, SK hynix
Presentation Title:
Generative AI Solution for Data Governance
Presentation Abstract:
Data governance is essential for ensuring compliance with data standards and maintaining data quality. It involves the implementation of policies, procedures, and responsibilities that oversee the management, usage, and protection of data within an organization. However, SK Hynix is not yet fully prepared in this area, so we have decided to make a generative AI solution ourselevs and to help to establish foundational information (standards) for an efficient data governance framework.
The reason for this decision is that effective data governance ensures that data is accurate, consistent, and secure, enabling organizations to make informed decisions and meet smart factory's requirements in the future. By establishing clear guidelines and accountability, we expect that data governance will help maximize the value of data as a strategic asset.
Author Bio:
Since 2018, Jongseok Jung has been employed at SK hynix.
He holds a master's degree in New Material Engineering from Korea University, where also completed my thesis and have published a paper as the first author in the international journal "Coatings," with an impact factor of 2.9.
He has submitted six papers and published one at the SK hynix internal academic conference.
Ronen Hyatt, CEO and Co-Founder, UnifabriX
Presentation Title:
How to use memory pooling to accelerate AI workloads and reduce cost
Presentation Abstract:
In this presentation, you'll learn:
· How a real Memory Pool is working include live demo
· How CXL3.1 is implemented today with the support of Dynamic Memory Allocation (DCD)
· How to create multiple CXL links to hosts for maximum bandwidth
· Techniques to reduce latency and accelerate LLM and RAG workloads
· Ways to save memory costs by using a mix of DDR5/DDR4 and SCM
· Sharing AI models across multiple platforms without data movements
· Implementation and value of UALink in Memory Pool
Don't miss this opportunity to gain valuable insights and improve your AI system's efficiency.
Author Bio:
Ronen is an expert in system architectures with over 25 years of experience leading and delivering silicon designs running Compute acceleration cores, DSAs, CXL and Ethernet connectivity, RDMA networking and programmable switches. Ronen has served as CTO and lead architect in multiple leading silicon companies, including Intel, where he co-founded the IPU (Infrastructure Processing Unit) and initiated the programmable Ethernet connectivity development. Ronen is Founder and CEO at UnifabriX, a system and silicon startup targeting the Memory Wall with CXL-based Software-Defined Memory Pools and CXL Fabrics. Ronen holds more than 40 patents (some pending),
an MSc and BSc in Computer Engineering from Technion Institute of Technology, and MA in Law from Bar-Ilan University.
Prasad Venkatachar, AI Solutions Director, VAST DATA
Presentation Title:
Agentic AI – The Next Evolution of Gen AI
Presentation Abstract:
Agentic AI – The Next Evolution of Gen AI
The recent emergence of Agentic AI marks a paradigm shift towards more autonomous,
decision-making entities capable of planning, reasoning, and taking actions in complex
environments. This session explores the core distinctions between Generative AI and
Agentic AI, highlighting key characteristics, technological advancements, and
applications across industries. It also delves into how we can navigate from passive
content generation in Gen AI to active problem-solving intelligence using core building
blocks of Agentic AI architecture with RAG.
Author Bio:
Prasad Venkatachar is the Director of AI Solutions Engineering at Vast Data. He is focused on building AI Solutions by working with AI partners like NVIDIA. Prasad Venkatachar is an IEEE Senior Member, BCS Fellow, serving as Conference Advisory Board for Future of Memory and Storage, Google Databases Partner Advisory and served as Lenovo Technology Innovation panel member and Microsoft Data and AI Partner Advisory Member. As subject matter expert in Data and Ai filed served fortune 500 enterprise customers to deliver business value outcomes for Datacenter and Cloud deployments. He has good experience and certified in Multiple AI/Gen AI certifications from Google, Nvidia, Deep Learning and Cloud (AWS/Azure/GCP/IBM) Database (Oracle/DB2/Azure Data) and A regular speaker in Industry Conferences: Microsoft Ignite, Oracle Open World, Gartner Conference, Developer conferences: Pass Summit, Oracle users’ group, Percona live and SNIA, SDC, Future of Memory & Storage. Prior to Vast Data he worked at Pliops, Lenovo, Hewlett Packard Enterprise.
Behnam Eliyahu, CTO APAC & SEMEA, Zadara
Presentation Title:
Generative AI on the Edge Cloud
Presentation Abstract:
GPUs and Artificial Intelligence (AI)
Overviews in Bird’s Eyes
Main Industry Trends
Rapid Rise of GPUaaS and AI Workloads
Sovereign AI is Gaining Momentum
Inference-as-a-Service on Sovereign AI Cloud
Retrieval-Augmented Generation (RAG)
Use Cases & Demos
GPUaaS
Sovereign AI Use Cases, such as: Customized Generative AI for Anyone
GPUaaS Setup
Author Bio:
With over 18 years in the storage industry, Behnam has led cross-functional teams in designing and developing firmware and software, with expertise spanning NOR, NAND, SSD, AFA, and SDS technologies. His career includes roles in both R&D and technical product marketing, managing technical customers and partners globally for companies like Intel, Micron, WD, and startups such as Excelero. Behnam specialties include Cloud, Virtualization, Storage, Networking, and Distributed Systems.
This session explores the dynamic intersection of data governance, AI-driven memory management, and the evolution of generative AI into more autonomous systems. It underscores the critical role of effective data governance in ensuring data accuracy, consistency, and security, with SK Hynix's initiative to develop a generative AI solution as a foundational move towards robust data management. The session also delves into advanced memory solutions like CXL3.1 and memory pooling, showcasing techniques to optimize AI system efficiency through latency reduction and cost-effective memory strategies. Further, the emergence of Agentic AI is highlighted as a transformative force, enhancing AI’s capability to autonomously plan and execute decisions, thus shifting from passive content generation to active problem-solving. This theme is complemented by the exploration of GPUaaS and Sovereign AI, emphasizing their pivotal role in supporting complex AI workloads and enabling customized AI solutions. Together, these presentations offer a comprehensive view of the technological advancements shaping the future of AI and data management across industries.
Open
BMKT-202-1:
Data Intensive Customer Solutions: Customer Experience
GAMR-1 & 2 (Great America Meeting Rooms, SCCC 2nd Floor)
Track:
Business Strategies & Memory Markets
Organizer + Chairperson:
Jean Bozman, President, Cloud Architects Advisors
Jean S. Bozman is President of Cloud Architects Advisors, a market research and consulting firm focused on hardware and software for enterprise and hybrid multi-cloud computing. She analyzes the markets for servers, storage, and software related to datacenters and cloud infrastructure. A highly-respected IT professional, she has spent many years covering the worldwide markets for operating environments, servers, and server workloads. She was a Research VP at IDC, where she focused on the worldwide markets for servers and server operating systems. She is a frequent conference participant as a speaker, chairperson, and organizer at such events as Flash Memory Summit, OpenStack, and Container World. She is often quoted in a variety of publications including BusinessWeek, Investor’s Business Daily, the Los Angeles Times, CNET, Bloomberg, and Reuters. Ms. Bozman has also been VP/Principal Analyst at Hurwitz and Associates and Sr Product Marketing Manager at Sandisk. She earned a master’s degree from Stanford.
Presenters:
Presentation Session Description:
Gary Smerdon, CEO and Founder, MEXT
Presentation Title:
Meet AI-Powered Predictive Memory: DRAM Performance at Flash Cost
Presentation Abstract:
Data-intensive, memory-hungry applications like AI and large-scale databases are putting more and more pressure on data center compute resources—driving up the cost of computing. Discover how MEXT AI-powered predictive memory technology makes Flash storage appear as DRAM-speed memory to the OS, empowering customers to achieve DRAM-class performance while taking advantage of the cost-efficiency, scalability, and ubiquity of Flash.
Author Bio:
Gary Smerdon is the CEO and founder of MEXT. Before MEXT, Gary served as CEO at TidalScale and held numerous leadership positions including at Fusion-io, LSI, and AMD. He is a recognized innovator having led key efforts around industry transitions in networking, storage, and computing.
JM Hands, CEO, FarmGPU
Presentation Title:
Storage Requirements for AI NeoClouds
Presentation Abstract:
AI NeoClouds live on three distinct storage tiers: lightning‑fast checkpoints for multi‑petabyte training, ultra‑low‑latency KV‑cache and vector‑DB layers for inference (including RAG pipelines), and the next generation of composable flash‑class memories that must deliver RAM‑like bandwidth and SSD‑class economics at rack scale. In a ten-minute presentation, this talk converts cutting‑edge benchmarks into concrete bandwidth, endurance, and TCO targets for each tier — giving architects a concise playbook for sizing storage that keeps 2025‑era AI clouds fed, efficient, and future‑proof.
Author Bio:
Jonmichael Hands is CEO of FarmGPU, a data center provider of sustainable GPU hosting and AI infrastructure, catering to the increasing global demand for cost-effective, high-performance compute and storage resources.
Dharmin Parikh, Head of Product, Uber AI and Data, Uber
Presentation Title:
Accelerating and Scaling AI/ML at Uber
Presentation Abstract:
In this short talk, Dharmin will share Uber's journey from machine learning (ML) to deep learning to generative AI (GenAI). He'll talk about how Uber's AI platform powers all critical AI/ML applications for Uber, and he will share his insights into how compute, memory and storage bottlenecks have evolved over time for such applications
Author Bio:
Dharmin Parikh leads Product Management for Uber AI & Data. In this capacity, he oversees Uber's AI Platform Michelangelo and in several Applied AI areas, including Computer Vision, Personalization and Generative AI. Over the past decade, Dharmin has led various AI/ML/Data product teams spanning Uber, Panasonic and the IOT startup Arimo. Prior to that, Dharmin was a system architect at Intel Corp., where he architected network processors. He holds an MBA degree from UC Berkeley's Haas School of Business, and an MSEE degree from the University of Southern California (USC).
Eric Herzog, CMO, Infinidat
Presentation Title:
Storage can help Reduce CAPEX and OPEX in your Data Center
Presentation Abstract:
Learn how to win over the CFO with strong financial value saving millions in CAPEX and OPEX. Make IT happier with powerful technical benefits and guarantees. With storage management boosted efficiency by over 50% and payback on investment in less than a year, it will be hard for your executives not to pay you BIG. So, who's the vendor that delivers the value, performance, and certainty you deserve, but aren’t getting from your current enterprise storage vendor? Infinidat is your answer.
Author Bio:
Eric Herzog is the Chief Marketing Officer at Infinidat. Prior to joining Infinidat, Herzog was CMO and VP of Global Storage Channels at IBM Storage Solutions. His executive leadership experience also includes: CMO and Senior VP of Alliances for all-flash storage provider Violin Memory, and Senior Vice President of Product Management and Product Marketing for EMC’s Enterprise & Mid-range Systems Division.
This session with presentations followed by a panel discussion, delves into the transformative impact of innovative storage solutions on both financial and technical dimensions within enterprise environments. Across the presentations, a common thread emerges: the imperative of optimizing storage to meet the escalating demands of modern data-intensive applications, such as AI and large-scale databases. Highlighting the ability to dramatically enhance storage efficiency, reduce CAPEX and OPEX, and deliver rapid ROI, the session underscores the importance of selecting vendors that align with organizational needs for value, performance, and certainty. Complementing this, we discuss how AI-powered predictive memory technology is showcased as a breakthrough in achieving DRAM-class performance using Flash storage, offering significant cost-efficiency and scalability. Additionally, the session addresses the architecture of AI NeoClouds, emphasizing the necessity for a multi-tiered storage approach that balances bandwidth, endurance, and total cost of ownership (TCO) to future-proof AI applications. Collectively, these insights provide a comprehensive framework for architects and executives alike to enhance storage strategies, ensuring their infrastructure is both economically viable and technically robust.
PRO
CHIP-202-1:
Innovative Architectures and Emerging Opportunities: UCIe Integration and Chiplet Advancements in Mobile and AI Systems
Ballroom C (Santa Clara Convention Center, First Floor)
Track:
Chiplets and UCIe
Chairperson:
Charles Sobey, Chief Scientist, ChannelScience
Chuck Sobey is the General Chair of Chiplet Summit. He leads the Organizing Committees and identifies key trends, sessions, and speakers. Chuck is also Chief Scientist of ChannelScience, where he secured ~$3M in seed funding to develop a multi-format magnetic tape reader to access rare and deteriorating data sets. These data sets will be used for domain-specific training of AI/ML models, such as for monitoring data for nuclear nonproliferation efforts globally. Chuck earned an MS in electrical and computer engineering from University of California, Santa Barbara (UCSB), a BS from Carnegie Mellon University, and holds 8+ US patents.
Presenters:
Presentation Session Description:
Minsoon Hwang, TL, SK hynix
Presentation Title:
New Era of Memory Scalability: MOSAIC Chiplet Architecture for High-Capacity CXL
Presentation Abstract:
High-capacity CXL memory systems will be essential to meet the needs of emerging generative AI applications. However, building the required controller as a single large chip would be prohibitively expensive due to the high performance requirements. A new architecture called MOSAIC allows controllers in which only key chiplets are implemented in the smallest process node, while other parts remain at larger, cheaper nodes. A modified version of UCIe, called M.Link (MOSAIC Link), is also necessary to provide a variety of connections without excessive power dissipation or large area requirements. MOSAIC and M.link together can provide advanced CXL memory system controllers at a reasonable cost.
Author Bio:
Minsoon Hwang is a Director at SK hynix, where he works on design and analysis of mixed signal circuits and memory architecure. He previously worked at LG Electronics on CDMA basestations and flat panel displays. He has written technical articles and holds several patents. He earned a PhD in electrical and computer engineering from the University of Florida.
Soojin Kim, Senior Engineer, SK hynix
Presentation Title:
Start New Game: HBS (High Bandwidth Storage/Solution)
Presentation Abstract:
The requirement for mobile system is predicted to greatly increase and even exceed the specifications of current system due to the emergence of the applications for on-device AI. Therefore, we propose HBS (High Bandwidth Storage/Solution), the next-generation storage archiecture, to solve the limitation of storage bandwith and power optimation issues that will be pain points for future flagship mobiles. In order to increase the storage bandwidth and optimize energy efficiency, we propose LPW (Low Power Wide-IO)-NAND and to use D2D (Die-to-Die) interface between the LPW-NAND and its controller. Furthermore, we also propose to use the technology of VFO (Vertical Fan-Out) package for wide-IO connections. One of the candidate utilizations for the proposed HBS is smartphone in which AP (Application Processor) and our HBS are interconnected with D2D interface and integrated into the same package. In addition to the mobile utilizations, we expect that HBS can also be utilized in CXL-hybrid, automotive and robotics, and GPU solutions.
Author Bio:
From 2010 to 2013, she was a Researcher at the SoC Platform Research Center at Korea Electronics Technolgy Institute, Korea. After receiving her Ph.D degree from Department of Electronics Engineering in Korea in 2014, she has been a Senior Engineer at the Solution Development Division of SK hyinx, Korea. Her current reserch activities include the SoC architecture and design, and storage solutions for high-performance and low-power.
Brian Rea, UCIe Marketing Work Group Chair, UCIe Consortium
Presentation Title:
Forging an Open Chiplet Ecosystem Leveraging UCIe Technology
Presentation Abstract:
Chiplets provide design flexibility for end-users seeking to match chip designs based on established requirements. By combining best-in-class, die-to-die interconnect and protocol connections from an interoperable, multi-vendor ecosystem, UCIe™ — Universal Chiplet Interconnect Express™ — addresses customer requests for more customizable, package-level integration solutions.
Technology industry consultant firm McKinsey forecasts that semiconductors will become a trillion-dollar industry by the end of this decade. Anticipating this massive growth, manufacturers are taking into account the need to balance costs with chip performance and working to answer this challenge by shifting toward chiplet manufacturing; creating smaller, modular chiplets, designed for a specific function, that can be connected to construct a larger system.
UCIe Consortium representatives will discuss the necessity for collaboration in the industry toward the future of chiplet innovation in markets such as AI, ML, aerospace, and automotive. Our panelists will also share best practice strategies for chiplet design utilizing UCIe technology.
Author Bio:
Brian Rea is a senior technologist in the industry initiative and technology enabling team at Intel and is the Marketing Working Group Co-Chair for the UCIe Consortium. Brian has held engineering, marketing, and strategic planning roles bringing products with new technologies to market including USB, Gigabit Ethernet, PCIe, and CXL. His passion is working with customers and partners to enable ecosystem innovations in silicon, hardware, and software. Brian holds an MBA from the University of Washington and a BSEE from the University of Texas at Austin.
Randy White, Memory Solutions Program Manager, Keysight Technologies
Randy White is the Memory Solutions Program Manager for Keysight Technologies. He is focused on test methodologies for emerging memory technologies in server, mobile and embedded applications. Randy has spent the last 20 years investigating signal integrity measurement techniques including de-embedding algorithms, measurement/model correlation and high speed measurements for real-time & sampling oscilloscopes as well as BERTs & AWGs. He has participated on many standards committees including UCIe, PCI-SIG, USB-IF, SATA-IO, and JEDEC to help define new test methodologies and is currently the chair of the JEDEC JC40.5 Logic Validation subcommittee. He graduated with a BSEE from Oregon State University.
This session features presentations followed by a panel discussion, and dives into the transformative potential of modular design in semiconductor technology, highlighting the pivotal role of interconnect innovations such as UCIe™ and MOSAIC in addressing the growing demands of diverse markets including AI, mobile, and automotive sectors. Presentations will explore the strategic shift towards chiplet architecture, enabling customizable and cost-efficient solutions through die-to-die interconnects and multi-vendor ecosystems. Discussions will center on the implementation of high-bandwidth storage solutions and power optimization techniques, crucial for the next generation of mobile and AI applications. Additionally, the session will examine the development of advanced memory systems using MOSAIC and M.Link technologies, designed to offer high performance without prohibitive costs. By embracing these advancements, industry leaders aim to propel the semiconductor industry toward its forecasted trillion-dollar status, fostering innovation through collaboration and best practice strategies.
PRO
DCTR-202-1:
Data Center Consumer Panel: Storage Needs for the AI Era
Ballroom F (Santa Clara Convention Center, First Floor)
Track:
Data Center Storage and Memory
Chairperson:
Jeremy Werner, SVP & GM, Core Data Center Business Unit, Micron Technology
Jeremy is an accomplished storage technology leader with over 20 years of experience. At Micron he has a wide range of responsibilities, including product planning, marketing and customer support for Server, Storage, Hyperscale, and Client markets globally. Previously he was GM of the SSD business at KIOXIA America and spent a decade in sales and marketing roles at startup companies MetaRAM, Tidal Systems, and SandForce. Jeremy earned a B.S.E.E. from Cornell University, is a Stanford Graduate Business School alumni, and holds over 25 patents or patents pending
Jeremy is an accomplished storage technology leader with over 20 years of experience. At Micron he has a wide range of responsibilities, including product planning, marketing and customer support for Server, Storage, Hyperscale, and Client markets globally. Previously he was GM of the SSD business at KIOXIA America and spent a decade in sales and marketing roles at startup companies MetaRAM, Tidal Systems, and SandForce. Jeremy earned a B.S.E.E. from Cornell University, is a Stanford Graduate Business School alumni, and holds over 25 patents or patents pending
Organizer:
Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft
Jonathan Hinkle is Senior Director - Azure Memory and Storage Pathfinding at Microsoft. He previously was In Micron's Storage Business Unit, where he investigated new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.
Panel Members:
Panel Session Description:
Chris Newburn, Distinguished Engineer, NVIDIA
Dr. Chris J. Newburn, who goes by CJ, is a Distinguished Engineer who drives industry-wide initiatives like Storage-Next, HPC strategy and the SW IO product roadmap in NVIDIA Compute Software, with a special focus on data center architecture and security, storage and network IO, systems, and programming models for scale. He is a community builder with a passion for extending the core capabilities of hardware and software platforms from HPC into AI, data science, and visualization. He's delighted to have worked on volume products that his Mom used and that help researchers do their life's work in science that previously wasn't possible.
Karthik Ganesan, Fellow, Micron
Karthik Ganesan is a seasoned technologist and thought leader in storage systems and computer architecture. With a strong foundation in performance optimization and systems design, Karthik has contributed extensively to advancing enterprise and data center storage technologies. As a Technical Fellow at Micron, he drives storage solutions architecture for the Core Data Center Business Unit, focusing on next-generation storage innovations that power AI, cloud, and enterprise workloads.
His earlier tenure at Solidigm and Intel included leadership roles in SSD architecture, firmware, and system engineering, where he was instrumental in the development and global success of groundbreaking SSD products, including the industry’s first hybrid Optane/NAND SSD and a revolutionary QLC SSD family.
Karthik holds advanced degrees in electrical and computer engineering as well as an MBA from Golden Gate University.
Rajesh Rajaraman, VP and CTO, AI Data Platforms & Data Protection, Dell Storage
Rajesh Rajaraman is responsible for technology strategy, architecture, and innovation across the portfolio. Proven technology leader with over 25 years of experience in storage and distributed systems. He possesses tremendous breadth and technical depth in storage, data protection, public cloud technologies and has authored many patents. He also holds an engineering degree in electronics and communication. Prior to joining Dell, he held positions at NetApp, Cohesity and DEC.
Shimon Ben-David, CTO, WEKA
Shimon Ben-David, WEKA's CTO, engages with customers and partners to gather feedback and insights for the Engineering and Product Management teams, leveraging his extensive enterprise IT experience from leadership roles at companies like Primary Data, XtremIO, IBM, and XIV Storage. He previously led customer success and sales engineering at WEKA and studied Computer Science and Philosophy.
Artificial intelligence is changing the world of storage at the speed of light. With a growing focus on higher capacities, performance, QoS, form factors, and lower power, it can be challenging to translate those needs into specific use cases, system architectures, or even specific product selections. Join us for an enlightening panel discussion moderated by Jeremy Werner, SVP and GM of Micron's Core Data Center Business Unit. He will lead industry luminaries from various technology domains in exploring the future of storage in an AI-driven world. Come and learn from these technology leaders what it takes for your storage solutions to thrive in that world!
PRO
DESN-202-1:
Design Automation
Ballroom G (Santa Clara Convention Center, First Floor)
Track:
Design Automation
Chairperson + Organizer:
Andrew Tomlin, CEO, QiStor
Andy Tomlin is Founder, CEO and Principal Architect at QiStor, a startup developing a hardware-accelerated, flash-based, Key-Value-as-a-Service solution for data centers. He is a 30-year industry veteran with extensive experience in flash management and controller architecture, and has delivered many flash-based products to both the client and enterprise spaces. Andy has led multiple leading-edge controller and firmware development projects while holding executive and VP Engineering positions at multiple flash and controller vendors including Sandisk, SandForce, WD, Samsung, and KIOXIA. He has presented on these topics numerous times over the years at Flash Memory Summit, and he holds over 60 patents in these areas. Also the principal developer behind the open source arch2code tool.
Presenters:
Presentation Session Description:
Luis E Rodriguez, Verification IP Architect, Siemens Digital Industries Software
Presentation Title:
Software Aware Verification IP for CXL, NVMe, UCIe
Presentation Abstract:
A major challenge for SoC engineering teams is the proliferation of firmware features. For NVMe controllers, CXL endpoints and UCIe, certain protocol features are split between hardware and firmware. Functional Verification Engineers and Firmware Engineers typically work in separate environments, with firmware tested in FPGA prototypes before first silicon. Debugging FPGA firmware issues related to hardware is difficult and time-consuming.
This presentation details a Software-Aware Verification IP platform enabling collaboration among firmware, software, and hardware teams for simulation based system-level validation. Leveraging open-source tools like QEMU and ARM Fast Models, and integrating System-C, we bridge simulation-based SystemVerilog BFMs, allowing a seamless transition from UVM to a full virtual platform. This platform aids in compliance testing for standards like CXL, NVMe, PCIe, and UCIe. It also provides a familiar interface for engineers to collaborate, effectively shifting left firmware and software validation. We will present video demos of NVMe and CXL conformance testing and discuss the benefits reported by teams that have adopted this new methodology.
Author Bio:
Luis E. Rodriguez is a Technical Product Manager and Site Manager for Siemens DISW Costa Rica. He currently works on architecture and development of UCIe verification IP and also leads an AI/ML cross functional team. He has participated in standards bodies such as PCIe and CXL, where he led compliance test specification. He earned an MS in computer science from the National Taiwan University.
TziYang Shao is a product lead for Siemens’ Virtual In-Circuit Simulation product line. He led the development and deployment of the digital twin using virtual platforms such as QEMU/ARM Fast models combined with System Verilog simulation. He previously worked on BIOS/Linux Kernel problems and user applications targeting protocol verification or early driver development for interfaces such as UCIe, CXL, and PCIe. He earned a BSEE from the Hong Kong University of Science and Technology.
Andrew Tomlin, CEO, QiStor
Presentation Title:
Improving Silicon TTM with Improved Development Automation
Presentation Abstract:
Presenting arch2code an open source toolchain and methodology to improve architecture, design and debug of complex hardware designs. This methodology allows rapid development in SystemC and SystemVerilog and including cosimulation. Start FW and verification earlier in cycle and reduce documentation workload. Eliminate the communication overhead associated with multi-disipline development.
Going through some real world benefits experienced using the toolchain.
Author Bio:
Andy Tomlin is Founder, CEO and Principal Architect at QiStor, a startup developing a hardware-accelerated, flash-based, Key-Value-as-a-Service solution for data centers. He is a 30-year industry veteran with extensive experience in flash management and controller architecture, and has delivered many flash-based products to both the client and enterprise spaces. Andy has led multiple leading-edge controller and firmware development projects while holding executive and VP Engineering positions at multiple flash and controller vendors including Sandisk, SandForce, WD, Samsung, and KIOXIA. He has presented on these topics numerous times over the years at Flash Memory Summit, and he holds over 60 patents in these areas. Also the principal developer behind the open source arch2code tool.
This session delves into innovative methodologies and platforms designed to enhance semiconductor manufacturing and system-level validation. A common theme across the presentations is leveraging advanced computational technologies to optimize processes and foster interdisciplinary collaboration. The first presentation introduces a TCAD-augmented Generative Adversarial Network, which drastically reduces computation time in 3D NAND fabrication, enabling precise etching predictions even with limited experimental data. The second presentation discusses a Software-Aware Verification IP platform for enhancing collaboration between firmware, software, and hardware teams. By using open-source tools and integrating System-C, it streamlines the validation process for protocols like CXL and NVMe. Lastly, the arch2code toolchain offers an open-source methodology for expediting hardware design and debugging, promoting early-stage firmware and verification activities while reducing documentation burdens. Collectively, these presentations underscore the importance of integrating cutting-edge technology and collaborative frameworks to improve efficiency and accuracy in semiconductor development.
Open
INDA-202-1:
How CXL Transforms Server Memory Infrastructure
Ballroom D (Santa Clara Convention Center, First Floor)
Track:
Industry Associations
Chairperson:
Anil Godbole, Sr. CXL Mktg Manager, Intel
Anil Godbole is a CXL Marketing Working Group Co-Chair and Senior Marketing Manager for Intel’s Xeon Product Planning and Marketing Group. His domain is in Memory, Serdes Technologies & Associate Protocols (DDRx, CXL, PCIe, Ethernet, etc.). Previously, he held a position as Design Engineer in CPU-support ASICs, FPGAs.
Panel Members:
Panel Session Description:
Jianping Jiang, SVP, Business, Xconn Technologies
Jianping(JP) Jiang is the Senior VP of Product Marketing and Business Operation at Xconn Technologies, a silicon valley startup pioneering CXL switch IC. At Xconn, he is in charge of CXL ecosystem partner relationship, CXL product marketing, business development, corporate strategy and operations. Before joining Xconn, JP held various
leadership positions at several large scale semiconductor companies, focusing on product planning/roadmaps, product marketing and business
development. In these roles, he developed competitive and differentiated product strategies, leading to successful product lines that generate over billions of dollars revenue annually. JP has a Ph.D degree in computer science from the Ohio State University.
Sandeep Dattaprasad, Director, Product Management, Astera Labs
Sandeep Dattaprasad is a Director of Product Management and Technologist with Astera Labs. He has 15+ years of experience in semiconductor, software diagnostic tools, developing security strategies and firmware development for complex SoC product lines including Compute Express Link products, SAS RAID controllers, SAS expanders and PCIe switches. He is also a contributing member of the CXL Consortium. At Astera Labs, Sandeep’s focus is on driving product strategy for new market segments by translating data center bottlenecks into profitable and competitive hardware and software solutions using CXL technology.
Geof Findley, Vice President of Business and Sales, Montage Technology
Geof Findley has held the role of Vice President of Business Development and Sales at Montage Technology, Inc. since March 2018. Previously, he spent 17 years at Intel Corporation in positions including Director of Memory Enabling in the Data Center Group, focusing on aligning products with JEDEC standards, and Channel Alliance Manager, emphasizing market timing and partnership optimization. His earlier experience includes roles in business development and strategic program management at Intel Corporation and 11 years as a Senior Sales Representative at Royal Trading – Unify. Geof holds a B.S. in System Engineering from the University of Arizona and a MBA from St. Edward’s University.
Siamak Tavallaei, Sr. Principal Engineer, Samsung
Siamak Tavallaei is Sr. Principal Engineer at Samsung, Systems Architecture. He joined the CXL effort as a founding member of the CXL Consortium and co-chair of the Technical Task Force (TTF) in 2019 to develop the CXL 2.0 specification. He has served on the CXL Board of Directors and as the CXL President. In 2016, he joined Open Compute Project (OCP) as a co-lead of Server Project. He later served as the Incubation Committee Representative for the Server Project and Steering Committee where he drives open-sourced modular design concepts for integrated hardware/software solutions for massively-scaled systems. Previously, he has served as Distinguished Technologist at HP, Senior Principal Architect at Microsoft Azure, and Chief Systems Architect at Google.
CXL technology allows both coherent shared and dedicated pooled memory to serve different purposes – enabling a composable data center architecture and providing a cost-efficient solution to expand memory, while improving overall performance for memory-intensive applications like In-Memory Database, HPC, and AI/ML.
In this session, attendees will explore the benefits of CXL memory pooling and sharing and gain valuable insights into how the technology is being deployed to accelerate performance in AI workloads, In-Memory Databases, and Big Data Analytics.
PRO
OMEM-202-1:
Emerging Memory Technologies
Ballroom E (Santa Clara Convention Center, First Floor)
Track:
Other Memory Technologies
Chairperson:
Feng Zhou, Senior Member of Technical Staff, Microchip Technology
Feng Zhou is a senior member of the technical staff at Microchip Technology.
Organizer:
Dave Eggleston, Sr Business Development Manager, Microchip Technology
Dave Eggleston is Sr. Business Development Manager at Microchip. Dave's extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at Sandisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.
Presenters:
Presentation Session Description:
Mark Webb, Consultant/Analyst, MKW Ventures Consulting LLC
Presentation Title:
Future Scenarios for Emerging Memory Markets
Presentation Abstract:
We update market and bit costs for the technologies that have already emerged like MRAM, ReRAM, PCM, FeRAM. We show timelines for technologies that will emerge into revenue products in five plus years and where they are in the memory product development lifecycle. We show revenue and bit growth for discrete chips and the current limiters to growth. We show bit shipment penetration into chiplets applications and into embedded markets with scenarios for how those could grow at a faster pace. We also show the pros and cons of using these technologies in AI applications in similar ways to HBM memory and a possible scenario for future memory systems combining multiple memory types
Author Bio:
Mark Webb is principal analyst and advisor at MKW Ventures Consulting LLC. His focus areas are memory technology and semiconductor foundry processes and costs. Mark is a recognized expert in NAND, DRAM, and Emerging Memory technologies and costs. Mark was previously Manufacturing Director in the NVM Solutions Group at Intel Corporation. Prior to that, Mark was Product Quality and Reliability Manager at IM Flash Technologies from 2006-2008. From 1989 to 2006, Mark held a variety of positions at Intel Corporation in Process Logic and Memory Integration and Product Engineering. Mark is a frequent presenter at Flash Memory Summit and other Memory and Storage conferences. Mark has a BS degree in electrical and computer engineering
Steve Chung, Chair Professor, National Yang Ming Chiao Tung University
Presentation Title:
Perspectives on 3D AND-type Resistive-Gate RAM Development with QLC Capability
Presentation Abstract:
The floating-gate stopped at 28nm for embedded memory, a scalable flash memory becomes crucial. RRAM is one of the promising solution owing to its simple structure, low cost, and CMOS compatible process. Although there are thousands of RRAM papers, conventional 1T1R structure, MIM connected to the FET’s drain, was commonly used. It has a small window (~10x-100x) with limitation on multi-level operation and requires high current to drive arrays. Cross-bar arrays, although has high density while is troubled by the sneak path. We proposed a unique structure to deal with the above drawbacks.
Here, we demonstrated a gate-type 1TnR in a 3D AND-type Macros, by using one transistor at the bottom and grow nR (with backend process) on the top of its gate. A quad-level cell (QLC) of a resistive-gate RAM (RG-RAM) will be demonstrated. Its performance includes forming-free of stacked MIM, low programming current (<uA), wide range window (~10^5x), no sneak path, disturb-free, high endurance and excellent data retention.
This design can be easily extended to FinFET and nanosheet generations down to 1nm, either in stand-alone or embedded applications, a promising solution to compete with FG.
Author Bio:
Steve Chung received his Ph. D. from University of Illinois at Urbana-Champaign, under the supervision of world renowned CMOS co-Inventor C. T. Sah. He is the Chair professor of NYCU (former NCTU) with past administrative position in managing International Office and Executive Director of the school's TOP-University plan funded by the government. He was a visiting prof. to both Stanford and UC-Merced, CA, in 2021 and 2008 respectively. He was also a consultant to the two world giants in foundry- tsmc and UMC. His current research interests include- nanoscale CMOS, flash memory, resistance Memory Technologies, from storage to AI applications. He has 35+ times presentations at IEDM/VLSI, more than 300+ publications and also holds more than 50 patents. He is an IEEE Life Fellow, US NAI Fellow, current IEEE Distinguished Lecturer, Senior Editor of Applied Physics-A (Springer), Executive Committee member of VLSI, and with past involvements as IEEE EDS Board of Governor for more than 12 years, EDS Regions/Chapters Chair, and Editor of IEEE J-EDS, EDL), etc. Among numerous awards, he received Lifetime achievement award as National Inventors (2019) etc.
Amir Regev, VP Quality and Reliability, Weebit Nano
Presentation Title:
ReRAM: Emerging as the New Embedded NVM Standard
Presentation Abstract:
At 28nm and below, embedded flash is not a viable option for non-volatile memory (NVM) integration in SoCs. Even for designs at more mature geometries, embedded flash no longer delivers the most competitive solution in terms of power, performance and cost. Today ReRAM is the embedded NVM of choice for a growing range of applications including automotive, edge AI, MCUs, PMICs and others. ReRAM is low-power, low-cost, byte-addressable, scales to advanced nodes, and is highly resilient to a range of environmental conditions including extreme temperatures, ionizing radiation and electromagnetic fields.
In this session, Weebit will discuss the current state of ReRAM adoption in embedded applications, and performance results that are making it the technology of choice for more and more designs. We will focus in particular on unique requirements in edge AI where embedded NVM is needed in advanced processes, and automotive where the mission profiles are tough to meet from the perspectives of temperatures, harsh environments and longevity. We will also touch on the future of ReRAM, including its roadmap as analog in-memory compute engine.
Author Bio:
Amir Regev is VP of Quality and Reliability at Weebit Nano. He has two and a half decades of experience in semiconductor devices and technology, with particular expertise in flash memory technology. He previously held senior R&D and engineering roles at companies including Intel, Sandisk, Micron and Marvell. Amir holds a M.Sc. in Electrical Engineering from Tel-Aviv University and a B.Sc. in Material Science and Engineering from Ben-Gurion University.
Jung Yoon, Distinguished Engineer & CTO, IBM Supply Chain
Presentation Title:
Quantum Computing - Memory & Storage directions & requirements’
Presentation Abstract:
This talk will provide key technical insights into the future of memory and storage in quantum computers. This will include quantum memory technologies (solid state & atomic) that stores and manipulates quantum bits, Hybrid Quantum-classical systems focused on enabling efficient data processing and storage, Quantum Error Correction, materials science advancements, and quantum memory density that will enable large scale quantum computing systems and capabilities.
We will also discuss the intersection of flash storage and quantum computing – where advancement in 3D-NAND technology is expected to play a key role with improved data density, speed, latency and reliability. As quantum computing has implications in data security and cryptography, we will also focus on future memory and storage security key directions aligned with quantum safe security needs.
Author Bio:
Jung Yoon is a Distinguished Engineer & CTO of IBM Supply Chain. He is a recognized industry leading expert in DRAM, 3D-NAND, SSDs, and semiconductor devices, and drives technology convergence between industry capabilities and IBM’s strategic product offerings. Jung has over 30 years of experience in the field of Semiconductor R&D, technology enablement and quality. Jung earned his PhD in Solid State Physics from Columbia University, MS from University of California Berkeley, and a BS from Seoul National University.
Nilesh Shah, VP Business Development, ZeroPoint Technologies
Presentation Title:
Compression enabled MRAM memory chiplet subsystems for LLM Inference
Presentation Abstract:
LLM inference is increasingly memory-bound, demanding a 6:1 read-to-write ratio, while HBM-based GPUs, designed for balanced memory access, suffer from <60% utilization. Existing compression techniques like quantization and pruning reduce memory overhead but compromise accuracy. MRAM-based memory chiplets provide HBM-equivalent bandwidth at 30-50% lower power, optimizing read-heavy AI workloads and offering a viable alternative to GPUs. This talk will explore AI-specific chiplet solutions that challenge GPU dominance by enabling custom AI inference SoCs with energy-efficient, high-throughput architectures. We’ll discuss future innovations, including KV cache compression, hybrid lossy-lossless algorithms, MRAM-based memory controllers, and cloud-scale MRAM integration. Join us to explore how next-gen memory architectures will redefine AI inference efficiency.
Author Bio:
Nilesh Shah is VP Business Development, ZeroPoint Technologies. Additionally. He participates and contributes regularly at standards bodies like SNIA, OCP, JEDEC, RISC-V, CXL Consortium. He is regularly invited to speak at conferences, and has led multiple panels and is featured in Analyst/ Press interviews, focused on AI and memory technologies. Previously, Nilesh led Strategic Planning at Intel Corporation's Non Volatile Memory Solutions Group, where he was responsible for the product planning and launch of the Data Center SSD products and Pathfinding innovations. Nilesh advises GPU and memory Chiplet startups.
This session delves into the evolving landscape of memory technologies, highlighting their transformative potential across various applications. Emerging alternatives to Flash such as ReRAM and MRAM are gaining traction, offering superior performance in terms of power efficiency, scalability, and resilience, particularly in demanding environments like automotive and edge AI. The session also explores innovative structural designs, such as gate-type RRAM, and their implications for future computing architectures. Additionally, the intersection of memory technologies with quantum computing and AI is examined, illustrating how advancements in 3D-NAND and MRAM are poised to enhance data processing capabilities in quantum systems and optimize AI inference workloads. Overall, the discussions underscore the pivotal role of next-generation memory architectures in addressing the growing demands of modern computing, from AI to quantum applications.
11:00 AM to 11:30 AM
Open
KEYN:
Keynote 7: NEO Semiconductor: Breaking the Bottleneck: Disruptive 3D Memory Architecture for AI
Mission City Ballroom (Santa Clara Convention Center, First Floor)
Track:
Keynotes
Keynote Speakers:
Keynote Description:
Andy Hsu, Founder and CEO , NEO Semiconductor
Andy Hsu is the Founder and CEO of NEO Semiconductor. He has over 3 decades of experience in the semiconductor industry including positions as VP of Engineering and leader of R&D and Engineering Teams. This resulted in the development of more than 60 products in various non-volatile memories, DRAM, and AI chips. Andy is an accomplished technology visionary and inventor of 125 granted U.S. patents. He performed research in the fields of Neural Networks and Artificial Intelligence (AI) while earning a master’s degree in Electrical, Computer, and System Engineering (ECSE) from Rensselaer Polytechnic Institute (RPI) in New York. He earned a bachelor’s degree from the National Cheng-Kung University in Taiwan.
As AI systems scale, the widening gap between processor and memory performance has become a critical limitation. NEO Semiconductor introduces a breakthrough in 3D memory architecture that eliminates the need for through-silicon via (TSV) processes—dramatically increasing memory bandwidth by up to 10x, while reducing die cost, height, and power consumption by as much as 90%.
In this keynote, NEO will explore how rethinking memory from the ground up can unlock new levels of performance and efficiency in AI. Attendees will also get an exclusive preview of a soon-to-be-announced innovation that promises to redefine the future of memory technology.
11:30 AM to 11:40 AM
Open
SPEC-201-1:
SuperWomen of FMS Leadership Award
Mission City Ballroom (Santa Clara Convention Center, First Floor)
Track:
Special Sessions
Speakers:
Special Presentation Description:
Betsy Doughty, Vice President of Partner Marketing , Hammerspace
Betsy Doughty is Vice President of Partner Marketing at Hammerspace. She previously was Vice President of Corporate Marketing at Spectra Logic.
Tracy Chan, Director, Hyperscale, Pure Storage
Tracy Chan is Director, Hyperscale, at Pure Storage.
The SuperWomen of FMS Leadership Award recognizes women who have shown outstanding leadership in the growth, development and use of flash memory and associated technologies and systems. Join us as we honor the 2025 recipient, Rita Gupta of AMD.
11:40 AM to 12:10 PM
Open
KEYN:
Keynote 8: Sandisk: The Diversification of Flash Storage - Unlocking the Full Potential of NAND in the AI Era
Mission City Ballroom (Santa Clara Convention Center, First Floor)
Track:
Keynotes
Keynote Speakers:
Keynote Description:
Alper Ilkbahar , Executive Vice President, Chief Technology Officer , Sandisk
Alper Ilkbahar is Executive Vice President of Memory Technology at Sandisk, overseeing NAND technology development, next-generation technologies, corporate research functions, and market development. Most recently, Alper served as Senior Vice President of Global Strategy and Technology at Western Digital. Prior to Western Digital, he was the Vice President of the Data Center Group and General Manager of the Intel Optane Group. In this role, he supported the development of memory and storage solutions by integrating innovative hardware and software for next-generation data centers around Optane Technology.
Alper served as Vice President and General Manager of several business units at Sandisk. He started his career in Intel’s microprocessor division, where he worked in design engineering and management. A leader who has honed his technical expertise, Alper holds more than 50 patents in the fields of semiconductor process, device, design, and testing.
Alper received a bachelor’s in electrical engineering from Boğaziçi University in Istanbul, Turkey, a Master’s in Electrical Engineering from the University of Michigan, and a Master of Business Administration from the Wharton School of the University of Pennsylvania.
Jim Elliott, Executive Vice President and Chief Revenue Officer, Sandisk
Jim Elliott is Executive Vice President and Chief Revenue Officer at Sandisk. In this role, Jim leads efforts to maximize revenue opportunities and drive Sandisk’s growth. A highly respected industry leader with nearly 30 years of experience in the semiconductor memory and storage sector, Jim has held leadership roles in both global corporations and Silicon Valley start-ups. Known as a market visionary, he has played a key role in driving memory and storage transitions and market evolution. He has proven expertise in developing synergistic product portfolios across a wide range of markets including Server, Data Center, PC, Tablet, Phone, Wearables, and Automotive. Prior to Sandisk, Jim served as Executive Vice President at Samsung Semiconductor, Inc., where he led all Sales and Marketing activities for Samsung’s memory organization in the Americas. There, he was responsible for the sales, marketing, operations, and QA teams for Samsung’s memory business, comprised of 3D NAND, SSDs, DRAM, LPDDR, Graphics, HBM and UFS products. Jim holds a Bachelor of Arts from the University of California at Davis, and a Master of Business Administration from Cal Poly University, San Luis Obispo
Mrinal Kochar, Senior Vice President of SSD Engineering, Sandisk
Mrinal Kochar is a visionary leader with over 21 years of experience in the SSD, Flash, and DRAM industry, driving innovation, product differentiation and industry standards. As Corporate Vice President at Sandisk, he leads the SSD engineering organization, spearheading next-generation Flash storage solutions that push the boundaries of speed, efficiency, and reliability. A prolific inventor with 20+ patents, Mrinal has played a pivotal role in advancing memory technology, shaping technology roadmaps, and aligning product strategies with business goals. With a track record of scaling engineering organizations and fostering a culture of collaboration and excellence, he continues to inspire teams and industry partnerships. A recognized thought leader, Mrinal has delivered keynotes at esteemed global conferences, shaping the future of SSD technology and driving sustained business growth in a multi-billion market. He firmly believes that technology is only as powerful as the people behind it and remains committed to mentoring and developing the next generation of engineers and leaders. Mrinal holds BS and MS degrees in Electrical Engineering from the University of Idaho.
We are witnessing a fundamental shift where flash moves from being a cost-optimized component to a specialized and diverse technology based on evolving workload and business requirements. The storage itself becomes more customizable to match more complex workloads. Sandisk believes that the unique dimensional capabilities of NAND present an unparalleled opportunity to drive innovation within the evolving AI landscape. Join us as we showcase NAND-based solutions that will strategically elevate its value to the ecosystem, delivering tangible benefits for the most challenging data-intensive workloads.
12:00 PM to 07:00 PM
Open
GEN :
FMS Exhibition
Exhibit Hall (Santa Clara Convention Center, First Floor)
Track:
General Events
General Event Description:
Attend the FMS Exhibit Hall, expanded again for 2025! Along with our sponsors and exhibitors from a broad scope of the memory and storage industries, the show floor has a variety of events, including a Pitch Theater, Industry Receptions, Winners' Circle - FMS Awards Ceremony, and the highly sought-after End-of-Show Raffle (you never know who will show up to entertain)! This year, there will be a dedicated lunch hour from 12:00 to 1:00 Tuesday through Thursday.
12:10 PM to 01:10 PM
Open
BRK:
Wednesday Lunch
Exhibit Hall D (Santa Clara Convention Center, First Floor)
Track:
General Events
General Event Description:
Wednesday's lunch in the Exhibit Hall is sponsored by JEDEC.
01:10 PM to 01:40 PM
Open
KEYN:
Keynote 9: MaxLinear: “Accelerated” Software-Defined Storage Transforming Data Storage at Enterprise Data Centers
Mission City Ballroom (Santa Clara Convention Center, First Floor)
Track:
Keynotes
Keynote Speakers:
Keynote Description:
Vikas Choudhary, VP & GM Connectivity and Storage, MaxLinear
Vikas Choudhary joined MaxLinear in 2024, responsible for the business strategy and product development for the company’s Connectivity & Storage business. In this role, he will be driving business and product strategies that enable next generation of ethernet (copper) and storage products in data centers, cloud networks, and enterprise storage. His 30+ year career in the semiconductor industry began as an analog/mixed-signal design engineer at ST Microelectronics. From there, he had continued success with companies such as Silicon Systems/Texas Instruments, PMC-Sierra/Microsemi and Analog Devices (ADI). Most recently, Vikas served as Vice President of Marketing, Sales, and Systems at Murata-pSemi, overseeing growth across consumer mobile, connectivity, wireless infrastructure, and high-performance multi-market components. Vikas received his MBA in Marketing & Strategy from Northwestern University, M.S. in Electrical Engineering (MSEE) from UCLA Technology, and BE from the Birla Institute of Technology (BITS) in Ranchi, India. Vikas is also the author of 5 patents, multiple publications, and editor of a book on fundamental technology on MEMS.
Stephen Bates, Fellow, AI Storage Architecture and Software, AMD
Stephen Bates is an AMD Fellow focusing on AI storage architectures and software in the AI Group. He is a renowned expert on topics like NVMe, RDMA, TCP/IP and NVM. He has worked on a range of complex storage and communication systems including NVMe controllers and PCIe switches. He enjoys working at the interface between hardware and software and is an active contributor to the Linux kernel and other open-source software projects. He has spent time as an academic as an Assistant Professor in Computer Engineering at The University of Alberta. He holds a PhD degree from The University of Edinburgh, Scotland and is a Senior Member of the IEEE.
The data storage market is experiencing enormous growth, driven largely by AI adoption. According to Fortune Business Insights, the global cloud storage market is projected to grow six folds from 100B$ to 600B$+ over next 5 years. This growth is creating significant challenges:
• Rising power consumption even beyond current 2% of global energy consumption
• Increasing storage costs as data volumes expand
• Performance bottlenecks with traditional storage solutions
• Security concerns with distributed data
This keynote will address these challenges suggesting novel methods using combination of high-performance CPU Cores (performance per watt) and storage acceleration SoC (System-on-a-Chip) drastically reduce the power consumption over traditional methods. Several architectural trade-offs involving off-load, in-line and a hybrid method along with accelerated data services like deep compression for hot and cold data, encrypted data and providing quantum resilience with an achievable scale-out at 1Tb per second will be discussed. These methods can improve effective storage by factors up-to 1:20.
01:40 PM to 02:10 PM
Open
KEYN:
Keynote 10: VergeIO: AI Infrastructure for Everyone: Flattening the Pipeline, Simplifying Deployment
Mission City Ballroom (Santa Clara Convention Center, First Floor)
Track:
Keynotes
Keynote Speakers:
Keynote Description:
Yan Ness, Chief Executive Officer, VergeIO
Yan Ness is an entrepreneur and infrastructure strategist with over 25 years of experience leading technology companies through transformation and scale. As CEO of VergeIO, he guides the company's vision to simplify IT infrastructure and empower organizations to operate sovereign and private clouds with greater efficiency. Yan earned a BS in Computer Science from University of Michigan.
Greg Campbell, Chief Technology Officer, VergeIO
Greg Campbell is the architect behind VergeOS and a veteran in scalable system design. With a background in distributed computing and a passion for eliminating infrastructure bottlenecks, he leads VergeIO’s engineering efforts to integrate advanced capabilities like AI into the core of the operating system. Greg earned a degree from University of Michigan - Dearborn.
Today, the complexity of artificial intelligence demands specialized skills, sophisticated tools, and robust infrastructure, rendering it both inaccessible and costly for many organizations. IT teams encounter significant learning curves and operational challenges when developing AI solutions on fragmented infrastructures. Current solutions fail to address the core issue: the ecosystem’s overwhelming complexity. Innovations in AI infrastructure must flatten the AI pipeline and reduce integration burdens. This talk will examine how streamlining the AI ecosystem facilitates the privatization of AI for organizations and sovereign entities, enabling the creation of secure, self-managed AI environments. These advancements will promote broader AI adoption, leading to faster returns on GPU investments and justifying the use of high-capacity SSD technology within AI processes. During the keynote, VergeIO will showcase a live demonstration of VergeIQ, and provide a peek at what integrated, sovereign AI looks like in practice.
02:10 PM to 02:40 PM
Open
KEYN:
Keynote 11: KOVE: Rethinking the Box: Why Memory Constraints Are Now a Design Choice
Mission City Ballroom (Santa Clara Convention Center, First Floor)
Track:
Keynotes
Keynote Speakers:
Keynote Description:
Dr. John Overton, CEO, KOVE
Dr. John Overton is the CEO and founder of Kove IO, Inc., responsible for introducing the world's first software-defined memory offering, Kove: SDM™. Once considered impossible, Kove: SDM™ delivers infinitely scalable memory, and unleashes new artificial intelligence and machine learning capabilities while also reducing power consumption by up to 54%. In the late 1990s and early 2000s, Dr. Overton co-invented and patented pioneering technology using distributed hash tables for locality management. This breakthrough technology created unlimited scaling, and enabled the advent of cloud storage, scale-out database sharding, among other markets. While at the Open Software Foundation in the late 1980s, Dr. Overton wrote software used by approximately two-thirds of the world's workstation market. Dr. Overton has more than 65 issued patents world-wide, has peer-reviewed publications across a number of academic disciplines, and holds post-graduate and doctoral degrees from Harvard and the University of Chicago.
For decades, compute and storage evolved — but memory stayed in the box. We accepted its limits as fact. In this keynote, Kove CEO John Overton challenges that assumption and shows how software-defined memory (SDM) redefines what’s possible. With Kove: SDM™, memory is no longer constrained by local hardware — it becomes a virtualized, high-performance resource, dynamically allocated where and when it’s needed most. Enterprises are now running memory-bound jobs at up to 60x speed, achieving 100x container density, and reducing power and cooling costs by up to 54%. From AI/ML model training to risk modeling and real-time analytics, Kove: SDM™ unlocks new agility—without code changes or hardware overhauls. Join us to explore how Kove engineered around the limits of physics to rewrite what modern infrastructure can do.
02:40 PM to 03:10 PM
Open
KEYN:
Keynote 12: Where In the World is Tom Coughlin?
Mission City Ballroom (Santa Clara Convention Center, First Floor)
Track:
Keynotes
Keynote Speakers:
Keynote Description:
Tom Coughlin, Former IEEE President/FMS Conference Chair, FMS
Tom Coughlin, FMS Conference Chair, is President, Coughlin Associates and a digital storage analyst and business/ technology consultant. He has over 40 years in the data storage industry with engineering and senior management positions. Coughlin Associates consults, publishes books and market and technology reports and puts on digital storage and memory-oriented events. He is a regular contributor for forbes.com and M&E organization websites. He is an IEEE Fellow, 2025 IEEE Past President, Past-President IEEE-USA, Past Director IEEE Region 6 and Past Chair Santa Clara Valley IEEE Section, and is also active with SNIA and SMPTE. For more information on Tom Coughlin go to www.tomcoughlin.com.
Tom Coughlin was elected President-Elect of the IEEE in 2022. In 2023 he was the President Elect and in 2024 the IEEE President. During 2024 he traveled 250 days, visited 26 countries and thirteen states, some more than once. In this presentation he will discuss what our focus was while he was President, some things we accomplished and a few stories from his travels.
03:15 PM to 04:20 PM
PRO
AIML-203-1:
Storage for AI: Benchmark and Test
Ballroom A (Santa Clara Convention Center, First Floor)
Track:
AI and ML Applications
Chairperson:
Carina Chen, Manager, DRAM Product Marketing, Samsung Semiconductor
Carina Chen is DRAM Product Marketing Manager at Samsung Semiconductor, responsible for DRAM product transition, new product launches, and market enablement initiatives. She has also led CXL marketing efforts, focusing on use case analysis and ecosystem engagement. Prior to Samsung, Carina worked in venture capital and consumer electronics, supporting early-stage tech startups in scaling their GTM strategies and accelerating growth. She holds an MS in Communications from Northwestern University and a BS in Marketing from Emerson College.
Organizer:
David McIntyre, Director Product Planning, Samsung Electronics
David McIntyre focuses on computational storage acceleration solutions development and strategic business enablement for cloud to edge applications including AI inference/video analytics, database processing and blockchain networks. He has held senior management positions with IBM, Samsung, Xilinx, Intel (formerly Altera) and at Silicon Valley startups. He has consulted for institutional investors including Fidelity, Goldman Sachs and UBS. David is a frequent presenter and chairperson at the Flash Memory Summit and other technical conferences including SNIA.
Presenters:
Presentation Session Description:
Murat Siyfiyev, System Performance Engineer, Micron Technology
Presentation Title:
Benchmarking Updates for Storage AI Workloads
Presentation Abstract:
Current A storage benchmarks (like MLPerf Storage) require the deployment of AI frameworks such as pytorch or tensorflow. While this is useful for accurately representing a real workload it is a difficult process for test and validation of enterprise SSDs.
In this session we go over a process to deconstruct the MLPerf Storage training workloads and represent them with FIO. Then we will analyze IO traces of the workloads to show that they produce the same workload to disk without the overhead of complex, pre-requisite ridden AI frameworks.
Author Bio:
Murat Siyfiyev is a System Performance Engineer at Micron Technology, working on creating synthetic AI workloads using FIO. Previously he worked as SSD Validation Engineer at Micron and has a BS in Computer Science from Univeristy of Colorado Denver.
Sayali Shirode, Senior Systems Performance Engineer, Micron Technology
Presentation Title:
Benchmarking Updates for Storage AI Workloads
Presentation Abstract:
With the rapid pace of AI, storage benchmarking needs to also keep up to ensure devices will meet the ever evolving requirements. We plan to discuss two areas of focus towards improving AI benchmarking: 1) MLPERF Storage 2.0 updates for checkpoint and Vector databases, and 2) simplifying AI workload analysis using FIO.
MLPerf Storage 2.0 released with two new benchmarks: Checkpointing and Vector Databases. This session will discuss the vector database benchmark, its implementation, and how it relates to real AI clusters. Finally, we'll cover an analysis of the IO patterns of this workload covering traits such as: LBA access pattern, IO sizes, and Queue Depth histograms.
In addition, we will go over a process to deconstruct the MLPerf Storage training workloads and represent them with FIO. Then we will analyze IO traces of the workloads to show that they produce the same workload to disk without the overhead of complex, pre-requisite ridden AI frameworks.
Author Bio:
S.Shirode received M.S. in Electrical and Computer Engineering from Colorado State University in 2015. Sayali has over 6 years of experience and is currently focused on analyzing the performance for data center applications. She is a Senior Storage Performance Engineer at Micron Technology, Inc. Sayali worked as Firmware Test Engineer prior to this role at Micron.
Devasena Inupakutika, Performance Engineer, Samsung Semiconductor Inc.
Presentation Title:
Storage I/O Characterization of VectorDBs
Presentation Abstract:
The integration of Vector Databases (VectorDBs) with MLPerf's storage presents a unique opportunity to evaluate the performance and scalability of local storage and distributed systems handling large-scale datasets in AI workloads. This study explores the synergy between VectorDBs and MLPerf, focusing on the storage and I/O characterization of scale-out datasets in a local storage and distributed, file-based scale out system settings. By conducting extensive I/O profiling and performance analysis, we aim to assess the storage access patterns, and query performance. This study investigates how vector embeddings interact with the underlying storage, highlighting the impact of different storage configurations, metadata filtering with vector search on both local and distributed on the performance and scalability of AI workflows.
Author Bio:
Devasena works with Samsung Semiconductor Inc. in the Datacenter Technology and Cloud Solutions Lab. She conducts data center systems and storage performance analysis with focus on AI/ ML workloads.
This session brings together insights from cutting-edge research and practical implementations in the realm of vector databases and AI storage benchmarks, highlighting the intricate relationship between database performance, storage efficiency, and AI workload optimization. The presentations collectively explore the Vector Database Benchmark as a critical tool for evaluating high-dimensional data handling and similarity searches, emphasizing the importance of indexing methods such as IVF, HNSW, and DiskANN in optimizing storage and performance. Additionally, the integration of Vector Databases with MLPerf's storage system is examined, shedding light on the synergy between local and distributed systems in managing large-scale datasets for AI applications. The discussions extend to MLPerf Storage 2.0 updates, focusing on checkpointing and vector database benchmarks and their relevance to AI clusters. A novel approach to deconstructing MLPerf Storage training workloads using FIO is also presented, offering a streamlined method to replicate AI workload characteristics without the complexities of full AI frameworks. This comprehensive session underscores the critical role of efficient storage solutions and benchmarking in supporting the evolving demands of AI technologies.
Open
BMKT-203-1:
CMO Panel
GAMR-1 & 2 (Great America Meeting Rooms, SCCC 2nd Floor)
Track:
Business Strategies & Memory Markets
Chairperson:
George Crump, CMO, Verge.IO
George Crump is the Chief Marketing Officer at Verge.IO.
Organizer:
Jay Kramer, Founder, Network Storage Advisors
Jay Kramer, founder at Network Storage Advisors, is a dynamic results-oriented strategic marketing leader and creator of world-class marketing teams with a proven track record of building company brand and demand generation initiatives that accelerate sales.
He has over 25 years of repeated marketing success with industry leading Fortune 500 companies (Unisys, Seagate) as well as early and late stage emerging companies. His industry knowledge spans cloud, virtualization, software defined storage (SDS), hyper convergence, data protection, SAN, NAS, and object storage solutions plus network storage technologies including Fibre Channel, iSCSI, VTL, dedup, backup, and replication.
He has served as board member to technology industry associations and event development/professional conference companies.
Panel Members:
Panel Session Description:
John Mao, VP Global Business Development , VAST Data
A technology executive and leader with over 20-years of cross-functional experience in early and growth stage technology companies, John is currently the VP of global business development and strategic alliances at VAST Data, focused on enabling AI, data analytics, and cloud use-cases for large data organizations. Prior to joining VAST, John led product management and product strategy teams across a wide range of technology verticals including cloud infrastructure, network and application performance management, custom hardware (silicon), big data / analytics, storage and hyper-converged infrastructure. Starting his career as a database engineer provided an onramp into the world of unlocking meaningful insight from large datasets, a passion he still possesses today. John holds a B.S. in Computer Science from the University of Texas.
Floyd Christofferson, VP of Product Marketing , Hammerspace
Floyd Christofferson is VP of Product Marketing at Hammerspace.
Gokul Sathiacama, Vice President & General Manager, Hewlett Packard Enterprise
Gokul Sathiacama is the Vice President and General Manager for the File and Object Data Storage for AI at Hewlett Packard Enterprise (HPE). Gokul is responsible for the strategy and execution of the portfolio and works closely with the sales and marketing teams, to accelerate HPE's innovation agenda.
Gokul’s data storage career spans over 20+ years, with leadership roles in engineering, product management and marketing. Prior to joining HPE in 2018, Gokul was responsible for product, solutions and technical marketing at Tegile Systems - acquired by Western Digital. Before Tegile, he guided the product direction for Coraid, Oracle and Pillar Data Systems (acquired by Oracle) and also led a global engineering team for Sun Microsystems.
Gokul earned his MBA from Pepperdine University and graduated with a Computer Engineering and Computer Science degree from the University of Southern California.
Eric Herzog, CMO, Infinidat
Eric Herzog is the Chief Marketing Officer at Infinidat. Prior to joining Infinidat, Herzog was CMO and VP of Global Storage Channels at IBM Storage Solutions. His executive leadership experience also includes: CMO and Senior VP of Alliances for all-flash storage provider Violin Memory, and Senior Vice President of Product Management and Product Marketing for EMC’s Enterprise & Mid-range Systems Division.
Patrick Osborne, SVP and GM, Cloud Data, HPE
Patrick Osborne is a Senior Vice President and General Manager, Cloud Data, at HPE.
Gary Lyng, VP, Portfolio Marketing and Analyst, Hitachi Vantara
Gary Lyng is Vice President, Portfolio Marketing and Analyst, at Hitachi Vantara.
Jyothi Swaroop, Chief Marketing Officer, DDN
Jyothi Swaroop is Chief Marketing Officer at DDN.
The informative and entertaining CMO Panel returns to FMS, with Marketing Officers from DDN, Hammerspace, HPE, Hitachi Vantara and INFINIDAT. This session will provide secrets into the marketing playbook of these successful storage solution vendors. These executives will provide their vision for the storage industry and future solutions. Get insights into the changing customer requirements and how to turn these new customer selection criteria into winning go-to-market strategies.
PRO
CXLT-203-1:
CXL Use Cases
Ballroom B (Santa Clara Convention Center, First Floor)
Track:
CXL
Chairperson + Organizer:
Anil Godbole, Sr. CXL Mktg Manager, Intel
Anil Godbole is a CXL Marketing Working Group Co-Chair and Senior Marketing Manager for Intel’s Xeon Product Planning and Marketing Group. His domain is in Memory, Serdes Technologies & Associate Protocols (DDRx, CXL, PCIe, Ethernet, etc.). Previously, he held a position as Design Engineer in CPU-support ASICs, FPGAs.
Presenters:
Presentation Session Description:
Mahinder Saluja, Director of Technology and Storage Pathfinding, KIOXIA America, Inc.
Presentation Title:
Eliminate Data Bottlenecks with CXL Interface and Low-latency XL-Flash
Presentation Abstract:
CXL-attached flash memory enables tiered and pooled storage, significantly enhancing price, capacity, and performance. By integrating Flash memory’s speed and reliability with CXL’s low latency and high bandwidth, Flash over CXL optimizes large-memory, AI-driven workloads. This seamless architecture eliminates data bottlenecks, addressing the limitations of traditional storage solutions for high-performance computing.
Author Bio:
Mahinder has 20+ years of engineering leadership in innovative storage technologies development, building teams and product delivery. Currently Mahinder is one of the main leads for SSD technology strategy at KIOXIA America, Inc., collaborating with industry experts. He has several pending storage related patents.
Anil Godbole, Sr. CXL Mktg Manager, Intel
Presentation Title:
Boost your In-memory Database Performance with CXL Memory
Presentation Abstract:
Today memory is one of the highest BOM cost item in a Datacenter Server/Rack. Extensive deployment for In-memory database & AI workloads is the primary reason. Multi-multi core CPUs are now available to support the needed compute power. Besides the native DRAM memory channels these CPUs also sport CXL interfaces to augment the memory capacity & bandwidth of the server. This presentation will focus on innovative ways CXL memory can be used to boost performance of the above mentioned workloads.
Author Bio:
Anil Godbole is a CXL Marketing Working Group Co-Chair and Senior Marketing Manager for Intel’s Xeon Product Planning and Marketing Group. His domain is in Memory, Serdes Technologies & Associate Protocols (DDRx, CXL, PCIe, Ethernet, etc.). Previously, he held a position as Design Engineer in CPU-support ASICs, FPGAs.
Minseong Kim, Distinguished Engineer, SK hynix
Presentation Title:
CXL Memory Use Cases: Insights into Expansion and Pooling
Presentation Abstract:
We explore two primary approaches to utilizing the CXL Memory Module (CMM): memory expansion by integrating CMMs into individual servers and memory pooling by consolidating multiple CMMs within a pooling server. Through comprehensive workload evaluations and studies, we assess the benefits and feasibility of each approach across diverse use cases.
Author Bio:
He is a Distinguished Engineer at SK hynix, specializing in performance analysis of DRAM-based server systems and exploring use cases for emerging memory technologies. His current research focuses on next-generation system architectures and applications involving CXL memory (expansion/pooling), PIM, and MRDIMM to enhance scalability in data centers. He earned a Ph.D. in Electronics, Electrical, and Computer Engineering from Korea University, where his research centered on system architecture, performance analysis, and prediction.
Khurram Malik, Director, Product Marketing, CXL, Marvell
Presentation Title:
Addressing Server Memory Bandwidth and Capacity Challenges in Cloud Data Centers
Presentation Abstract:
Marvell Structera CXL devices are designed to address the growing demands of cloud data centers, particularly for memory-intensive workloads. The Structera A 2504 near-memory accelerator integrates 16 Arm Neoverse V2 cores to enhance performance in applications such as deep learning recommendation models). It supports up to 200 GB/s memory bandwidth and a maximum of 4 TB of DDR5 memory.
The Structera X 2504 memory-expansion controller enables substantial scaling of server memory capacity. It supports configurations up to 8 TB of DDR5 memory across eight DIMMs, which is crucial for mission-critical applications such as AI and in-memory databases. By facilitating the seamless integration of additional memory resources, the Structera X device allows data center server infrastructure to adapt to evolving workload requirements without compromising memory capacity.
The presentation will highlight specific use cases for both products, demonstrating how Structera A CXL devices accelerate machine learning workloads by optimizing memory access; and how Structera X devices efficiently expand memory capacity for large-scale data processing.
Author Bio:
Khurram Malik is the Director of Product Marketing for CXL at Marvell, where he manages the CXL product portfolio and advanced memory technology, driving adoption among data center and enterprise customers. In his previous role, he was responsible for product and technical marketing for Marvell’s storage accelerator product lines within the Flash Business Unit.
Previously, Khurram Malik served as Technical Marketing Manager for the enterprise, data center, and client SSD product portfolios at Samsung Semiconductor Inc. His career also includes various roles at SK Hynix Memory Solution, Link A Media Devices Corporation, Broadcom Corporation, and Maxim Integrated Products, where he contributed significantly to product definition and development.
Yu-Ming Chang, Director, Wolley
Presentation Title:
NVMe-oC Powered Memory Tiering: Unlocking Cost-Effective Data Management in DC
Presentation Abstract:
To sustain the rapid growth of AI, cloud computing, and high-performance workloads, datacenters need memory solutions that balance speed, capacity, and cost, making memory tiering a crucial innovation. Wolley introduces an NVMe-oC powered memory tiering solution that seamlessly unifies DRAM, HDM (CXL device memory), and SSD into a single, intelligent memory space, delivering unprecedented efficiency without requiring any modifications to user applications. By leveraging NVMe-oC, which combines CXL device memory with SSD, our approach enables efficient data migration across tiers. A software policy dynamically detects data hotness, which ensure critical workloads benefit from high-speed DRAM, while less frequently accessed data is intelligently allocated to SSD, with HDM serving as an ultra-fast intermediate buffer. Our transparent, automated tiering mechanism boosts performance, reduces data movement latency, maximizes resource utilization, lowers TCO, and makes it a game-changer for large-scale datacenter efficiency.
Author Bio:
Dr. Yu-Ming Chang is the Director at Wolley since 2016 in charge of technology and product development for storage class memory (SCM) controller and NVMe-over-CXL. Prior to joining Wolley, he served as manager in Emerging System Lab, a division of Macronix Taiwan, and technical consultant in National Security Bureau. Dr. Chang published more than 50 technical papers in global conferences including DAC, ICCAD, and ISPLED. He has also submitted 40+ patent applications, and received 23 patents. Dr. Chang received his Ph.D. degree in Computer Science and Information Engineering at National Taiwan University.
In this session, we delve into the transformative potential of Compute Express Link (CXL) technology in reshaping data center memory architectures to meet the escalating demands of AI, cloud computing, and high-performance workloads. Across multiple presentations, key themes include the integration of CXL Memory Modules (CMMs) for memory expansion and pooling, the deployment of advanced CXL devices like Marvell's Structera series to enhance memory bandwidth and capacity, and the critical role of memory tiering in optimizing resource allocation. Presenters highlight the synergy between CXL interfaces and multi-core CPUs to boost performance for in-memory databases and AI workloads, while innovative solutions like Wolley's NVMe-oC powered memory tiering offer a unified, efficient memory space that intelligently manages data across DRAM, HDM, and SSD tiers. Additionally, the integration of CXL-attached flash memory for tiered and pooled storage solutions underscores the importance of reducing data bottlenecks and enhancing large-scale data center efficiency. Collectively, these insights underscore CXL's pivotal role in creating agile, scalable, and cost-effective memory solutions that cater to evolving workload requirements.
Open
DRAM-203-1:
DRAM: Future Research
GAMR3 (Great America Meeting Rooms, SCCC 2nd Floor)
Track:
DRAM
Organizer + Chairperson:
Ju Jin An, Senior Technical Staff Member, IBM
Ju Jin An is a Senior Technical Staff Member in IBM's Infrastructure Supply Chain Organization. Ju Jin has a background in silicon fabrication process R&D and manufacturing process integration through 20 years of career in the semiconductor industry. She is responsible for enabling memory sub-system for IBM power and z system. She holds a MS/Ph.D. degree in Chemical Engineering from MIT and a BS from Seoul National University.
Presenters:
Presentation Session Description:
Abdullah Giray Yaglikci, Postdoctoral Researcher and Lecturer, SAFARI Research Lab at ETH Zurich
Presentation Title:
Understanding and Securing the Cutting-Edge Industry Solutions to RowHammer
Presentation Abstract:
We present the first rigorous security, performance, energy, and cost analyses of the state-of-the-art industry solution to RowHammer, PRAC. We identify PRAC’s two major weaknesses and propose Chronus, a new mechanism that addresses those weaknesses.
We show that PRAC’s performance overhead is non-negligible for modern DRAM chips and increasingly grows going forward. This is because PRAC increases critical DRAM access latency constraints due to the additional time required to increment activation counters and performs a constant number of preventive refreshes at a time, making it vulnerable to an adversarial access pattern, wave attack, and consequently requiring it to be configured for significantly smaller activation thresholds.
Our solution, Chronus, updates row activation counters concurrently while serving accesses by separating counters from the data and prevents the wave attack by dynamically controlling the number of preventive refreshes performed. Our performance analysis shows that Chronus’s performance overhead is near-zero for modern DRAM chips and very low for future DRAM chips. We open-source our Chronus implementation at https://github.com/CMU-SAFARI/Chronus.
Author Bio:
Giray is a postdoctoral researcher and lecturer at the Safari Research Group in ETH Zürich. Giray’s Ph.D. thesis, advised by Prof. Onur Mutlu, builds 1) a detailed understanding of DRAM read disturbance, a major limitation of main memory density scaling, and 2) mechanisms that efficiently and scalably mitigate DRAM read disturbance. Giray’s broader research interests span high-performance, energy-efficient, and secure computer architectures aiming securely and sustainably scalable systems. Giray has published several works in this field in major venues, including HPCA, MICRO, DSN, ISCA, and USENIX Security. His research is 1) in part supported by Google Security and Privacy Research Award and Microsoft Swiss Joint Research Center and 2) recognized by HOST 2024 PhD Dissertation Competition (chosen as a finalist), ETH Medal (nominated), Intel Hardware Security Academic Award 2022 (chosen as a finalist), and ACM PACT Student Research Competition 2023 (won the first place). Giray is on the job market for research positions in industry and academia.
Rakesh Nadig, Ph.D. Student, SAFARI Research Group at ETH Zurich
Presentation Title:
Harmonia: Multi-Agent RL for Data Placement and Migration in Hybrid Storage
Presentation Abstract:
Hybrid storage systems (HSS) combine multiple storage devices with diverse characteristics to achieve high performance and capacity at low cost. The performance of an HSS highly depends on the effectiveness of two key policies: (1) the data-placement policy, and (2) the data-migration policy. Unfortunately, no prior work tries to optimize both policies together.
Our goal is to design a holistic data-management technique for HSS that optimizes both data-placement and data-migration policies to fully exploit the potential of an HSS. We propose Harmonia, a multi-agent reinforcement learning (RL)-based data-management technique that employs two light-weight autonomous RL agents, a data-placement agent and a data-migration agent, which coordinate to adapt their policies for the current workload and HSS configuration.
We evaluate Harmonia on a real HSS with up to four heterogeneous storage devices using 17 data-intensive workloads. On average, Harmonia (1) outperforms the best-performing prior approach by 49.5%, (2) bridges the performance gap between the best-performing prior work and Oracle by 64.2%. We plan to open-source Harmonia’s implementation to aid future research on HSS.
Author Bio:
Rakesh Nadig is a fourth-year Ph.D. student in the SAFARI Research Group at ETH Zurich, advised by Prof. Onur Mutlu. His main research areas are storage systems, heterogeneous storage/memory systems, near-data processing and machine learning in computer architecture. Prior to joining SAFARI, Rakesh worked as a Senior Staff Engineer at Samsung Semiconductor Research Labs in Bangalore, India. Rakesh obtained a master’s degree in Electrical and Computer Engineering from the University of California at Irvine.
Ataberk Olgun, PhD Student, SAFARI Research Group at ETH Zurich
Presentation Title:
Sectored DRAM: Energy-Efficient, High-Performance Fine-Grained DRAM Architecture
Presentation Abstract:
We propose Sectored DRAM, a new, low-overhead DRAM substrate that reduces wasted energy by enabling fine-grained DRAM data transfers and DRAM row activation. Sectored DRAM leverages two key ideas to enable fine-grained data transfers and row activation at low chip area cost. First, a cache block transfer between main memory and the memory controller happens in a fixed number of clock cycles where only a small portion of the cache block (a word) is transferred in each cycle. Sectored DRAM augments the memory controller and the DRAM chip to execute cache block transfers in a variable number of clock cycles based on the workload access pattern with minor modifications to the memory controller's and the DRAM chip's circuitry. Second, a large DRAM row, by design, is already partitioned into smaller independent physically isolated regions. Sectored DRAM provides the memory controller with the ability to activate each such region based on the workload access pattern via small modifications to the DRAM chip's array access circuitry. We hope and believe that Sectored DRAM's ideas and results will help to enable more efficient and high-performance memory systems.
Author Bio:
Ataberk Olgun is a 4th year PhD student at ETH Zurich. His broad research interests include designing secure, high-performance, and energy-efficient DRAM architectures.
Ataberk Olgun, PhD Student, SAFARI Research Group at ETH Zurich
Presentation Title:
Self-Managing DRAM: A Low-Cost Framework for Autonomous in-DRAM Operations
Presentation Abstract:
The memory controller is in charge of managing DRAM maintenance operations (e.g., refresh, RowHammer protection, memory scrubbing) to reliably operate modern DRAM chips. Implementing new maintenance operations often necessitates modifications in the DRAM interface, memory controller, and potentially other system components. Such modifications are only possible with a new DRAM standard, which takes a long time to develop, likely leading to slow progress in the adoption of new architectural techniques in DRAM chips.
We propose a new low-cost DRAM architecture, Self-Managing DRAM (SMD), that enables autonomous in-DRAM maintenance operations by transferring the responsibility for controlling maintenance operations from the memory controller to the SMD chip. To enable autonomous maintenance operations, we make a single modification to the DRAM interface, such that an SMD chip rejects memory controller accesses to DRAM regions under maintenance, while allowing memory accesses to others. SMD can be implemented without adding new pins to the DDRx interface with low latency and area overhead and provides substantial speedups over a state-of-the-art baseline DRAM-based computing system.
Author Bio:
Ataberk Olgun is a 4th year PhD student at ETH Zurich. His broad research interests include designing secure, high-performance, and energy-efficient DRAM architectures.
Ataberk Olgun, PhD Student, SAFARI Research Group at ETH Zurich
Presentation Title:
An Experimental Analysis of Temporal Variation in DRAM Read Disturbance
Presentation Abstract:
Modern DRAM chips are subject to read disturbance errors. State-of-the-art read disturbance mitigations rely on accurate and exhaustive characterization of the read disturbance threshold (RDT) of every DRAM row to prevent read disturbance bitflips securely and with low overhead.
We experimentally demonstrate for the first time that the RDT of a DRAM row significantly and unpredictably changes over time. Our experiments using 160 DDR4 chips and 4 HBM2 chips from three major manufacturers yield two key observations. First, it is very unlikely that relatively few RDT measurements can accurately identify the RDT of a DRAM row. Second, the probability of accurately identifying a row's RDT with a relatively small number of measurements reduces with increasing chip density or smaller technology node size. Our empirical results have implications for the security guarantees of read disturbance mitigation techniques. We hope and believe future work on efficient online profiling mechanisms and configurable read disturbance mitigation techniques could remedy the challenges imposed on today’s read disturbance mitigations by the variable read disturbance phenomenon.
Author Bio:
Ataberk Olgun is a 4th year PhD student at ETH Zurich. His broad research interests include designing secure, high-performance, and energy-efficient DRAM architectures.
In this insightful session, we delve into innovative advancements in DRAM and hybrid storage systems aimed at addressing critical challenges in performance, cost, and security. From Chronus, a mechanism enhancing the state-of-the-art RowHammer solution by reducing performance overhead and fortifying against wave attacks, to Harmonia's reinforcement learning approach optimizing data placement and migration in Hybrid Storage Systems, these presentations highlight the integration of cutting-edge technology for efficiency. Sectored DRAM introduces a low-overhead technique for fine-grained data transfers, promoting energy efficiency and high performance, while Self-Managing DRAM shifts maintenance responsibilities in-DRAM to accelerate architectural adoption. Additionally, addressing the fluctuating read disturbance threshold in modern DRAM chips, the session underscores the need for robust profiling mechanisms to enhance security. Collectively, these innovations signify strides toward more reliable, efficient, and secure memory systems for future technological landscapes.
PRO
FARC-203-1:
Flash Architectures and Provisioning
Ballroom F (Santa Clara Convention Center, First Floor)
Track:
FDP and ZNS
Organizer + Chairperson:
Brian Berg, President, Berg Software Design
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley Section, Director and past Chair of the Consultants Network of Silicon Valley, Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for Outstanding Service to the Consulting and Electrical Engineering profession, and the 2012 Outstanding Leadership and Professional Service Award for Region 6.
Presenters:
Presentation Session Description:
Rory Bolt, Senior Fellow, KIOXIA America
Presentation Title:
FDP Use Cases
Presentation Abstract:
Real world benefits of Flexible Data Placement (FDP) that can be realized without modifying software. A common software development workflow achieved great WAF improvements without requiring any code changes by using FDP with simple system configuration changes. The experiment with a typical Continuous Integration/Continuous Deployment (CI/CD) environment and its results are presented along with a surprising possible benefit.
Author Bio:
Rory Bolt is a senior fellow at KIOXIA America and leads the forward-looking technology and storage pathfinding group for SSDs. He has more than twenty-five years of experience in data storage systems, data protection systems, and high-performance computing with a pedigree from marquee storage companies. Rory has been granted over 12 storage related patents and has several pending. Rory has a BS in Computer Engineering from UCSD.
Chandra Guda, SSD Systems Architect, Micron
Presentation Title:
Benefits of FDP on Device Power Efficiency
Presentation Abstract:
Flexible Data Placement has a clear benefit on workload performance. Through efficient placement of data on the SSD, you will get the benefit of lower write amplification and higher performance but are there other benefits? This presentation will explore the fundamentals of FDP and highlight the benefits on performance as well as drive power efficiency through the study of applications and synthetic workloads.
Author Bio:
Chandra Guda received his M.S in Electrical Engineering from New Jersey Institute of Technology (Newark, New Jersey USA) in 2008. Mr.Guda is an SSD Systems Architect at Micron. He is responsible for developing technical architecture for Datacenter NVMe SSDs. Mr. Guda focuses on QoS/Performance features and SSD AI Workload Analysis for Datacenter SSDs at Micron. Mr. Guda has over 30 patents granted in the areas of caching architectures, Performance, QoS. He previously held positions with Western Digital as a firmware engineer working on HDDs and SSHDs.
Javier Gonzalez, Principal Engineer, Samsung
Presentation Title:
FDP Panel: Use Cases and Industry Trends
Presentation Abstract:
FDP Panel on use-cases and industry trends
Author Bio:
I lead Samsung Semiconductor's Global Open-ecoSystem Team (GOST - https://tinyurl.com/SamsungGOST), where I take care of our ecosystem activities and manage a distributed team of highly talented engineers. This includes defining our vision, strategy, internal / external communication, and day-to-day execution. I am also the founder and site manager for Samsung Semiconductor Denmark Research (SSDR) - Samsung’s Memory Solutions first R&D center in Europe and fifth worldwide.
Heechul Chae, Application Engineer, FADU
Presentation Title:
Enhancing Checkpointing Performance in GPUs using FDP
Presentation Abstract:
Checkpointing in GPUs is a challenging task due to bandwidth constraints and bottlenecks in shared SSD storage. Traditional methods often struggle with bandwidth allocation, leading to contention and performance degradation across GPUs. In this talk, we introduce a novel approach leveraging FDP Reclaim Units (RUs) assigned to each GPU in a cluster. These RUs provide dedicated bandwidth, minimized contention, and a significant improvement to checkpointing efficiency. We will explore the implementation, performance benchmarks, and scalability potential of this approach, along with future architectural enhancements to further optimize GPU checkpointing.
Author Bio:
Having gained experience at SAMSUNG, I am currently working at FADU, focusing on SSD performance and the optimization of SSD-based application technologies, including FDP.
Viacheslav Dubeyko, Linux kernel developer, IBM
Presentation Title:
Building an Efficient Ecosystem Using ZNS SSDs
Presentation Abstract:
ZNS SSD represents an efficient engine with multiple limitations for any file system architecture:
- How to deal with append-only mode without introducing GC subsystem on the file system side?
- How to manage huge zone sizes efficiently?
- How can a file system survive in the environment of a limited number of open/active zones?
- Can a regular file system that uses an in-place update technique manage operation of a ZNS SSD without any modifications?
- Is it feasible to combine ZNS SSDs and a computational engine in one device?
This talk will analyze various file system architectures, techniques, and approaches that can employ the benefits of ZNS, manage ZNS limitations, and achieve good efficiency and performance for file system operations.
Author Bio:
I was born in a small and nice Russian town in 1973. My first passion was physics and I graduated in 1997 with specialization in X-ray spectroscopy. Then, I acquired a Ph.D degree (X-ray spectroscopy) after finishing my postgraduate studies in 2002. But I always had a passion for programming and algorithms designing and I started my career as C++ developer in 2004. As a result, I was in production development for around 6 years. My research career started in 2010 and I served as a researcher in several companies (Samsung Electronics, Huawei, HGST, Western Digital). I am involved in Linux kernel open-source activity and I contributed in HFS+ and NILFS2 file system drivers. Also, I designed and implemented a SSDFS (flash-friendly) open-source file system. My research interests include file systems and data storage design, neuromorphic computing, data-centric and memory-centric computing, cognitive computing, and quantum computing. I have several papers and around 50 patents.
This session converges on the transformative potential of Flexible Data Placement (FDP) and Zoned Namespaces (ZNS) in enhancing data management, performance, and efficiency across diverse computational environments. The presentations collectively underscore FDP's ability to optimize data placement on SSDs, yielding notable reductions in write amplification and power consumption without necessitating software modifications. Real-world applications, such as CI/CD workflows and GPU checkpointing, illustrate FDP's capacity to streamline processes and mitigate bottlenecks, significantly enhancing performance and scalability. Meanwhile, the exploration of ZNS SSDs highlights architectural innovations required to handle unique constraints like append-only modes and zone management, while maximizing file system performance. Together, these insights reveal a cohesive narrative of data-centric strategies driving efficiency and innovation in storage technologies.
Open
INDA-203-1:
SNIA Technical Activities
Ballroom D (Santa Clara Convention Center, First Floor)
Track:
Industry Associations
Chairperson + Presenter:
Richelle Ahlvers, Vice Chair, SNIA
Richelle Ahlvers runs Technology Initiatives and Ecosystem Enabling for the Datacenter / AI business for Intel, promoting and driving enablement of new technologies and standards strategies. Richelle has spent over 30 years in Enterprise R&D teams in a variety of technical roles, spanning architecture, design and development of software, firmware, and hardware, for everything from enterprise storage solutions to CPUs.
Richelle has been engaged with industry standards initiatives for many years and is actively engaged with many groups including SNIA, DMTF, NVMe, OFA and UCIe. She is Vice-Chair of the SNIA Board of Directors, Chair of the Storage Management Initiative, leads the SSM Technical Work Group developing the Swordfish Scalable Storage Management API, and is a former SNIA Technical Council Chair. She serves on the DMTF Board of Directors as the VP of Finance and Treasurer.
Presenters:
Presentation Session Description:
Anthony Constantine, SFF TWG Co-chair, SNIA
Anthony Constantine is a Distinguished Member of the Technical Staff at Micron Technology responsible for storage standards within the Storage Business Unit. He is involved through authoring or contributing in various industry organizations including NVMe, SNIA, JEDEC, PCI-SIG, and OCP. Anthony has over 24 years of experience in the technology industry with an expertise in memory, storage, physical interfaces, low power technologies, and form factors. He earned a BS in Electrical Engineering from UC Davis.
Jason Molgaard, Principal Storage Solutions Architect, Solidigm
Jason Molgaard is an experienced storage controller RTL designer and architect having worked for various storage device companies architecting and designing HDD and SSD storage controllers. As a Principal Storage Solutions Architect on the Solidigm Pathfinding and Advanced Development Team, Jason focuses on future storage controller architectures and technologies, including Computational Storage and CXL. Jason is co-chair of the SNIA Computational Storage TWG and the SNIA Technical Council. Jason helps drive the Computational Storage standard at both SNIA and NVMe. Jason holds a Master of Science degree in Electrical Engineering.
David Landsman, Distinguished Engineer, Western Digital Corporation
Dave is a Distinguished Engineer and Director of Storage Standards at Western Digital Corporation. His early years were at Intel, where he wrote early generation Ethernet driver software, worked as a product planner on a generation of the Intel i860 superscalar processor, and was a member of Intel’s technical liaison team with Microsoft, where he focused on getting Windows support for Intel processor, graphics, and chipset features. Dave began his career in storage in 2004, joining mSystems, which led to Sandisk and Western Digital, by acquisitions. Since 2008, Dave has been a leader in the storage interface standards community, driving Sandisk’s and Western Digital’s engagements in NVMe, PCIe, SAS/SCSI, ATA/SATA, TCG, JEDEC, OCP, SNIA, SFF, CFA, and others. In 2019, he helped found the DNA Data Storage Alliance. He recently published the Alliance’s DNA Stability Evaluation Method specification and has published various articles and white papers on DNA data storage with the Alliance. He received his B.A. degree in Computer Science from the University of California, San Diego, in 1980.
Come hear about all of the developments in SNIA technical activities and our communities. You will learn how SNIA is working together with other industry organizations to enable higher performance for AI applications. Hear updates on what is going on in the areas of DNA data storage for long term data retention, Cloud Object Storage to provide for better interoperability of cloud applications with cloud service providers, and Connectors and Form Factors to support 400G. Also hear from our communities that provide education in the areas of SCSI, Storage Management, Green, Compute, Storage, and Persistent Memory. You will get a brief taste of all the work that is going on and an invitation to join us in our technical work groups to participate.
PRO
OPSW-203-1:
NVMe SSD Virtualization Ecosystem - A Panel
Ballroom E (Santa Clara Convention Center, First Floor)
Track:
Open Source Software
Organizer + Chairperson:
Javier Gonzalez, Principal Engineer, Samsung
I lead Samsung Semiconductor's Global Open-ecoSystem Team (GOST - https://tinyurl.com/SamsungGOST), where I take care of our ecosystem activities and manage a distributed team of highly talented engineers. This includes defining our vision, strategy, internal / external communication, and day-to-day execution. I am also the founder and site manager for Samsung Semiconductor Denmark Research (SSDR) - Samsung’s Memory Solutions first R&D center in Europe and fifth worldwide.
Panel Members:
Panel Session Description:
Klaus Jensen, Software Engineer, Samsung Electronics
Klaus is a software engineer at Samsung Semiconductor Denmark Research where he leads a small, dedicated team tasked with technology adoption and open-ecosystem enablement of emerging NVMe® and PCIe® technologies. He is involved with the NVMe® community as a technical proposal co-author and maintains the QEMU emulated NVMe® device.
Chaitanya Kulkarni, Director, NVIDIA
With a Master’s Degree in Computer Science by research in High-
Performance Computing, Chaitanya Kulkarni brings over 17 years of
dedicated experience in the field. Chaitanya has extensive experience
in various key-value stores and storage protocols, including
NVMe/NVMeOF and SCSI/iSCSI and F/W development and storage virtualization.
His knowledge extends to a range of file systems, such as ZFS, XFS,
BTRFS, Open Media Grid, and Lustre. He has hands-on experience in SSD
cache stores (EnhanceIO), flash storage, and Zoned block storage. He has
also developed and managed multi-functional teams for device drivers
across multiple platforms, including VMware, Windows, and Linux. His
in-field experience in virtualization further complements his skill set,
making him a versatile professional in the realm of high-performance
computing.
Lee Prewitt, Director Cloud Hardware Storage, Microsoft
Lee Prewitt is a Director of Cloud Hardware Storage at Microsoft with 30+ years of storage industry experience ranging from Magneto-Optical to spinning rust to Flash. His former work at Microsoft has included working in the Windows and Devices Group where he was responsible for many of the components in the storage stack including File Systems, Spaces, Storport and Microsoft’s inbox miniport drivers (SD, UFS, NVMe, etc.). He currently works in the Azure Memory and Storage (AMS) group where he is responsible for future Data Center storage initiatives, specifications (OCP, NVMe, EDSFF, etc.), and evangelization.
Nicolae Mogoreanu, Very Senior Software Engineer, Google
Google Compute Engine old timer. Tech Lead for Google Compute Engine integration with the offloaded storage devices.
This session delves into the pivotal advancements and collaborative efforts in the realm of SSD virtualization, with a particular focus on standardizing Live Migration in NVM Express® to enhance the efficiency of Virtual Machine migrations with direct-attached PCI Express® storage. Through a series of presentations and panels, experts explore the intricacies of NVMe® SSD Virtualization, discussing how hypervisors and Virtual Machine Managers can leverage open-ecosystem host software stacks to manage data and state migration. Key themes include the coordination required between hosts and devices, the challenges of tracking host memory modifications, and the strategic trade-offs in abstraction and complexity when implementing virtualization across different layers of the technology stack. Additionally, the session highlights the implications of these innovations for cloud service providers, underscoring the importance of flexibility and effective resource management in response to evolving virtualization demands.
PRO
SSDT-203-1:
High Capacity SSDs and Optimizations for QLC Flash Storage
Ballroom G (Santa Clara Convention Center, First Floor)
Track:
SSD Technology
Chairperson:
Randy Brown, Senior Principal Engineer, Marvell
Randy Brown, a graduate of Carnegie Mellon University with a degree in Computer Science, is currently a Senior Principal Engineer in the Architecture team of Marvell’s Custom, Compute and Storage Group. Randy has over 30 years of experience in the storage industry. His experience spans filesystems, advanced storage stacks including snapshot and replication, RAID, and iSCSI. He has also managed and contributed to firmware teams that have shipped multiple SATA and NVMe based SSDs.
Organizer:
Erich Haratsch, Senior Director Architecture, Marvell Semiconductor
Erich Haratsch is the Senior Director of Architecture at Marvell, where he leads the architecture definition of SSD and storage controllers. Before joining Marvell, he worked at Seagate and LSI, focusing on SSD controllers. Earlier in his career, he contributed to multiple generations of HDD controllers at LSI and Agere Systems. Erich began his career at AT&T and Lucent Bell Labs, working on Gigabit Ethernet over copper, optical communications, and the MPEG-4 video standard. He is the author of over 40 peer-reviewed journal and conference papers and holds more than 200 U.S. patents. A Senior Member of IEEE, Erich earned his MS and PhD degrees from the Technical University of Munich, Germany.
Presenters:
Presentation Session Description:
Pete Kirkpatrick, VP, Hardware Architect, Pure Storage
Presentation Title:
Maximizing the Benefits of QLC Flash for Applications Ranging from AI/ML to HDD Displacement
Presentation Abstract:
As data growth accelerates in the age of AI, hyperscalers demand higher-capacity storage solutions that deliver a balanced combination of performance, efficiency, and cost-effectiveness. Collaborating closely with hyperscaler engineering and NAND partners, Pure Storage developed a purpose-built QLC storage solution that seamlessly integrates optimized device hardware, intelligent flash management software, and streamlined operations to deliver high throughput and scalability. Explore how this technology enhances workload efficiency, reduces total cost of ownership (TCO), and simplifies deployment compared to traditional storage solutions across workloads including AI/ML and HDD displacement.
Author Bio:
Pete Kirkpatrick is the VP of Hardware Architecture at Pure Storage. He has played a critical role in advancing Pure Storage's mission to enable the widespread adoption of flash in data centers. He holds a Master’s degree in Electrical and Computer Engineering from the University of Colorado Boulder and has numerous patents to his name.
Mike Klemm, Fellow, KIOXIA America, Inc.
Presentation Title:
Offloading Storage Compute Tasks from DPU to SSD Can Free Compute Resources
Presentation Abstract:
Many applications have meta data that is small in size but accessed and updated frequently. By exposing a small amount of the QLC media as a separate pseudo SLC namespace, applications can enjoy the benefits of a high performance and high endurance media without having to dedicate entire drive slots for this purpose. Additionally, the amount of pSLC vs QLC media may be set bet by the customer depending on application needs. Finally, by allowing each QLC drive to supply a pSLC namespace, the amount of pSLC can scale with the system and when multiple drives are present there can be resiliency at the system level.
Author Bio:
Mike is a Fellow at KIOXIA America, Inc. in the Technology and Storage Pathfinding team. He has 20+ years of storage system development creating innovative technologies, building teams and delivery numerous products. Mike has 20+ storage related patents. Mike has a BS in Electrical and Computer Engineering from UW-Madison.
Sampath Ratnam, Distinguished Member of Technical Staff, Micron Technology
Presentation Title:
Optimizing SSD Use for Power and Endurance
Presentation Abstract:
As SSDs increase in size, optimizing for endurance and power is critical. From an endurance perspective, the write amplification needs to be kept to a minimum in order for the SSD to meet it life cycle goals for Drive Writes per Day (DWPDs). Some of the factors impacting this are the indirection unit sizes, data placement considerations, and other factors. From a power perspective, as drives get bigger managing the active and idle power becomes more critical design consideration especially if similar performance/W/TB is expected. The purpose of this talk is to share the challenges and opportunities of moving to larger capacity SSDs and a call to action on what can be done to improve these from a hardware and software perspective.
Author Bio:
S. Ratnam received a M.S. degree in electrical engineering from the Arizona State University, Phoenix, Arizona in 2003. He joined Micron Technology, Inc. in 2003. During his tenure at Micron over 20 years, he worked on various roles spanning from NAND Product Engineering, Media Architecture development to SSD architecture development. He is currently working as a Distinguished Member of the Technical Staff in SSD Systems Architecture.
Daniel Gomez, Staff Engineer, Samsung Electronics
Presentation Title:
Preferred I/O for High-Capacity SSDs
Presentation Abstract:
The demand for High-Capacity (HC) SSDs requires an increase in the indirection mapping used in the Flash Translation Layer (FTL) for logical-to-physical (L2P) translation. This mapping is referred to as the Indirection Unit (IU). The adoption of larger IUs for HC SSDs presents a software stack challenge: How can these drives be optimally integrated with host software? What modifications are necessary to ensure seamless adoption?
For many years, 4 KiB IU drives have been the industry standard and have sufficed. This has led to certain assumptions in host software that may no longer hold true for these new drives. Understanding and reviewing these differences, while analyzing host software behavior under these new constraints, is essential to ensuring optimal performance and endurance for HC SSDs. What are the implications of writes smaller than the Indirection Unit, and what boundaries need to be considered to facilitate proper adoption of HC SSDs?
Author Bio:
Daniel Gomez is working as a Staff Engineer at Samsung Electronics, where he is part of the Samsung’s Global Open-ecoSystem Group Team (GOST) working with the Linux kernel and High Capacity SSD enablement.
This session will delve into the transformative advancements in Solid State Drives (SSDs) as they cater to the evolving demands of modern applications and hyperscale environments. A recurring theme is the balance between performance, endurance, and power efficiency, particularly as SSDs increase in capacity. Presentations will explore innovative techniques such as utilizing pseudo SLC (pSLC) namespaces to enhance high-frequency metadata access while maintaining system resilience and flexibility. As SSDs scale, optimizing write amplification and managing power consumption become critical, offering opportunities for both hardware and software enhancements. The integration of larger Indirection Units (IUs) demands a reassessment of host software to ensure seamless adoption and optimal performance of high-capacity SSDs. Additionally, the session highlights the collaboration with hyperscalers to develop QLC storage solutions that combine hardware innovations and intelligent software management, delivering high throughput, scalability, and cost benefits crucial for AI/ML workloads and beyond. Through these discussions, attendees will gain insights into the strategies for optimizing SSD deployment in a rapidly changing technological landscape.
PRO
SUST-203-1:
Energy Efficiency
Ballroom C (Santa Clara Convention Center, First Floor)
Track:
Sustainability
Organizer:
Wayne Adams, SNIA Chairman Emeritus, SNIA
Wayne Adams has over 35 years of IT industry experience spanning business development, technical product/solution management, and partner ecosystems. Wayne has been involved in SNIA leadership roles since 2002. Wayne has served on the SNIA Board of Directors since 2003 including roles as Chair, Chair Emeritus, Treasurer in addition to a number of leadership roles for forums and initiatives, conferences, and strategic alliances. He has spoken at numerous industry forums and events. Over his career, Wayne M. Adams was a Senior Technologist and Director of Standards within the Office of the CTO at EMC, technical alliances partner manager, and a manager of product managers for its portfolio of SRM products. Prior to EMC, Wayne was responsible for product marketing and business development for several strategic software and hardware products at Digital Equipment Corporation. He started his high-tech career at Eastman Kodak as a system designer of real-time control systems. Wayne has been involved in many industry associations including serving on the DMTF Board of Directors, serving as Advisory Committee member of W3C, contributing to the Industrial Internet Consortium for IoT/big data test-beds, leadership of the Fibre Alliance, and participating with various committees within INCITS, OASIS, Cloud Security Alliance, and TheGreenGrid. Wayne holds a Bachelor of Science degree with a dual major in Computer Science and Mathematics from the University of Pittsburgh.
Presenter + Chairperson:
Bill Gervasi, Principal Memory Solutions Architect, Monolithic Power Systems
Mr. Gervasi has nearly 5 decades of experience in high speed memory subsystem definition, design, and product development. He piloted the definition of Double Data Rate SDRAM since its earliest inception, authoring the first standard specification, and created the Automotive SSD standard. With MPS, Bill is driving some of the memory and storage system management mechanisms for a post-quantum world. He received the JEDEC Technical Excellence award, their highest honor, in 2020.
Presenters:
Presentation Session Description:
Anna Fessler-Hoffman, Sustainability Specialist, Cisco
Presentation Title:
Innovating Toward Net Zero: Next-Generation Data Center Solutions
Presentation Abstract:
As the world confronts the challenges of climate change, the role of technology in shaping a more sustainable future has never been more critical. Today, I’ll walk you through the latest global emissions scenarios, why sustainability is now a top strategic priority for the tech industry, and how Cisco is helping lead the way—particularly as data center energy demand continues to surge. We’ll explore innovations in server and data center design that deliver both high performance and significant energy savings, helping our customers advance their digital transformation while addressing the environmental imperatives of our time.
Author Bio:
Anna Fessler-Hoffman is a Sustainability Specialist leading sustainability initiatives for silicon, optics, and hardware platforms across Cisco’s core Switching, Routing, and Wireless portfolios. She is responsible for driving engineering efforts that reduce Cisco’s carbon footprint and for advancing the development of hardware solutions designed with circularity and long-term environmental impact in mind.
Jung Yoon, Distinguished Engineer & CTO, IBM Supply Chain
Presentation Title:
Memory & Storage Power consumption trends in future AI Infrastructure
Presentation Abstract:
In this paper, we will provide an overall technical perspective of AI infrastructure Power consumption, driven by exponential growth in Gen AI applications, and performance requirements. We will focus on CPU/GPU/HBM driven power consumption trends, component & system reliability challenges vs thermal/cooling solutions. At the component level, we will discuss DRAM and 3D-NAND scaling – from a performance, and power consumption trends & requirement standpoint. In addition, we will discuss future EDSFF SSD form factors (e.g., E3.S, E3.L), which are specifically designed for high density enterprise & datacenter environments, and future key requirements focused on balancing performance, capacity and power efficiency.
Author Bio:
Jung Yoon is a Distinguished Engineer & CTO of IBM Supply Chain. He is a recognized industry leading expert in DRAM, 3D-NAND, SSDs, and semiconductor devices, and drives technology convergence between industry capabilities and IBM’s strategic product offerings. Jung has over 30 years of experience in the field of Semiconductor R&D, technology enablement and quality. Jung earned his PhD in Solid State Physics from Columbia University, MS from University of California Berkeley, and a BS from Seoul National University.
In this session, we will delve into the critical intersection of energy consumption, technological advancement, and environmental sustainability within the rapidly evolving landscape of AI and data infrastructure. As AI applications and cryptocurrency mining drive significant increases in global energy demand, the pressure on data centers to prioritize power efficiency has never been greater. Presentations will explore the intricate balance between performance and energy efficiency, focusing on advancements in CPU, GPU, and memory technologies, as well as innovative data center designs that optimize power usage. We will discuss the implications of these power consumption trends on environmental sustainability, highlighting strategies for mitigating the impact of technology on climate change. Additionally, we will examine emerging SSD form factors and server innovations aimed at achieving high-density performance while minimizing energy use. This session will provide a comprehensive overview of how industry leaders are spearheading efforts to align technological progress with ecological responsibility, ensuring that digital transformation contributes positively to a sustainable future.
04:00 PM to 06:00 PM
Open
SPEC-202-1:
SuperWomen at FMS Peer Exchange Happy Hour
Hyatt Evolution Courtyard (Santa Clara Convention Center, First Floor)
Track:
Special Sessions
Special Event Description:
Peer to Peer
FMS celebrates the SuperWoman in Flash award winner at a special reception sponsored by Hammerspace and Pure Storage.
05:00 PM to 07:00 PM
Open
GEN:
All Industry Reception
Exhibit Hall (Santa Clara Convention Center, First Floor)
Track:
General Events
General Event Description:
Join colleagues and friends at the All Industry Reception, sponsored by Intel.
07:15 PM to 08:30 PM
Open
SPEC-203-1:
Beer, Pizza, and Chat with the Experts
Ballrooms A-D (Santa Clara Convention Center, First Floor)
Track:
Special Sessions
Special Event Description:
Always a favorite at FMS, Chat with the Experts provides the opportunity to meet one-on-one with a large number of experts within the flash memory industry. With 40 tables devoted to each of 40 industry topics, take advantage of this opportunity to have casual conversations with these important industry players while enjoying some beer and pizza.