Program at a Glance
07:30 AM to 02:00 PM
Open
REG:
Registration
Main Lobby (Santa Clara Convention Center, First Floor)
Track:
General Events
General Event Description:
Registration for August 5-7, 2025 FMS Conference.
08:00 AM to 08:30 AM
Open
BRK:
Thursday Continental Breakfast
Track:
General Events
General Event Description:
Description Not Available
08:30 AM to 09:35 AM
PRO
AIML-301-1:
Data Analytics
Ballroom A (Santa Clara Convention Center, First Floor)
Track:
AI and ML Applications
Chairperson:
Vasanthi Jagatha, Senior Manager, Software Product Management, AI & HPC, Samsung Semiconductor
Vasanthi Jagatha is Senior Software Product Manager at Samsung. In this role, Vasanthi leads system level memory solution enablements for AI & HPC usecases with Cognos- a memory management orchestration platform for tiered memory. Vasanthi joined Samsung from Marvell and Intel where she held product management, business development and research engineering roles for Storage and FPGA products. Vasanthi earned a master’s degree in Electrical Engineering and a bachelor’s degree in Computer Systems Engineering from Arizona State University.
Organizer:
David McIntyre, Director Product Planning, Samsung Electronics
David McIntyre focuses on computational storage acceleration solutions development and strategic business enablement for cloud to edge applications including AI inference/video analytics, database processing and blockchain networks. He has held senior management positions with IBM, Samsung, Xilinx, Intel (formerly Altera) and at Silicon Valley startups. He has consulted for institutional investors including Fidelity, Goldman Sachs and UBS. David is a frequent presenter and chairperson at the Flash Memory Summit and other technical conferences including SNIA.
Presenters:
Presentation Session Description:
Suresh Bysani Venkata Naga, Director of Engineering, Eightfold.ai
Presentation Title:
Separation of Compute and Storage
Presentation Abstract:
In modern AI analytics, achieving high query-per-second (QPS) performance is critical for processing AI-driven insights and real-time agent queries. This presentation explores the strategic separation of compute and storage within analytics platforms—a paradigm shift that enables scalable, high-performance query processing. By decoupling these two key components, organizations can independently scale resources to meet the demands of intensive AI analytics workloads and agent interactions, ensuring rapid data retrieval, lower latency, and efficient resource utilization. Attendees will gain insights into the architectural benefits of this separation, including improved fault tolerance and enhanced system flexibility, making it a cornerstone for building next-generation, high-QPS analytics solutions.
Author Bio:
Suresh Bysani, an IEEE Senior Member, CNSV member, and FMS CAB member, leads the core SaaS and AI infrastructure at Eightfold.ai, managing the platform for a B2B2C product with 100 million active users. He oversees search, data, OLAP, serving stack, and AI infrastructure, bringing over a decade of experience in scaling systems. Before joining Eightfold, he was an early engineer at Cohesity, a distributed data platform. Throughout his career at both Cohesity and Eightfold, Suresh has collaborated with Fortune 100 and 500 companies to address complex infrastructure challenges at scale.
Youngjune Kang, Data Analyst, SK hynix
Presentation Title:
From Data to Insights: Establishing a Quality-Driven Data Ecosystem in D/C
Presentation Abstract:
As the importance of data centers as key hubs for information storage grows in modern society, the quality management of Enterprise SSDs has become a crucial factor for storage manufacturer. To obtain consistent quality and prevent significant quality issues at the data center level, SK hynix has developed a unique data solution by creating a Data Eco-System utilizing data from data centers. This strategy enables us to deliver innovative and reliable solutions tailored to the needs of data centers. In this project, SK hynix implemented three key functions by storing, processing, and utilizing data from data centers according to purpose. The first is Failure Rate Monitoring, which identifies patterns of failure related to factors like server compatibility and environmental conditions. The second is Drive Log Monitoring, which identifies anomalies from SSD logs to preemptively detect issues before data loss occurs due to product failure. Lastly, Task Monitoring systematically manages quality-related tasks to ensure zero omissions and promote efficient process handling for various activities related to data centers.
Author Bio:
Youngjune Kang is currently quality engineer and data analyst at the SK hynix. With several years of experience in the quality engineering team, he leverages data analysis techniques to improve quality and enhance efficiency.
For actively applying the latest data science techniques to his work, Youngjune Kang has completed the Machine Learning Engineer program at Seoul National University.
Jiin LEE, TL, SK hynix
Presentation Title:
One Resume: Innovating Talent Management through Integrated AI-Driven Insights
Presentation Abstract:
One Resume is an AI-powered integrated resume system that consolidates scattered talent data into a comprehensive format, enhancing personal talent management. It features four main components: Experience, Performance, Capability, and Private Note, covering various aspects of an individual's professional profile. The system employs advanced AI technologies to create personalized talent summaries and facilitate intent-based resume searches, effectively streamlining talent data management and improving connectivity between employees. By centralizing information and providing AI-enhanced features, One Resume revolutionizes the way organizations handle talent data and fosters more effective professional connections.
Author Bio:
As a junior Data Scientist in the Corporate Center Data Intelligence Team at SK Hynix, I focus on merging AI with people data to drive insights. Since 2021, I've delved into Natural Language Processing, particularly interested in how language influences social phenomena such as hate speech and media commentary. My academic research centered on analyzing the connection between language and social dynamics using textual datasets. At SK Hynix, I narrowed my focus from broad social issues to people analytics, enhancing key decision-making through data analysis on employee retention, recruitment, and corporate culture, including the development of an Intelligent ERP system. Our team aims for business innovation by leveraging data analytics, AI, and digital transformation technologies like RPA. A notable project, the 'Employee Survey Automation System,' implemented a proprietary text summarization model to streamline report creation for over 200 teams, saving around 565 working hours and 60 million won annually.
Eric Anderson, Director of Data Science R&D, Lam Research
Presentation Title:
Human-Machine Collaboration in Semiconductor Device Manufacturing and Process Development
Presentation Abstract:
As the demand for compute continues to increase, the semiconductor industry has been facing challenges in its ability to execute ever greater logic and memory scaling. The transition to three-dimensional logic, first as FinFET transistors and now as nanosheets, is already apparent while we expect a similar transition in DRAM to enable greater densities and power performance properties. This innovation comes at a cost, with substantially increased process complexity and extremely tight unit operation tolerances.
In this paper we will demonstrate the effects of human-machine collaboration and its effect on accelerating process development. By leveraging the key strengths of human process engineers and machine learning, i.e. experience/education and high dimensional optimization respectively, the time to solution on process development can be profoundly accelerated as process complexity increases.
Author Bio:
I head the data science organization within the Semiverse(r) Solutions organization within Lam Research. We develop machine learning solutions for process development, AI/Physical model hybrid models, and deep learning models for a variety of semiconductor specific applications.
This session explores the innovative intersections of AI, data management, and technology scalability, highlighting the transformative impact of strategic resource optimization across industries. A recurring theme is the disentanglement of traditional system architectures, as seen in the separation of compute and storage to enhance query performance in AI analytics, and the development of a Data Eco-System at SK hynix for superior SSD quality management. These strategies underscore the importance of modular, scalable systems capable of addressing the growing demands of modern data centers and AI applications. Additionally, the session delves into the role of AI in centralizing and optimizing talent data management, as exemplified by One Resume's integrated system that harmonizes professional profiles for improved connectivity. Further expanding on the theme of efficiency and scalability, the semiconductor industry's shift towards three-dimensional logic illustrates the necessity of human-machine collaboration to navigate increased process complexity and drive rapid innovation. Together, these presentations offer a comprehensive view of how decoupled architectures and AI-driven solutions are reshaping the landscape of data storage, talent management, and technological advancement.
Open
BMKT-301-1:
Memory Markets
GAMR-1 & 2 (Great America Meeting Rooms, SCCC 2nd Floor)
Track:
Business Strategies & Memory Markets
Organizer + Chairperson:
Jean Bozman, President, Cloud Architects Advisors
Jean S. Bozman is President of Cloud Architects Advisors, a market research and consulting firm focused on hardware and software for enterprise and hybrid multi-cloud computing. She analyzes the markets for servers, storage, and software related to datacenters and cloud infrastructure. A highly-respected IT professional, she has spent many years covering the worldwide markets for operating environments, servers, and server workloads. She was a Research VP at IDC, where she focused on the worldwide markets for servers and server operating systems. She is a frequent conference participant as a speaker, chairperson, and organizer at such events as Flash Memory Summit, OpenStack, and Container World. She is often quoted in a variety of publications including BusinessWeek, Investor’s Business Daily, the Los Angeles Times, CNET, Bloomberg, and Reuters. Ms. Bozman has also been VP/Principal Analyst at Hurwitz and Associates and Sr Product Marketing Manager at Sandisk. She earned a master’s degree from Stanford.
Presenters:
Presentation Session Description:
Jim Handy, General Director, Objective Analysis
Jim Handy of Objective Analysis is a 35-year semiconductor industry executive and a leading industry analyst. Following marketing and design positions at Intel, National Semiconductor, and Infineon he became highly respected as an analyst for his technical depth, accurate forecasts, industry presence, and numerous market reports, articles, white papers, and quotes. He posts blogs at www.TheMemoryGuy.com, and www.TheSSDguy.com.
Praveen Midha, Director, Segment & Technical Marketing, Sandisk
Presentation Title:
A Sprint or Marathon to High-Capacity SSDs
Presentation Abstract:
Aggressive Data Center growth, primarily fueled by AI, has amplified the need for enterprise-grade SSD solutions. Raw data archives and content storage demands continue to accelerate, driving the need for higher capacity and faster storage media. This presentation will focus on how Enterprise SSDs are not only fulfilling the necessary capacity and performance requirements but doing it in a way that’s more wallet friendly.
Attendees will see key market indicators, highlighting how data ingestion, preparation, training, and inferencing requires larger and faster data lakes. Additionally, we will showcase how high-capacity eSSDs are paramount to navigating these challenges successfully, along with a better overall Total Cost Ownership (TCO) than traditional storage media.
Author Bio:
Praveen Midha leads Segment & Technical Marketing at SanDisk for their Enterprise Storage Flash portfolio. Praveen has held leadership roles in technical and product marketing, product management, software engineering to deliver storage and networking infrastructure solutions for Fortune 100 Data Center customers. He is currently focused on AI and its impact on storage architectures.
John Lorenz, Principal Analyst and Director, Yole Group
Presentation Title:
DRAM and HBM Economics
Presentation Abstract:
The current generative AI moment is especially remarkable given the long history of semiconductor device revenues. In this short talk, we will discuss the diverging markets of HBM and non-HBM DRAM, and outline the different economics behind the strategic challenges of today’s DRAM manufacturers.
Author Bio:
John is a principal analyst and director of computing and memory research at Yole Group. He is primarily responsible for covering DRAM technology and markets, having spent more than 20 years in engineering and market intelligence roles in the memory and advanced semiconductor industries.
Brad Warbiany, Director, Technical Marketing, Western Digital
Presentation Title:
The Long Term Case for HDDs in the Data Center
Presentation Abstract:
Data creation & demand for storage are undergoing exponential growth, accelerated by generative AI. Demand placed on data center operators to satisfy this storage demand is intense.
Devices populating a data center include SSD, HDD, and magnetic tape. Each offers specific performance and total cost of ownership (TCO) tradeoffs to meet data center storage needs. The most significant driver of TCO is acquisition cost, measured by $/TB, and there are clear differences with the three. HDDs today make up ~80% of installed storage capacity, with SSD and tape splitting the remainder.
Some suggest SSD will overtake HDD in TCO, and HDD will be excluded from the data center. HDD today has a significant advantage in acquisition cost. With the technological & economic drivers in the production of both technologies, the HDD advantage will be retained for the foreseeable future.
The presentation explores the case supporting that the TCO advantage of HDD persists well into the future. HDD will remain the dominant storage technology in the data center. Applications which must SSD will use SSD, but those that can utilize HDD will continue to do so.
Author Bio:
Brad Warbiany is Director of Technical Marketing. After studying electrical engineering at Purdue University, Brad spent the bulk of his career as a field applications engineer, before transitioning to his current role in 2021. Brad has worked with and supported both SSDs and HDDs for over 20 years, from his previous role at Advantech and continuing during his 17 years with Western Digital.
Josephine Lau, Senior Analyst, Yole Group
Presentation Title:
Memory Market Dynamics – A 2025 Update
Presentation Abstract:
This presentation will explore quantifiable trends in the memory market within the context of the broader semiconductor industry. We will examine the most influential near- and long-term market and technology drivers impacting the two largest revenue segments: DRAM and NAND. By assessing their probabilistic impact, we will provide strategic insights into how these drivers shape industry dynamics. Additionally, the session will include an in-depth analysis of China’s evolving position in the memory landscape and its potential implications on the global market. This discussion is backed by the latest findings from Yole's Status of the Memory Industry 2025 report and Q2 2025 DRAM & NAND Monitors.
Author Bio:
Josephine Lau is a Senior Technology & Market analyst for Memory at Yole Group. As a member of Yole's memory team, she contributes to the analysis of memory markets and technologies. Josephine has 10+ years in memory and storage industry, passed CFA level I and holds a bachelor's degree in business marketing.
In this session, we delve into the evolving landscape of data storage and memory technologies, exploring their critical roles in meeting the burgeoning demands driven by generative AI and data center growth. Across the presentations, a recurring theme is the balance of performance and total cost of ownership (TCO) among storage solutions such as HDD, SSD, and emerging semiconductor technologies. While HDDs currently dominate due to their cost advantage, the rise of enterprise-grade SSDs is highlighted as a key factor in addressing the need for faster and higher-capacity storage. The discussion extends to the memory market, focusing on DRAM and NAND dynamics influenced by global economic and strategic factors, including China's growing influence. Furthermore, the potential for adopting a foundry model in the memory sector, akin to the success seen in CMOS logic, is explored, emphasizing the opportunities and challenges posed by trends like processing in memory (PiM). This session offers a comprehensive overview of how technological advancements and market forces are shaping the future of data storage and memory, providing strategic insights into navigating these complex environments.
PRO
CXLT-301-1:
CXL Infrastructure
Ballroom B (Santa Clara Convention Center, First Floor)
Track:
CXL
Organizer:
Anil Godbole, Sr. CXL Mktg Manager, Intel
Anil Godbole is a CXL Marketing Working Group Co-Chair and Senior Marketing Manager for Intel’s Xeon Product Planning and Marketing Group. His domain is in Memory, Serdes Technologies & Associate Protocols (DDRx, CXL, PCIe, Ethernet, etc.). Previously, he held a position as Design Engineer in CPU-support ASICs, FPGAs.
Presenters:
Presentation Session Description:
Scott Lee, Principal Software Engineer Lead, Microsoft
Presentation Title:
CXL Memory Architecture and Workflows in Windows
Presentation Abstract:
In this presentation, we plan to present the architecture for CXL Memory in Windows and the related workflows including RAS and virtualization.
Author Bio:
Scott Lee is a Principal Software Engineer Manager in Microsoft’s Core OS group with 25+ years of industry experience and 15+ years working in Window’s storage stack. He leads the team that owns the Windows lower storage stack and the Window inbox drivers for NVMe, SATA, UFS, iSCSI and persistent and CXL memory.
Arvind Jagannath, Technology Product Manager, VMware by Broadcom
Presentation Title:
VMware by Broadcom Memory Vision for Real World Applications
Presentation Abstract:
VMware has been on an evolving journey on memory innovations mainly first with persistent memory, then with memory tiering, and is now extending that with CXL. CXL provides an opportunity for VMware (by Broadcom) to further improve on performance, and provide further customer benefits such as TCO reduction, server consolidation, and even disaggregation, with increased capacity and bandwidth to run workloads like Mission critical databases, AI/ML and analytics. Use of accelerators increases the number of use-cases that can be supported with a larger variety of workloads with minimum configuration changes. This session aims to provide real-world application examples using memory tiering.
Author Bio:
Arvind Jagannath works in Product Management at VMware by Broadcom. With over 26 years of experience in the industry working on networking, storage, embedded, and kernel development, he currently leads infrastructure and core platform enablement for vSphere, working most recently on memory technologies, and across the VMware ecosystem of server, IO, and storage partners. Arvind most recently drove platform product management at Cohesity and NetApp. Arvind holds an MBA from Booth and a Bachelors in Computer Science and Engineering from India.
Eishan Mirakhur, Member of Technical Staff, Micron
Presentation Title:
CXL Intelligent Page Placement
Presentation Abstract:
Most existing heterogenous memory systems are either classified as tiering, where hot data is placed in local memory and cold data is placed in remote memory, or interleaving, where data is split between the local and remote memory tiers. Tiering is useful for latency sensitive applications by keeping frequently accessed memory in the lower latency local tier. Interleaving is useful for bandwidth sensitive applications by using the aggregate bandwidth of the local and remote tiers. However, we notice that tiering is just a special case of interleaving where all data is placed in local memory. We have built CXL Intelligent Page Placement, a system that dynamically updates the interleave ratio for an application depending on its memory access characteristics. Additionally, unlike previous memory interleaving systems, CIPP has a mechanism to demote infrequently accessed pages when the local tier is under memory pressure.
Author Bio:
With a keen focus on driving system software, tools, and benchmarking, I specialize in CXL memory and disaggregated memory solutions at Micron. My expertise lies in optimizing CXL memory controllers to meet best-in-class performance requirements. Additionally, a commitment to enabling broad use cases across various workloads to demonstrate the viability of CXL memory in real-world applications.
Harry Kim, CPO, XCENA
Presentation Title:
How CXL computational memory will revolutionize data processing forever.
Presentation Abstract:
With the introduction of CXL, unprecedented memory expansion has become possible. By leveraging CXL’s cache coherence and XCENA’s unified virtual memory technology, data can be processed seamlessly and directly within CXL memory. This enables user-friendly accelerated computing while simultaneously scaling both memory and computing. Additionally, by accommodating hybrid memory media(DRAM+SSD) that deliver DRAM-level performance and transparent memory access while benefiting from the cost and capacity advantages of NAND, we provide storage-class memory optimized for your applications. Experience XCENA’s memory-centric computing technology with a simple demonstration.
Author Bio:
Harry Kim is the CPO and co-founder of XCENA. He is an experienced system software architect with 10 years of SoC expertise. He has developed hardware and software solutions for memory, storage, and processor systems. Before joining XCENA, he worked at SK Hynix as an SSD controller and firmware architect.
This session delves into the transformative impact of Compute Express Link (CXL) in advancing memory architecture and performance across various platforms, including Windows and VMware. The presentations collectively highlight the strategic integration of CXL to enhance memory tiering, virtualization, and resource allocation, enabling significant improvements in server consolidation, total cost of ownership (TCO) reduction, and workload efficiency for applications such as AI/ML and analytics. Central to these discussions is the exploration of memory tiering and interleaving, with innovations like CXL Intelligent Page Placement dynamically optimizing memory access for latency and bandwidth-sensitive applications. The synergy of CXL with technologies like XCENA's unified virtual memory further underscores the potential for seamless, accelerated computing and memory expansion, accommodating hybrid memory solutions that combine DRAM and SSD to achieve unprecedented performance and capacity. This session promises to provide valuable insights into real-world applications of these technologies, showcasing the possibilities for future-ready, scalable computing infrastructures.
PRO
DCTR-301-1:
Enterprise Storage and SSD
Ballroom F (Santa Clara Convention Center, First Floor)
Track:
Data Center Storage and Memory
Chairperson:
Anthony Constantine, Distinguished Member of Technical Staff, Micron Technology
Anthony Constantine is a Distinguished Member of the Technical Staff at Micron Technology responsible for storage standards within the Storage Business Unit. He is involved through authoring or contributing in various industry organizations including NVMe, SNIA, JEDEC, PCI-SIG, and OCP. Anthony has over 24 years of experience in the technology industry with an expertise in memory, storage, physical interfaces, low power technologies, and form factors. He earned a BS in Electrical Engineering from UC Davis.
Organizer:
Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft
Jonathan Hinkle is Senior Director - Azure Memory and Storage Pathfinding at Microsoft. He previously was In Micron's Storage Business Unit, where he investigated new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.
Presenters:
Presentation Session Description:
Gordon Waidhofer, Senior Technical Staff Engineer - Firmware, Microchip Technology
Presentation Title:
Transition from SR-IOV to SIOV (PCISIG) for IO Virtualization
Presentation Abstract:
This presentation will cover the latest advancements in SIOV (Scalable IO Virtualization) virtualization design, the successor to SR-IOV, and how SIOV overcomes previous limitations. We will also discuss the necessary components across software, controllers and firmware to achieve the enhanced scalability and efficiency offered by SIOV.
SR-IOV has been a key virtualization technology for scaling hardware resources in data centers and cloud storage, thereby improving Total Cost of Ownership (TCO), CPU utilization and reducing latency. As virtualization technology continues to evolve, the underlying controller architecture for NVMe® SSDs must adapt accordingly. The transition from SR-IOV to SIOV (Scalable IO Virtualization), the latest standard from PCISIG, aims to further advance the capabilities of virtualization.
Author Bio:
Gordon Waidhofer is part of the architecture team for Flashtec® NVMe SSD Controllers within the Data Center Solutions Business Unit at Microchip Technology Inc. Gordon has been working with SSD for 15 years, with decades of block, file, and networking storage technology experience. He focuses on emerging storage standards and initiatives including virtualization, AI enablement, and accelerating time to deployment of ever improving components.
Dheeraj Skandakumar Nair, Senior Engineer, Hardware Development Engineering, Sandisk Technologies, Inc
Presentation Title:
Efficient Management of NVMe SSDs using I3C
Presentation Abstract:
Managing SSDs efficiently is becoming more important as data centers grow and storage demands increase. The NVMe Management Interface (MI) has been essential for monitoring and controlling SSDs, but traditional communication methods like I2C and SMBus come with speed and scalability limitations.
This talk introduces NVMe MI over I3C, a faster and more efficient way to handle SSD management. We’ll break down how I3C improves communication, provides more flexibility, and enables better real-time monitoring. Through real-world examples and performance comparisons, we’ll explore why shifting to I3C is a game-changer for modern storage systems. Whether you’re new to SSD management or already familiar with NVMe MI, this session will provide practical insights into the future of storage technology.
Author Bio:
I am a Senior Engineer at Western Digital, specializing in embedded systems, hardware design,validation, and microcontroller-based solutions for SSD management and debugging. I have played a key role in developing PCIe Gen5 Debug Infrastructure, implementing communication protocols like I3C and USB HID, and optimizing power management IC validation. Recognized for my contributions to embedded firmware development and automation, I have successfully led validation efforts and streamlined test processes. I hold a degree in Masters Degree in Computer Engineering from San Jose State University. I also multiple publications in the field of machine learning.
Mahinder Saluja, Director of Technology and Storage Pathfinding, KIOXIA America, Inc.
Presentation Title:
Offloading Storage Compute Tasks from DPU to SSD Can Free Compute Resources
Presentation Abstract:
A Data Processing Unit (DPU) is becoming an essential component of modern data centers by offloading and accelerating software-defined networking, storage, security, and management functions. However, as network speeds increase, maintaining line-rate throughput becomes increasingly challenging. By collaborating with SSD to offload storage compute tasks from DPU to SSD, can free up resources to focus on higher level storage networking tasks, preventing potential bottlenecks.
Author Bio:
Mahinder has 20+ years of engineering leadership in innovative storage technologies development, building teams and product delivery. Currently Mahinder is one of the main leads for SSD technology strategy at KIOXIA America, Inc., collaborating with industry experts. He has several pending storage related patents.
Pinaki Chanda, Director of Software Engineering, MaxLinear
Presentation Title:
Optimizing Data Compression: Enhancing Efficiency of Delayed Match Windowing
Presentation Abstract:
In dictionary-based lossless data compression algorithms, such as GZIP, Deflate, XP10 "lazy matching" improves compression by delaying the selection of matches. After finding a match of length N, the compressor searches for a longer match starting from the next input symbol. If a longer match is found, the previous match is replaced by a single literal, and the longer match is emitted. If no longer match is found, the original match is emitted, and the compressor advances N bytes. The "Delayed Match Window" (DMW) is a runtime parameter that controls how often the algorithm delays match selection.
Increasing the lengths of the DMW has enabled higher compression ratios, leading to more effective storage capacity. However, this increase in data reduction often results in higher compression latencies and computational workload with increase in DMW length.
This proposal introduces a method to mitigate the increase in compression latency and computational workload introduced by lazy matching while preserving the bit-exactness of the compressed data stream. The proposed method significantly reduces latency compared to existing dictionary-based data compression method using lazy matching.
Author Bio:
Pinaki Chanda is an experienced engineering leader with extensive experience in developing advanced technology solutions, particularly in data compression, storage systems, and video transport. He is currently serving as the Director of Software Engineering at MaxLinear, where he leads the architecture and development of Panther family of storage accelerator SoCs and software. Additionally, he worked on Remote PHY SoCs for distributed access architecture, HD DVRs and set-top box SoCs, enabling major US cable and satellite broadcasters.
Pinaki holds a Master of Engineering in Electrical Communication Engineering from Indian Institute of Science.
In an era where data centers are the backbone of digital infrastructure, optimizing storage and processing capabilities has never been more critical. This session explores cutting-edge advancements in SSD management, data processing, virtualization, and data compression. The integration of NVMe MI over I3C redefines SSD management, addressing the speed and scalability limitations of traditional methods to enhance real-time monitoring and control. Complementing this, the synergy between Data Processing Units (DPUs) and SSDs is explored, highlighting how offloading storage tasks to SSDs can alleviate potential network bottlenecks and improve efficiency. As virtualization technology continues to evolve, the transition from SR-IOV to SIOV promises enhanced scalability and resource allocation, integral for modern data centers. Finally, innovations in dictionary-based data compression, specifically with delayed match window adjustments, offer solutions to improve storage capacity while minimizing latency and computational demands. Together, these presentations underscore a common theme of enhancing efficiency and performance in data center operations, providing invaluable insights for professionals navigating the future of storage technology.
PRO
DRAM-301-1:
3D DRAM Technology Now and Future
Ballroom E (Santa Clara Convention Center, First Floor)
Track:
DRAM
Organizer + Chairperson:
Ju Jin An, Senior Technical Staff Member, IBM
Ju Jin An is a Senior Technical Staff Member in IBM's Infrastructure Supply Chain Organization. Ju Jin has a background in silicon fabrication process R&D and manufacturing process integration through 20 years of career in the semiconductor industry. She is responsible for enabling memory sub-system for IBM power and z system. She holds a MS/Ph.D. degree in Chemical Engineering from MIT and a BS from Seoul National University.
Presenters:
Presentation Session Description:
Kevin Yee, Sr. Director of IP and Ecosystem Marketing, Samsung Foundry, Samsung Foundry
Presentation Title:
Unleashing the Performance of AI Training with HBM4
Presentation Abstract:
AI training models are growing in both size and sophistication at a breathtaking rate, requiring ever greater bandwidth and capacity. With its unique 2.5D/3D architecture, HBM4 can deliver Terabytes per second of bandwidth and unprecedented capacity in an extremely compact form factor. Join Kevin Yee from Samsung and Nidish Kamath from Rambus discuss the design considerations of HBM4 memory subsystems (PHY, Memory Controller, and Packaging) in next-generation AI SoCs.
Author Bio:
Kevin Yee is Sr. Director of IP and Ecosystem Marketing at Samsung Foundry, responsible for driving strategic partners for IP enablement and the SoC ecosystem. With over 30 years in the semiconductor industry, he has served a variety of senior management roles in R&D engineering, product planning, sales, marketing and business development in system, semiconductor, FGPA, IP/VIP and EDA companies. Kevin's background includes system/ASIC design, FPGA architecture, IP development and he holds several patents in design architecture. Kevin is actively involved in the HPC/AI, Automotive and Chiplet space as well as with industry standards organizations such as UCIe, OCP, CXL, JEDEC, PCI-SIG, USB I/F and MIPI, driving the latest in industry standards and technologies. He holds a Bachelor of Science in Electrical Engineering from the University of California.
Tom Hsu, Analyst, TrendForce
Presentation Title:
Increasing Bandwidth and Stacking Layer to Boost Development in HBM Process Tech
Presentation Abstract:
The development of HBM is set to accelerate as stacking layers increase from 4hi to configurations of 8hi, 12hi, 16hi, and even 20hi. This presentation examines the advancements in HBM process technologies, focusing on methods such as TSV, TC-NCF, MR-MUF, and hybrid bonding. Key process steps, including temporary bonding, etching, grinding, and thermal compression molding, are critical for successful production. Additionally, as the gap between stacking layers decreases, challenges arise regarding the liquidity of underfill materials, necessitating innovations in equipment technology.
The bit density of each HBM chip is being enhanced through improved mono die density and stacking layers. Furthermore, advancements in 2.5D packaging, illustrated by NVIDIA's Hopper, Blackwell, and Rubin platforms, show an increase in the number of HBM chips per AI chip from six to eight and potentially twelve. The adoption of FOPLP and the exploration of glass core substrates and interposers will play a pivotal role in the long-term evolution of HBM technology, driving further growth in the market.
Author Bio:
Tom brings nine years of industry research experience from his tenure at KGI Securities Investment Consulting, where he specialized in the petrochemical sector for six years and the memory sector for three years. Since joining TrendForce, Tom has focused on researching the DRAM industry, including PC DRAM and HBM, as well as advanced packaging technologies such as FOPLP. Additionally, he possesses valuable experience in stock research and promotional activities, further enhancing his comprehensive expertise in the industry.
Suyash Walkunde, Staff Engineer, Samsung Semiconductor India
Presentation Title:
Thermal, Latency & Power Characterization of High Bandwidth Memory(HBM3)
Presentation Abstract:
With Semiconductor fabrication and Generative AI advancement the need for faster and denser memory subsystem has been raised in recent times. High Bandwidth memory provides the advantage of wide bandwidth (819.2 Gbps) with advance fabrication methods. Likewise, the need for verifying the HBM for its features and most importantly Thermal, Latency and Power characterization holds the equal importance.
In this talk, we will explain the architecture of HBM and how the different bus masters can be used to do the characterization, for latency, primarily the different data patterns and memory controller features such as refresh, bank management and memory reordering will be used. Thermal and Power analysis will be done alongside different bus masters stressing HBM with targeted addresses and data patterns (PRBS16, 32, random address, user defined data). The performance graphs and tables will be explained for minimal HBM latency with optimal power and thermal consumption.
Author Bio:
I am working on High Bandwidth Memory 3, 3E. Profiling and benchmarking these memories consume most of my work activities. Along with Memory I also work with DMA and Custom DMA for accelerating the AI applications with HBM. I have Completed my bachelor's in engineering From Maharashtra Institute of Engineering (MIT).
Nidish Kamath, Director - Product Management, Rambus
Presentation Title:
Unleashing the Performance of AI Training with HBM4
Presentation Abstract:
AI training models are growing in both size and sophistication at a breathtaking rate, requiring ever greater bandwidth and capacity. With its unique 2.5D/3D architecture, HBM4 can deliver Terabytes per second of bandwidth and unprecedented capacity in an extremely compact form factor. Join Kevin Yee from Samsung and Nidish Kamath from Rambus discuss the design considerations of HBM4 memory subsystems (PHY, Memory Controller, and Packaging) in next-generation AI SoCs.
Author Bio:
Nidish Kamath is the Director of Product Management for Memory Interface IP at Rambus. He previously held marketing and product management roles at AMD, Kioxia (formerly Toshiba Memory), Avalanche Technologies, Brocade and Qualcomm, where he worked on computational storage, SmartNICs and GPU cluster networking solutions. He has served in various standards and industry associations such as SNIA, Center for Open Source Software (CROSS), CXL Consortium, UEC and JEDEC.
Benjamin Vincent, Director Engineering, Lam Research
Presentation Title:
Nanosheet-based 3D-DRAM architecture
Presentation Abstract:
After the introduction of 3D-NAND memory technologies during the last decade, the logic industry has also been preparing its own transition to three-dimensional devices through the upcoming introduction of nanosheet transistors. This same transition is expected to occur in DRAM memory, taking DRAM into 3 dimensions. Current DRAM architecture, conventionally built using high aspect ratio capacitors on top of FinFET transistors, becomes complex to develop and manufacture when it is designed and processed laterally.
This paper introduces a new DRAM architectural concept, developed using SEMulator3D® process simulation. The new architecture supports the development of a 3D-DRAM device, by incorporating Nanosheet transistors and innovative staircase patterning techniques into the design. The process flow highlighted in this work is CMOS-compatible, and uses conventional materials currently being used in the advanced semiconductor industry.
Author Bio:
Benjamin Vincent is Director Engineering of the global semiconductor process and integration (SP&I) team at Lam Research company. He has 20 years of experience in semiconductor process engineering, including PhD degree obtained in CEA/Leti (France) followed by positions at imec (Belgium) as an epitaxy scientist in the advanced logic area, and at intel in Santa Clara, CA, as process/design integration engineer and manager. Benjamin Vincent joined Lam Research in July 2017, and is currently leading the global application team for Lam Research's SEMulator3D® solution.
This session explores the forefront of memory technology advancements with a focus on High Bandwidth Memory (HBM) and its pivotal role in meeting the increasing demands of AI and semiconductor applications. The presentations converge on the innovative strides being made in HBM, emphasizing the transition to more complex stacking configurations—8hi to potentially 20hi—enabled by cutting-edge techniques like TSV and hybrid bonding. With an eye on enhancing bit density and packaging efficiency, the talks highlight the criticality of thermal, latency, and power characterization, underscoring the importance of architecture in optimizing performance. The discussions also delve into the implications of 2.5D and 3D architectures, especially in the context of AI SoCs, where HBM4 is poised to redefine bandwidth capabilities. Complementary to these developments is the evolution in DRAM technology, as it embraces three-dimensional designs through nanosheet transistors and innovative patterning strategies, promising further integration and efficiency. Attendees will gain a comprehensive understanding of how these advancements collectively drive the future of memory technologies, addressing the needs of burgeoning AI models and semiconductor innovations.
Open
INDA-301-1:
UCI Express
Ballroom D (Santa Clara Convention Center, First Floor)
Track:
Industry Associations
Presenters:
Presentation Session Description:
Brian Rea, UCIe Marketing Work Group Chair, UCIe Consortium
Presentation Title:
UCIe Consortium: A Progress Report on the Open Chiplet Ecosystem
Presentation Abstract:
There are many drivers for on-package chiplets. As the die size increases to meet the growing performance demands, designs are running up against the die reticle limit. On-package integration of chiplets enables a fast and cost-effective way to provide bespoke solutions for memory and storage.
UCIe™ (Universal Chiplet Interconnect Express™) is an open industry standard interconnect offering high-bandwidth, low-latency, power-efficient, and cost-effective on-package connectivity between chiplets. UCIe provides the ability to package dies from different sources, designs, and various packaging technologies. Additionally, the UCIe specification outlines a comprehensive solution stack – including software, manageability, security, test and debug – encouraging interoperability between chiplet solutions.
This presentation will highlight the benefits of UCIe and chiplet technology and provide an update on the status of the UCIe Consortium.
Author Bio:
Brian Rea is a senior technologist in the industry initiative and technology enabling team at Intel and is the Marketing Working Group Co-Chair for the UCIe Consortium. Brian has held engineering, marketing, and strategic planning roles bringing products with new technologies to market including USB, Gigabit Ethernet, PCIe, and CXL. His passion is working with customers and partners to enable ecosystem innovations in silicon, hardware, and software. Brian holds an MBA from the University of Washington and a BSEE from the University of Texas at Austin.
Swadesh Choudhary, Principal Engineer/UCIe Consortium Protocol WG Co-Chair, Intel
Presentation Title:
UCIe Consortium: A Progress Report on the Open Chiplet Ecosystem
Presentation Abstract:
There are many drivers for on-package chiplets. As the die size increases to meet the growing performance demands, designs are running up against the die reticle limit. On-package integration of chiplets enables a fast and cost-effective way to provide bespoke solutions for memory and storage.
UCIe™ (Universal Chiplet Interconnect Express™) is an open industry standard interconnect offering high-bandwidth, low-latency, power-efficient, and cost-effective on-package connectivity between chiplets. UCIe provides the ability to package dies from different sources, designs, and various packaging technologies. Additionally, the UCIe specification outlines a comprehensive solution stack – including software, manageability, security, test and debug – encouraging interoperability between chiplet solutions.
This presentation will highlight the benefits of UCIe and chiplet technology and provide an update on the status of the UCIe Consortium.
Author Bio:
Swadesh Choudhary is a Principal Engineer at Intel and is the UCIe Consortium Protocol Work Group Co-Chair. Choudhary’s research interests include PCI-Express, CXL, Universal Chiplet Interconnect Express (UCIe), and their standardization and implementation. Choudhary received his M.S. degree in Electrical and Electronics Engineering from Stanford University.
In a rapidly evolving semiconductor landscape, the integration of chiplets on packages emerges as a pivotal innovation to overcome die size constraints and meet increasing performance demands. Key presentations explore the role of chiplets in facilitating bespoke solutions for memory and storage, emphasizing their ability to bypass the die reticle limit efficiently. Central to this integration is the Universal Chiplet Interconnect Express (UCIe™), an open industry standard that ensures high-bandwidth, low-latency, and power-efficient connectivity between chiplets. UCIe fosters interoperability across diverse designs and packaging technologies, supported by a robust solution stack encompassing software, manageability, security, and testing protocols. The session underscores the strategic advantages of adopting chiplet technology, providing insights into the latest developments from the UCIe Consortium and its efforts to streamline chiplet integration across the industry.
PRO
NETC-301-1:
Networks and Links 1: Foundations
Ballroom C (Santa Clara Convention Center, First Floor)
Track:
Networks and Connections
Organizer:
Paul Borrill, Founder and CEO, DAEDAELUS
Paul Borrill is founder and CEO of DÆDÆLUS and is a leading industry expert on the foundations of resilient network and storage infrastructures
Presenters:
Presentation Session Description:
Pankaj Goel, Associate Director, Siemens EDA
Presentation Title:
Evolving UALink and UEC as the Gold Standard for Accelerator Connectivity in AI
Presentation Abstract:
As AI workloads scale exponentially, the need for high-performance, low-latency interconnect solutions becomes critical. Traditional architectures struggle to keep pace with the massive data movement and compute demands of modern AI accelerators. UALink and UEC emerge as transformative technologies, optimizing accelerator-to-accelerator and multi accelerator Pods-to-multi Pods connectivity with high bandwidth, low latency, and efficient scalability.
Furthermore, the introduction of 200G UALink and 128G UALink leverages the existing PHY IP infrastructure, ensuring compatibility while creating a widely accepted and deployable solution. By utilizing established physical layer technologies, these standards enable seamless integration, reducing development costs and accelerating adoption across the industry.
This presentation will explore the evolution of UALink and UEC, their technical advantages, and their role in setting a gold standard for AI accelerator interconnects, addressing the future demands of AI-driven computing.
Author Bio:
I am an Associate Director at SIEMENS EDA, responsible for managing the Memory and Network VIP portfolio. With 19 years of industry experience in VIP development, worked on a wide range of VIPs, including AMBA, PCIe, Memory, Flash, Ethernet, and more.
Gautam Singampalli, Product Marketing Director, Cadence Design Systems
Presentation Title:
Maximizing AI Accelerator Performance with UALink: Advanced Features and Techniques
Presentation Abstract:
UALink, the de-facto standard for AI accelerator interconnects, plays a pivotal role in enabling this low-latency, high-bandwidth communication between accelerators.
UALink’s features like packet compression boost bandwidth utilization from 88% to 95%. Advanced techniques such as 1-way and 2-way FEC interleaving and efficient packing of UPLI transactions to TL-Flit reduce controller latency. Cadence's additional features like an interrupt-based message handling and UART/APB firmware-controlled responses using provide flexibility. We include FW components for integration with customer applications, with the Flit-play error injection, debug and Flit-capture for storing received flits for field debug. Flexibility in selecting ports optimizes core area efficiency, beneficial for large UALink stations. The 1-way interleave in the PCS improves latency, and internal buffers are shared across ports to optimize buffering.
By leveraging UALink's unique features and advanced techniques, Cadence IP significantly boosts bandwidth utilization, reduces latency, and provides flexible, efficient solutions for AI applications, enhancing overall customer experience.
Author Bio:
Gautam Singampalli is a Director of Product Marketing at Cadence Design Systems, where he leads marketing strategy for silicon IP solutions based on industry standards like PCIe, CXL, UALink, UEC and Ethernet. With close to two decades of experience spanning engineering and technical sales at Intel and Cadence, Gautam has played a key role in driving innovation and revenue growth across advanced semiconductor technologies.
Annie Liao, Product Management Director, Marvell Technology
Presentation Title:
Assemble compute, storage and memory resources through active PCIe/CXL cabling.
Presentation Abstract:
As more and more PCIe Gen 6 platforms and devices continue debut this year, industry is shifting to PCIe 6-based accelerated infrastructure. With various resources requirement for different application, building the composable infrastructure for flexible resource allocation is highly desired. Marvell will present PCIe 6 / CXL 3 based active cable solution that enables PCIe devices working together as there were physically attached. Marvell's PCIe 7 SerDes solution also pave the way for future PCIe 7 connectivity.
Author Bio:
Annie Liao, Product Management Director of Marvell Technology, is currently the product line owner of Marvell PCIe Retimer portfolio. Annie works closely with customers and ecosystem partners on the adoption of PCIe 6 technology and enablement of future PCIe 7, including but not limited to AI accelerator, compute, storage and CXL devices.
Santhosh Thodupunoori, Sr. Principal Engg and Dir of Engg., Auradine Inc.
Presentation Title:
Ultra Accelerator Link (UAL) Reference Implementation
Presentation Abstract:
The UAL provides an open standard to build scale-up networks for AI/ML and HPC workloads. In this session, we will present a software reference model paired with a High Bandwidth Domain simulation, delivering a cycle-based, bit-accurate view of the UAL controller’s functions in GPUs and switches. We will show the data flow from read, write, and atomic transactions down to the level of 64-byte flits and bits traversing the system.
Key Takeaways:
1. Understanding UAL: Discover how UAL serves as an open, high-performance alternative to proprietary solutions like NVLink, driving innovation in AI/ML and HPC applications.
2. Detailed Internals: Gain a deep understanding of UAL’s architecture by exploring its core components and learning how to extract and analyze flit traces from the reference implementation.
3. Building an Open Ecosystem: Learn how UAL fosters an open, collaborative AI ecosystem by offering transparent, interoperable networking solutions.
4. Future Directions: Get insights into the evolving landscape of high-performance networking and the future innovations in UAL and scale-up networking
Author Bio:
Santhosh Thodupunoori is a Senior Principal Engineer and Director of Engineering for AI products at Auradine, where he spearheads software development and leads the design of scalable systems, including Ultra Accelerator Link-based scale-up networking and UEC-based scale-out networking solutions. With extensive experience at industry giants like Meta and Cisco as well as innovative startups such as Insieme and Wichorus, Santhosh brings deep expertise in engineering leadership and management. A true generalist, he has driven advances in machine learning infrastructure, advertising technology, distributed systems, networking, and overall infrastructure engineering. Santhosh holds a Bachelor’s in Electrical Engineering from IIT Chennai and a Master’s in Computer Engineering from Purdue University.
Sahas Munamala, Protocol Engineer, OCP Open Atomic Ethernet
Presentation Title:
Open Atomic Ethernet: Making the world safe for Transactions
Presentation Abstract:
As the world moves towards chiplet-based designs, disaggregated computing, and endlessly expanding data workloads, networking is becoming more integral to system design than ever before. Yet despite its ubiquity, Ethernet is treated as an external I/O resource rather than a core component of computer architectures. There is a growing need to reconsider networking as a first-class citizen -- both in hardware and Software. An open, non-proprietary specification from API to bits on the wire. This presentation will include the major technical innovations in Atomic Ethernet, the principles, protocols and implementations. Our goal is bring together the leading voices in Ethernet evolution, chiplet interconnect standards (UCIe, HBM, UA-Link, NV-Link, PCIe, UCIe), and open source communities (OCP, SNIA, IEEE, Linux). The presentation continues the dialogue that began at the Ethernet 2025 Workshop at the Chiplet Summit and the OCP Open Atomic Ethernet initiative, exploring how a unified Ethernet approach can underpin the next 50 years of memory, storage, and computation..
Author Bio:
Sahas Munamala is a new graduate from the University of Illinois Urbana Champaign majored in Computer Engineering. He has a strong background in software development and engineering from years of projects and teams. With a passion for innovation and problem-solving, he has made significant contributions to various open source projects and organizations.
Sahas has worked at Amazon, enhancing an interface for Alexa Shopping and adding new features to the AWS Serverless backend. He also started a Math/CS online tutoring service, reaching 60 students and professionals, and led online courses in Python and HTML/CSS/JS. He also has interests in embedded systems, Robotics, IoT, computer and network security, and computer vision. In his final year, he ported an AI accelerator to run 20 times faster on an FPGA compared to a numpy implementation. At DÆDÆLUS, he uses his experience with Altera and Xilinx FPGAs to help develop the next generation of network protocols.
In the rapidly evolving landscape of computer architecture, this session delves into the transformative potential of emerging technologies such as Data Processing Units (DPUs), PCIe advancements, Unified Addressing Layer (UAL), and Atomic Ethernet. Presentations will explore the integration of DPUs in storage systems, highlighting their role in optimizing data management and enhancing scalability. This is complemented by discussions on PCIe 6 and 7 technologies, which are paving the way for more flexible and accelerated infrastructures, ultimately supporting diverse application needs. The session will also showcase UAL as an open standard for AI/ML and HPC workloads, emphasizing its role in fostering an open ecosystem through transparent and interoperable networking solutions. Lastly, the dialogue on Atomic Ethernet will underscore the shift towards viewing networking as a core component of system design, advocating for open specifications to support the next generation of computing. Together, these presentations offer a comprehensive view of the innovations driving the future of high-performance computing and networking.
PRO
OPSW-301-1:
Storage Ecosystem for AI
Ballroom G (Santa Clara Convention Center, First Floor)
Track:
Open Source Software
Organizer + Chairperson:
Javier Gonzalez, Principal Engineer, Samsung
I lead Samsung Semiconductor's Global Open-ecoSystem Team (GOST - https://tinyurl.com/SamsungGOST), where I take care of our ecosystem activities and manage a distributed team of highly talented engineers. This includes defining our vision, strategy, internal / external communication, and day-to-day execution. I am also the founder and site manager for Samsung Semiconductor Denmark Research (SSDR) - Samsung’s Memory Solutions first R&D center in Europe and fifth worldwide.
Presenters:
Presentation Session Description:
David Flynn, CEO, Hammerspace
Presentation Title:
[Accelerated I/O for AI] How Linux Is Used to Accelerate Workloads in the World’s Largest AI Environments
Presentation Abstract:
A key challenge for accelerating AI workloads is how to overcome bottlenecks that limit I/O to GPUs. Vendors propose a variety of solutions, from caching schemes, to proprietary client software, to custom kernel-based agents and exotic networking.
But within all standard Linux distributions is contained a standards-based parallel file system in pNFS v4.2 with Flex Files that is being used in some of the world’s largest AI environments to accelerate I/O to GPU clusters without any alteration to existing servers. As a standards-based solution, no custom client software is required, and it supports any hardware and networking technology.
This session will unpack these innovations within standard Linux that are being used at extreme scales to accelerate I/O to GPUs, and show real-world examples of how it scales linearly to many thousands of GPUs using commodity hardware.
The session will also show how this standards-based approach can be extended with innovation from Hammerspace to activate local NVMe on GPU servers, to create a protected Tier 0 that exceeds the performance of any external NVMe storage, without the network overhead, power, and added expense needed by such systems.
Author Bio:
Hammerspace founder and Chief Executive Officer David Flynn is a recognized leader in IT innovation who has been architecting disruptive computing platforms since his early work in supercomputing and Linux systems.
David pioneered the use of flash for enterprise application acceleration as founder and former CEO of Fusion-io, which was acquired by Sandisk in 2014. He served as Fusion-io President and CEO until May 2013 and board member until July 2013.
Previously, David served as Chief-Architect at Linux Networx where he was instrumental in the creation of the OpenFabrics stack and designed several of the world’s largest supercomputers leveraging Linux clustering, InfiniBand, RDMA-based technologies.
David holds more than 100 patents in areas across web browser technologies, mobile device management, network switching and protocols to distributed storage systems. He earned a bachelor’s degree in computer science at Brigham Young University and serves on boards for several organizations and startup companies.
Simon Lund, Staff Software Enginer, Samsung
Presentation Title:
[Accelerated I/O for AI] Feeding the Beast: Bridging NVMe Storage and GPUs While Preserving File Semantic
Presentation Abstract:
We present our work on enabling direct, peer-to-peer (P2P) access between
GPUs and NVMe storage while preserving file-semantic abstractions. Existing
approaches either drop file semantics to achieve P2P access, forcing
applications to handle raw storage, or retain file semantics but introduce
performance overhead due to host CPU and OS-managed file system logic.
Our approach avoids these trade-offs by maintaining the file-based model for
data import while enabling efficient direct GPU access. Instead of discarding
file semantics, we provide a lightweight file-system data-access library
that allows applications to use familiar abstractions without the usual CPU
and OS overhead. Using open-source tools, libraries, and drivers, we ensure
seamless integration with existing workflows while delivering low-latency,
high-performance storage access. This makes direct GPU-NVMe access both
practical and efficient for accelerator-driven workloads.
Author Bio:
As a Staff Engineer and Head of the Systems Advancement and Integration group at
Samsung, I focus on reducing the cognitive load for developers adopting emerging
storage interfaces, currently materialized in the xNVMe project. My work
revolves around bridging compute and storage with minimal overhead, enabling
efficient data access and processing. Previously, I worked at CNEX Labs, where I
designed and implemented liblightnvm, the Open-Channel SSD User Space Library.
I hold a Ph.D. from the University of Copenhagen, where my research focused
on high-performance backends for array-oriented programming on next-generation
processing units. I have delivered talks on programming languages, interpreters,
and compiler design for HPC, as well as storage technologies, at events such
as the SNIA Storage Developer Conference and Linux Vault. My work consistently
bridges high-level abstractions with low-level control while assessing the
trade-offs of doing so.
Specialties: Software Development, API Design, NVMe, Open-Channel SSDs, data
parallelism, array programming, multi-core processing, and accelerators.
Vikram Sharma Mailthody, Sr Research Scientist, NVIDIA
Presentation Title:
[Accelerated I/O for AI] Optimizing Data Delivery for GPU-Driven AI: Advancing Memory and Storage Archite
Presentation Abstract:
We have witnessed rapid data center growth as industry players race to develop AI agents and inference applications. These evolving workloads demand exceptional compute throughput, scalability, and rapid data access. However, efficiently delivering data from memory and storage systems like object stores and file systems to GPU compute engines has become a critical challenge for a subset of apps. The ability to address this bottleneck will be pivotal in meeting the performance requirements of next-generation AI applications. This talk will explore the key factors driving transformations in memory and storage architectures, mapping them to specific usage models and application domains. We will highlight our breakthrough advancements in accelerating the system software stack that enables us to unlock new possibilities for optimizing GPU-driven generative AI workloads at scale.
Author Bio:
Vikram Sharma Mailthody is a Sr Research Scientist in NVIDIA Research studying emerging datacenter workloads and building future NVIDIA systems. He works on distributed inference at scale, vector databases and agentic workflows. Dr. Mailthody co-leads Storage-next industry wide initiative with CJ Newburn and is co-architect of NVIDIA Dynamo.
In the rapidly evolving landscape of AI workloads, optimizing data access to GPUs has emerged as a critical challenge, with innovative solutions being explored across various fronts. Common themes from the presentations reveal a focus on overcoming I/O bottlenecks and enhancing performance without sacrificing existing infrastructures or introducing significant overhead. A notable strategy involves utilizing the standards-based pNFS v4.2 within Linux distributions to enhance I/O to large-scale GPU clusters, effectively leveraging commodity hardware without necessitating custom solutions. Complementing this, efforts to enable direct GPU to NVMe storage access while preserving file semantics underscore the importance of maintaining familiar abstractions for developers, thereby facilitating seamless integration into existing workflows. Additionally, the session will delve into breakthrough advancements in system software architectures, which are critical to scaling AI applications by optimizing data pathways between memory, storage, and GPU compute engines. These collective innovations promise to unlock the potential of next-generation AI workloads, addressing the challenges of scalability and performance in data-intensive environments.
09:35 AM to 09:45 AM
Open
BRK:
Thursday AM Refreshment Break
Main Lobby/Great America Lobby (SCCC, First Floor/Great America Meeting Rooms, Second Floor)
Track:
General Events
General Event Description:
Description Not Available
09:45 AM to 10:50 AM
PRO
AIML-302-1:
Storage for AI: Markets and Technologies
Ballroom A (Santa Clara Convention Center, First Floor)
Track:
AI and ML Applications
Chairperson:
Sarah Peach, Senior Director, Product Management, Samsung Semiconductor
Sarah is responsible for new product introduction in Samsung’s Memory business, with focus on launching new business models. She has also managed go-to-market for computational storage and Samsung’s IoT hardware and cloud platform. Previously while at Siemens she was responsible for turning early stage innovations from startups into viable business opportunities for Siemens’ industrial business units. Sarah has also directed business development at startups. She started her career in Germany at BASF. Sarah holds a Bachelor’s degree from Oxford and a Ph.D. from Cornell, both in physics.
Organizer:
David McIntyre, Director Product Planning, Samsung Electronics
David McIntyre focuses on computational storage acceleration solutions development and strategic business enablement for cloud to edge applications including AI inference/video analytics, database processing and blockchain networks. He has held senior management positions with IBM, Samsung, Xilinx, Intel (formerly Altera) and at Silicon Valley startups. He has consulted for institutional investors including Fidelity, Goldman Sachs and UBS. David is a frequent presenter and chairperson at the Flash Memory Summit and other technical conferences including SNIA.
Presenters:
Presentation Session Description:
Tam Do, Technical Staff Engineer-Product Marketing, Microchip Data Center Solutions
Presentation Title:
PCIe® Switch Implementation in an AI environment
Presentation Abstract:
PCIe® switches have been the key bridging interface between CPUs and many other endpoints.
The PCIe timeline remains largely driven by accelerators for ML and AI applications. The feature set of PCIe switches play a key role in these use cases. This paper will dive into the details on implementation of PCIe fanout switches in an AI data center environment.
In AI/ML use cases, a large number of GPU cluster topologies are needed which can be decided by the size of the interconnecting switch. Moving to a high-lane count switch allows the switch to handle use cases that the previous generations could not. This includes:
- 8:1 GPU:CPU ratio models
- Lower (6:1, 4:1) GPU:CPU ratio models with full dual host link Networking/Storage connections
- 16:1 and 16:2 GPU:CPU ratio models with x8 connections
While most accelerators use a proprietary interconnect to communicate with their cluster, there are use cases where a x16 crosslink between switches will be useful. Some scenarios where accelerator devices will use PCIe to communicate with peers are as follows:
• Heterogeneous Accelerators and Low cost accelerators
Author Bio:
Technical Marketing Professional and Application Engineering Management with proven expertise in IoT, consumer mobile, data center, and video products.
Bryan Ao, Analyst, TrendForce
Presentation Title:
The Storage Demands of the AI Wave: New Opportunities and Challenges for NAND
Presentation Abstract:
The NAND Flash market is undergoing significant transformation fueled by the AI surge, creating a spectrum of opportunities and challenges for manufacturers and consumers alike. This analysis delves into the increasing need for high-performance SSDs driven by AI training and inference workloads, as well as the demands of edge AI applications necessitating rapid data transfer and storage capabilities. We will explore the technological advancements required to keep pace with AI's escalating performance requirements while examining the risks of oversupply in a highly competitive market. Our presentation will provide a detailed overview of supply and demand dynamics, pricing trends, and the strategies employed by leading suppliers to navigate this evolving landscape. We will also discuss capacity adjustments and growth projections for the NAND market through 2025 and beyond, highlighting key strategic insights for industry stakeholders.
Author Bio:
• TrendForce Research Manager Bryan Ao focuses on demand trends of NAND Flash storage solutions used by server OEMs, data center operators, and AI or edge computing service provider. He previously worked in an electronic component distributor specializing in mobile device memory solutions and SSD controller ICs.
Thibault Grossi, Yole group, Yole Group
Presentation Title:
Storage Technology and Market Trends: Navigating the Future of Enterprise SSDs
Presentation Abstract:
The rapid growth of generative AI and data-centric workloads is reshaping the storage landscape, driving increasing demand for high-performance and high capacity enterprise SSDs. This presentation will explore the latest technology and market trends influencing the evolution of enterprise SSDs, examining how advancements in NAND technology are addressing the need for speed, efficiency, and scalability. Additionally, we will provide a forward-looking perspective on storage-class memory (SCM) technologies that hold the potential to disrupt the market in the long term. Attendees will gain a comprehensive understanding of the strategic opportunities and challenges facing the storage industry, positioning them to better navigate the next wave of innovation.
Author Bio:
Thibault Grossi is a Senior Technology & Market Analyst at Yole Intelligence, part of Yole Group, working with the Semiconductor & Software division. He is a member of Yole’s memory team and is engaged in the development of technology and market monitors and analyses.
Ryan Meredith, Director, Storage Solutions Architecture, Micron Technology
Presentation Title:
Real-world AI workloads need fast, efficient storage
Presentation Abstract:
As AI accelerators advance, traditionally compute bound AI workloads are becoming storage dependent. Workloads are also evolving to require massive amounts of data and traditional storage simply cannot keep up. In this session we'll examine storage focused AI workloads relevant to fast local SSDs and workloads that require massive amounts of storage. We'll examine performance and power efficiency of Micron's cutting edge data center SSDs and take glimpse into the future with PCIe Gen6 storage performance.
Author Bio:
Ryan Meredith is the Director of Storage Systems Architecture for Micron's Storage Business Unit. He and his team execute workload studies to characterize the performance of Micron's new data center SSDs. This enhances Micron's understanding of the workloads our customers care about, helps us build better SSDs, and expands Micron's thought leadership in fields like AI, all-flash software-defined storage technologies, and a host of cloud and data center workloads.
This session delves into the transformative impact of AI on the storage and connectivity landscape, highlighting the critical role of NAND Flash, SSDs, and PCIe technologies in meeting increasingly complex AI-driven demands. As AI workloads evolve, they necessitate rapid data transfer, high-performance storage solutions, and innovative interconnect strategies to manage massive datasets effectively. Presentations underscore the pivotal advancements in NAND technology that cater to AI's escalating performance needs, including the emergence of PCIe Gen6 and storage-class memory technologies poised to revolutionize market dynamics. The strategic interplay between AI accelerators, enterprise SSDs, and PCIe switches is dissected to reveal how these elements collectively enhance storage efficiency, scalability, and power performance. Attendees will gain insights into the supply-demand dynamics, pricing trends, and strategic maneuvers by industry leaders, equipping them with the foresight to navigate the next wave of technological innovation in AI-centric environments.
PRO
CXLT-302-1:
CXL Pooling and Fabrics
Ballroom B (Santa Clara Convention Center, First Floor)
Track:
CXL
Organizer:
Anil Godbole, Sr. CXL Mktg Manager, Intel
Anil Godbole is a CXL Marketing Working Group Co-Chair and Senior Marketing Manager for Intel’s Xeon Product Planning and Marketing Group. His domain is in Memory, Serdes Technologies & Associate Protocols (DDRx, CXL, PCIe, Ethernet, etc.). Previously, he held a position as Design Engineer in CPU-support ASICs, FPGAs.
Presenters:
Presentation Session Description:
Grant Mackey, CTO, Jackrabbit Labs
Presentation Title:
CXL Orchestration: Taming the Fabric
Presentation Abstract:
A follow on discussion from last year, learn how to tame the CXL fabric and unleash the power of composable infrastructure.
CXL promises a revolution in data center architecture, a new era of memory and resource sharing. However, without a robust middle connecting devices with applications, it's just potential. This presentation explores a working implementation of a CXL fabric orchestrator and its integration with the popular resource scheduler Kubernetes. Learn how CXL can enable dynamic allocation and optimized utilization, learn about the warts, learn about how you can get involved.
Author Bio:
Grant is the CTO of Jackrabbit Labs, a memory fabrics company, whose mission is to enable the next generation of data center through software. An avid supporter, consumer, and contributor of open source software, Grant was a pioneer for voluntary open source efforts while employed at Western Digital. He is an industry veteran familiar with data center, storage, and memory fabric architectures, and has advanced these areas in one way or another through simulation, prototype, and productization efforts across his career.
Brian Pan, CEO, H3 Platform
Presentation Title:
Usage case and performance of CXL 2.0 memory pooling and sharing among hosts
Presentation Abstract:
The H3 presentation will detail the current validation status of Compute Express Link (CXL) memory pooling and sharing. The session will encompass the readiness of operating system environments, central processing unit (CPU) platforms, and application programming interfaces (Redfish CXL APIs). Furthermore, the presentation will address Basic Input/Output System (BIOS) configuration procedures and present performance benchmark data. This comprehensive overview aims to provide attendees with a thorough understanding of the present stage of CXL technology development and system integration concerning CXL switching solutions.
Author Bio:
Brian Pan is the CEO and founder of H3 Platform. His extensive experience encompasses the development of PCIe-based solutions, utilizing Broadcom and Microchip PCIe Gen3, Gen4, and Gen5 switches. Additionally, he has contributed to the advancement of composable memory and GPU solutions. Brian possesses a deep understanding of cloud service provider and data center requirements, enabling him to design effective composable infrastructure solutions.
Jianping Jiang, SVP, Business, Xconn Technologies
Presentation Title:
CXL Memory Pooling/Sharing for In Memory Database
Presentation Abstract:
Alibaba and XConn will present a real usage case of using CXL memory pooling/sharing for in memory database application. We will show the system architecture where CXL servers, CXL swith, CXL memory box are major components of the system and how they are connected with each other. We will show performance data such as bandwidth and latency for memory access of CXL memory, the benchmark data is compared with the existing methods to show the performance improvements.
Author Bio:
Jianping(JP) Jiang is the Senior VP of Product Marketing and Business Operation at Xconn Technologies, a silicon valley startup pioneering CXL switch IC. At Xconn, he is in charge of CXL ecosystem partner relationship, CXL product marketing, business development, corporate strategy and operations. Before joining Xconn, JP held various
leadership positions at several large scale semiconductor companies, focusing on product planning/roadmaps, product marketing and business
development. In these roles, he developed competitive and differentiated product strategies, leading to successful product lines that generate over billions of dollars revenue annually. JP has a Ph.D degree in computer science from the Ohio State University.
John Groves, Technical Director, Micron
Presentation Title:
Famfs - the Fabric-Attached Memory File System
Presentation Abstract:
Sharing disaggregated memory presents new challenges. Existing abstractions are not already in place for sharable disaggregated memory. Famfs addresses this deficiency by enabling the file system abstraction to sharable memory. Because nearly all applications that use data can handle data in files, famfs provides the broadest initial enablement pos-sible for sharable memory.
Famfs is an append-only log-structured file system, which enables multiple hosts to mount a file system instance from the same memory. Although famfs imposes many limitations relative to a conventional file system, we will demonstrate that conventional applications can use data in famfs, and that cache coherency challenges can be addressed and mitigated with clever design of configurations and use cases.
Famfs is free and open source software which is working and available now, and is on track for merging into up-stream Linux in the coming months. The objective is to provide enablement for research, testing, design, and ulti-mately deployment of applications that use disaggregated shared memory.
Author Bio:
John Groves has been a kernel and system software developer for decades, working on several Unix variants prior to Linux. John is the author of famfs – the Fabric-Attached Memory File System – which is working its way toward inclusion the Linux Kernel. John is co-chair of the CXL Software and Systems Working Group (SSWG). a Micron’s voting member of the Systems and Software Working Group of the CXL consortium, and author of portions of the dynamic capacity device (DCD) and fabric management portions of the CXL specification. John has spoken on famfs at the last two Linux Plumbers conferences (2023 and 2024) as well as LSFMM in 2024 and Usenix FAST in 2025.
This session delves into the transformative potential and practical challenges of implementing Compute Express Link (CXL) technology within modern data center architectures. Through a series of presentations, attendees will explore the dynamic allocation and optimized utilization of resources enabled by CXL, as well as the orchestration of these capabilities via Kubernetes. The current readiness of CXL memory pooling and sharing across various platforms and the integration of Redfish CXL APIs are critically analyzed, providing insights into system integration and performance benchmarks. A real-world application by Alibaba and XConn highlights the tangible benefits of CXL in in-memory database applications, demonstrating significant improvements in bandwidth and latency. Additionally, the session introduces Famfs, a pioneering file system abstraction for sharable disaggregated memory, addressing challenges of cache coherency and enabling broad application use. Collectively, these discussions underscore CXL's role in advancing composable infrastructure, with a focus on innovation, collaboration, and the path toward deployment in production environments.
PRO
DCTR-302-1:
Data Center High-Capacity SSDs
Ballroom F (Santa Clara Convention Center, First Floor)
Track:
Data Center Storage and Memory
Organizer:
Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft
Jonathan Hinkle is Senior Director - Azure Memory and Storage Pathfinding at Microsoft. He previously was In Micron's Storage Business Unit, where he investigated new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.
Chairperson:
Steven Wells, Retired, Self
Steven Wells is a 40+ year veteran with most of that time focused on flash memory component and SSD design. He holds 65+ patents covering flash memory and security. He is currently retired and enjoying contributing time and energy to the industry he's spent his entire adult life developing.
Presenters:
Presentation Session Description:
Steven Sprouse, Distinguished Engineer, Sandisk
Presentation Title:
Sprandom - A fast, pseudo random preconditioning method for high capacity SSDs.
Presentation Abstract:
As SSD capacities increase beyond 16TB, the time to randomly precondition these drives has also increased from several hours to several days. Traditional methods involve a sequential write followed by multiple random writes to reach a steady state.
We present Sprandom (Sandisk Pseudo Random) – a novel approach to random preconditioning that uses the Flexible I/O Tester (fio) to achieve near steady-state performance with just a single physical drive write.
Our experiments show that using the Sprandom method, the random preconditioning time of large (> 64TB) drives can be reduced from days to hours.
This presentation offers a short introduction to the key concepts of random write preconditioning, overprovisioning (OP), and write amplification.
Attendees will learn how to use the flexible I/O tester (fio) and the Sprandom method to optimize an SSD's random preconditioning process—achieving the ideal steady-state distribution with just one physical drive write.
Author Bio:
Steven Sprouse has been with Western Digital/Sandisk for 20 years, focusing on systems architecture, performance analysis, and algorithms for NAND flash management. Prior to joining SanDisk, Steven worked at Sun Microsystems and PMC-Sierra.
Anthony Constantine, Distinguished Member of Technical Staff, Micron Technology
Presentation Title:
E2: A New High Capacity SSD for a New Storage Era
Presentation Abstract:
The need for higher capacity SSDs sooner than what traditional NAND scaling can provide is quickly emerging. As a result, development has started on a new SSD form factor specification called E2 that can meet this need. The purpose of this talk is to go through what is driving this need, introduce the details on this new form factor, and provide and update on this form factor's development.
Author Bio:
Anthony Constantine is a Distinguished Member of the Technical Staff at Micron Technology responsible for storage standards within the Storage Business Unit. He is involved through authoring or contributing in various industry organizations including NVMe, SNIA, JEDEC, PCI-SIG, and OCP. Anthony has over 24 years of experience in the technology industry with an expertise in memory, storage, physical interfaces, low power technologies, and form factors. He earned a BS in Electrical Engineering from UC Davis.
Pete Kirkpatrick, VP, Hardware Architect, Pure Storage
Presentation Title:
Enabling QLC Flash for Hyperscalers
Presentation Abstract:
QLC NAND is transforming the hyperscale storage landscape, offering unprecedented power, space and TCO advantages by delivering the highest densities and optimal performance for a growing set of workloads including AI. This session will explore how storage solutions can simplify exascale QLC adoption by seamlessly integrating into existing software stacks while maintaining robust management, diagnostics, and operational efficiency. Learn about how hyperscalers can unlock the full potential of QLC technology to deliver high performance, reliability and power efficiency for AI/ML, tiering and HDD displacement use cases.
Author Bio:
Pete Kirkpatrick is the VP of Hardware Architecture at Pure Storage. He has played a critical role in advancing Pure Storage's mission to enable the widespread adoption of flash in data centers. He holds a Master’s degree in Electrical and Computer Engineering from the University of Colorado Boulder and has numerous patents to his name.
As the demand for high-capacity SSDs surges, the storage industry is at the cusp of innovation, addressing challenges through new technologies and methodologies. This session brings together pivotal advancements in SSD technology, focusing on enhanced capacities, efficient preconditioning techniques, and the transformative potential of QLC NAND. The introduction of the E2 form factor aims to meet the burgeoning need for larger SSDs by overcoming limitations in traditional NAND scaling, setting a new standard for performance and capacity. Complementing this, the innovative Sprandom approach significantly reduces random preconditioning times, optimizing SSD performance and efficiency with large drives. Lastly, the adoption of QLC NAND is reshaping hyperscale storage, offering unmatched density and cost advantages for diverse workloads, including AI/ML applications. Together, these presentations illuminate the path forward in SSD technology, emphasizing integration, performance optimization, and strategic deployment to meet the evolving demands of data-intensive environments.
PRO
DRAM-302-1:
HBM: DRAM's Bright Future
Ballroom E (Santa Clara Convention Center, First Floor)
Track:
DRAM
Organizer + Chairperson:
Ju Jin An, Senior Technical Staff Member, IBM
Ju Jin An is a Senior Technical Staff Member in IBM's Infrastructure Supply Chain Organization. Ju Jin has a background in silicon fabrication process R&D and manufacturing process integration through 20 years of career in the semiconductor industry. She is responsible for enabling memory sub-system for IBM power and z system. She holds a MS/Ph.D. degree in Chemical Engineering from MIT and a BS from Seoul National University.
Presenters:
Presentation Session Description:
Simone Bertolazzi, Principal Analyst, Yole Group
Presentation Title:
Next-Generation DRAM – Market and Technology Trends
Presentation Abstract:
The DRAM industry is at a pivotal juncture, driven by the growing demands of AI, high-performance computing, and data-intensive applications. This presentation will explore the latest technical trends shaping the next generation of DRAM, with a particular focus on the key inflection points that are set to redefine the industry roadmap. I will delve into emerging innovations such as 3D DRAM and other architectural advancements still in the R&D phase, highlighting their potential to overcome current scalability challenges. Additionally, we will provide market perspectives on high-bandwidth memory (HBM), which continues to gain traction as a critical enabler for advanced computing workloads.
Author Bio:
Simone Bertolazzi, PhD, is a Principal Technology & Market analyst, Memory, at Yole Intelligence, part of Yole Group. As member of Yole’s memory team, he contributes on a day-to-day basis to the analysis of memory markets and technologies, their related materials, device architecture and fabrication processes. Simone obtained a PhD in physics in 2015 from École Polytechnique Fédérale de Lausanne (Switzerland) and a double M. A. Sc. degree from Polytechnique de Montréal (Canada) and Politecnico di Milano (Italy).
Marc Greenberg, Principal/CEO, Marc Greenberg Consulting
Presentation Title:
Memory for AI
Presentation Abstract:
In this PDS tutorial we will cover the the case for both existing and novel techniques for interfacing memory to the predominantly non-Von-Neumann compute architectures found in AI processors such as GPU/NPU/TPU (collectively, xPU).
We'll discuss AI processor architectures and how they use memory including how developments in quantization and sparsity will affect memory access. We'll review how existing JEDEC standard memories such as HBM, GDDR, LPDDR and DDR may be used to meet those needs based on capacity, access time, and access energy. Then we'll look at novel techniques that are showing promise such as in-memory computing using novel non-volatile memories like MRAM, near-memory computing in chiplets or 3D stacks based on UCIe, BoW or standards-based interfaces, and the case for SRAM-dominated compute on logic dies.
Author Bio:
Marc Greenberg is an independent consultant in memory, semiconductor and IP. Marc currently serves as VP of Product for Cassia.ai, an AI IP company, as vice-chair of an undisclosed task group at JEDEC, and as advisor to several other companies. Marc was responsible for product management of HBM and other memory and storage IP products at Denali, Cadence and Synopsys for 20 years out of a 30-year career in semiconductor and IP. Marc has a master's degree in Electronics from the University of Edinburgh in Scotland.
Mark Webb, Consultant/Analyst, MKW Ventures Consulting LLC
Presentation Title:
HBM Memory Future: Technology, Cost, and Market Size
Presentation Abstract:
High Bandwidth Memory has been growing at ~100% CAGR for two years and is dramatically impacting the DRAM memory market and contributing to the AI boom. There are changes starting in 2025 that will impact the market, the financials, and where the supply chain constraints are. We update the market forecast for next five years, show the impact of technology with cost and bit shipments forecasts, and show when the market will reach a period of slower growth and market correction. We show how this can be tracked and what the impacts will be to the memory markets overall during a future inventory digestion period.
Author Bio:
Mark Webb is principal analyst and advisor at MKW Ventures Consulting LLC. His focus areas are memory technology and semiconductor foundry processes and costs. Mark is a recognized expert in NAND, DRAM, and Emerging Memory technologies and costs. Mark was previously Manufacturing Director in the NVM Solutions Group at Intel Corporation. Prior to that, Mark was Product Quality and Reliability Manager at IM Flash Technologies from 2006-2008. From 1989 to 2006, Mark held a variety of positions at Intel Corporation in Process Logic and Memory Integration and Product Engineering. Mark is a frequent presenter at Flash Memory Summit and other Memory and Storage conferences. Mark has a BS degree in electrical and computer engineering
Jim Handy, General Director, Objective Analysis
Presentation Title:
HBM: DRAM's Bright Future
Presentation Abstract:
HBM has proven to be the bright spot in today’s memory business, and is one of the key drivers to the current growth of the semiconductor market. In this presentation, industry analyst Jim Handy will provide the current status of the HBM landscape its future direction, and will predict the impact HBM will have on the market for standard DRAM and other components. The presentation will explore AI's future growth while addressing concerns about sustainability and energy consumption, as well as technical issues ranging from signaling and heat dissipation to stacking and bonding tradeoffs, with an eye beyond HBM4 to processing-in-memory, HBM flash, and upcoming customization. This is a rich field that is just beginning to change the way that memory and processors interact.
Author Bio:
Jim Handy of Objective Analysis is a 35-year semiconductor industry executive and a leading industry analyst. Following marketing and design positions at Intel, National Semiconductor, and Infineon he became highly respected as an analyst for his technical depth, accurate forecasts, industry presence, and numerous market reports, articles, white papers, and quotes. He posts blogs at www.TheMemoryGuy.com, and www.TheSSDguy.com.
This session delves into the rapidly evolving landscape of memory technologies in the context of AI and high-performance computing, highlighting the interplay between existing standards and emerging innovations. A common theme across presentations is the transformative role of High Bandwidth Memory (HBM) in fueling the AI boom, with both its robust growth and impact on the DRAM market thoroughly examined. Discussions underscore the significant influence of AI processor architectures on memory access, particularly in light of developments in quantization and sparsity. The session explores the promise of novel techniques such as in-memory and near-memory computing, alongside the critical importance of addressing sustainability and energy consumption. Key insights into market dynamics, including future forecasts and supply chain implications, offer a comprehensive view of how these memory technologies are set to redefine the industry. From 3D DRAM advancements to potential processing-in-memory innovations, this session provides a forward-looking perspective on how these technological inflections will shape the future of memory and processor interactions.
Open
INDA-302-1:
UALink™ 200G 1.0 Specification Overview and Applications
Ballroom D (Santa Clara Convention Center, First Floor)
Track:
Industry Associations
Presenters:
Presentation Session Description:
Derek Williams, AMD Fellow, AMD
Derek Williams is an AMD Fellow and currently a UALink Architect. He joined AMD after a 34-year career at IBM with experience in system bring up, verification, storage subsystem design, fabric and coherence protocol design, front end tools design, memory consistency models, and transactional memory for Power servers over nine generations. His current area of interest is in UALink protocol development. Mr. Williams earned a BSEE and MSE from the University of Texas at Austin, holds in excess of 350 patents, and has co-authored several conference papers and journal articles on Power storage subsystem design, the Power Memory Consistency model, and transactional memory.
As the demand for AI compute grows, Cloud Service Providers, System OEMs, and IP/Silicon Providers need an efficient, optimized solution to address scale-up AI challenges. The UALink 200G 1.0 Specification defines a low-latency, high-bandwidth interconnect for communication between accelerators and switches in AI computing pods. By increasing performance, improving power and cost efficiency and introducing supply chain diversity and interoperability, UALink enables next-generation AI/ML applications.
During this session, a UALink panel of experts will highlight the technology’s latest advancements and demonstrate how UALink will help create multi-node systems for AI applications. Attendees will have the opportunity to ask questions about the future applications and benefits of UALink devices.
PRO
NVME-302-1:
NVMe New Features
Ballroom C (Santa Clara Convention Center, First Floor)
Track:
NVMe
Organizer:
Cameron Brett, Director, KIOXIA America, Inc
Cameron Brett is the Director of Enterprise SSD Marketing at Kioxia, where he manages a team of product line managers to drive product strategy and revenue growth. Cameron has over 18 years of product marketing and management experience in storage technology and has previously held managerial positions at QLogic, PMC-Sierra, Broadcom and Adaptec. Throughout his career in high-tech product marketing, he has focused on storage for enterprise and small/medium business servers and worked to bring new generations of storage technology to market. His area of expertise includes Flash/SSD storage, virtualization, convergence and cloud technologies
Presenters:
Presentation Session Description:
Jason Molgaard, Principal Storage Solutions Architect, Solidigm
Jason Molgaard is an experienced storage controller RTL designer and architect having worked for various storage device companies architecting and designing HDD and SSD storage controllers. As a Principal Storage Solutions Architect on the Solidigm Pathfinding and Advanced Development Team, Jason focuses on future storage controller architectures and technologies, including Computational Storage and CXL. Jason is co-chair of the SNIA Computational Storage TWG and the SNIA Technical Council. Jason helps drive the Computational Storage standard at both SNIA and NVMe. Jason holds a Master of Science degree in Electrical Engineering.
Scott Lee, Principal Software Engineer Lead, Microsoft
Presentation Title:
NVMe Innovations in Windows
Presentation Abstract:
I'm seeing a 12 minute slot to share about recent and upcoming NVMe related innovations in Windows. Recent NVMe related innovation will discuss new NVMe related features available in the latest shipping Windows client and server OSes. Upcoming NVMe innovation will preview new NVMe related features that Microsoft is working on that will impact NVMe device vendors and/or OEMs in future Windows OS versions.
Author Bio:
Scott Lee is a Principal Software Engineer Manager in Microsoft’s Core OS group with 25+ years of industry experience and 15+ years working in Window’s storage stack. He leads the team that owns the Windows lower storage stack and the Window inbox drivers for NVMe, SATA, UFS, iSCSI and persistent and CXL memory.
Prashant Dixit, Architect, Siemens EDA
Presentation Title:
Pre-Migration Verification for NVMe SSDs: Ensuring Seamless Live Migration
Presentation Abstract:
The host-managed live migration allows maintenance without interrupting a workload, rebooting an instance, or modifying any instance's properties like IP addresses, metadata or network settings. To ensure thorough verification and overcoming the challenges, solution must be agile to validate track and migration commands, suspend and resume, data transfers to and from different regions, controller data queues management, and memory scoreboarding across power cycles.
We will discuss the important characteristics of the solution from planning to closure. We will explore how using common APIs, data structures, migration with existing/updating queues and data structures, utilizing UVM features like callbacks and analysis components will make the solution highly adaptable by keeping the high-level stimulus same. We will also delve into strategies for making the solution reusable for new features like NVM Subsystem Migration. We will see a case study on how these techniques, along with an exhaustive compliance test suite and efficient debug mechanism, helped our NVMe customers thoroughly verify the intricacies of live migration-enabled SSD designs and achieve a shorter time to market.
Author Bio:
Prashant Dixit, an architect is leading the Verification IPs team which deals with the development, testing and deployment of CXL, NVMe over PCIe and over Fabrics solutions.
Prior to his role at Siemens EDA, Prashant gained valuable experience at Samsung, where he contributed to the design and verification of IPs and SoC of networking and storage domains.
He has completed his Master of Engineering in Microelectronics from BITS Pilani in 2006 and Bachelor of Technology in Electronics and Communication from Uttar Pradesh Technical University in 2004.
The pervasive era of Artificial Intelligence and Machine Learning, demands high performance secured storage mechanisms. NVM Express® (NVMe®) technology has become the storage backbone for AI, ML and beyond and this session will feature multiple presentations from industry experts discussing important technology updates and use cases. In the first presentation, attendees will receive an overview of the latest and upcoming drivers updates for Windows. The next presentation will discuss the Live Migration feature. The host-managed live migration allows maintenance without interrupting a workload, rebooting an instance, or modifying any instance's properties like IP addresses, metadata or network settings. To ensure thorough verification and overcoming the challenges, the solution must be agile to validate track and migration commands, suspend and resume, data transfers to and from different regions, controller data queues management and memory scoreboarding across power cycles. We will discuss the important characteristics of the solution from planning to closure. We will explore how using common APIs, data structures, migration with existing/updating queues and data structures, utilizing UVM features like callbacks and analysis components will make the solution highly adaptable by keeping the high-level stimulus same. We will also delve into strategies for making the solution reusable for new features like NVM Subsystem Migration. We will see a case study on how these techniques, along with an exhaustive compliance test suite and efficient debug mechanism, helped our NVMe customers thoroughly verify the intricacies of live migration-enabled SSD designs and achieve a shorter time to market.
Open
OPSW-302-1:
Optimizing AI Infrastructure at Scale - a Panel
GAMR-1 & 2 (Great America Meeting Rooms, SCCC 2nd Floor)
Track:
Open Source Software
Organizer + Chairperson:
Javier Gonzalez, Principal Engineer, Samsung
I lead Samsung Semiconductor's Global Open-ecoSystem Team (GOST - https://tinyurl.com/SamsungGOST), where I take care of our ecosystem activities and manage a distributed team of highly talented engineers. This includes defining our vision, strategy, internal / external communication, and day-to-day execution. I am also the founder and site manager for Samsung Semiconductor Denmark Research (SSDR) - Samsung’s Memory Solutions first R&D center in Europe and fifth worldwide.
Panel Members:
Panel Session Description:
Nilesh Shah, VP Business Development, ZeroPoint Technologies
Nilesh Shah is VP Business Development, ZeroPoint Technologies. Additionally. He participates and contributes regularly at standards bodies like SNIA, OCP, JEDEC, RISC-V, CXL Consortium. He is regularly invited to speak at conferences, and has led multiple panels and is featured in Analyst/ Press interviews, focused on AI and memory technologies. Previously, Nilesh led Strategic Planning at Intel Corporation's Non Volatile Memory Solutions Group, where he was responsible for the product planning and launch of the Data Center SSD products and Pathfinding innovations. Nilesh advises GPU and memory Chiplet startups.
Adi Gangidi, Performance Lead, Meta
Adi leads a team at Meta in designing, deploying and sustaining a large scale RDMA Network / Communication Software solution for AI training on GPUs. His specialty is using Commodity ethernet infrastructure and still providing great performance as SOTA vertically integrated vendor solutions.
Dhabaleswar K DK Panda, Professor and University Distinguished Scholar, Ohio State University
Dhabaleswar K (DK) Panda is a Professor and University Distinguished Scholar of Computer Science and Engineering at the Ohio State University. He serves as the Director of the newly-established $20M NSF-AI Institute, ICICLE (https://icicle.ai). He has published over 500 papers in the area of high-end computing and networking. The MVAPICH (High-Performance MPI over InfiniBand, Omni-Path, iWARP, RoCE, and Slingshot) libraries, designed and developed by his research group (http://mvapich.cse.ohio-state.edu), are currently being used by more than 3,400 organizations worldwide (in 92 countries). More than 1.88 million downloads of this software have taken place from the project's site.
Hoshik Kim, Senior VP & Fellow Memory System Research, SK Hynix
Hoshik Kim is Senior Vice President and Fellow of Memory Systems Research at SK hynix, where he leads various research and pathfinding activities in the area of memory systems and solution architecture.
His current research interests focus on next-generation memory systems architecture and software solution in various systems and application domains, which include Custom HBM, CXL memory expansion, memory disaggregation, computational memory and storage solutions.
Prior to joining SK hynix, he worked for Intel Corporation and LG Electronics, where he gained broad experiences in architecture, design, verification and electronic design automation (EDA) for microprocessors, system-on-chips (SoC) and intellectual properties (IP).
Akshay Subramaniam, Senior AI Tech Development, NVIDIA
I work on developing parallel numerical algorithms for high performance computing and AI applications. I enjoy using mathematics and computational tools in applied settings to solve challenging problems of societal value. My research interests are broad and I am specifically interested in algorithm development, simulation technologies and Artificial Intelligence. I am skilled in many computational tools including C++, Python, Fortran, Tensorflow, MPI , OpenMP and CUDA.
Andrew Greene, Member of Technical Staff, Zyphra
I do things with and to computers. I've worked at software companies like Palantir, Netflix, and Tiktok, and I currently work at Zyphra building software that interacts with models. As a product builder in this space working at a research lab, I view the question of whether to use a proprietary or open source model as not just cost-benefit analysis, but critical to the expressiveness and specificity of the way your product creates value for users.
Ace Stryker, AI Infrastructure Product Marketing, Solidigm
Responsible for identifying emerging market opportunities for Solidigm's data center products and building and executing marketing plans to accelerate market share gain. Current focus on generative AI applications.
In this session, industry experts will delve into the critical role of storage strategies in optimizing AI infrastructure as workloads scale. Central to the discussion is the evaluation of file, object, and block storage choices for accelerator-driven I/O in Vector Databases (VectorDBs) and foundational model workflows. The panel will explore the impact of these storage paradigms on latency, throughput, and scalability, particularly when GPUs and custom ASIC accelerators directly access data. A key focus will be the debate between open-source and proprietary solutions in terms of their effectiveness in delivering compressed foundational models, optimizing KV Cache storage for inference, and facilitating swift retrieval in VectorDBs. The session will also address the complexities of managing large-scale datasets across training, fine-tuning, and inference stages, emphasizing the need for efficient data streaming, checkpointing, and sharding. Participants will gain insights into how these evolving AI workloads are reshaping storage strategies and the future trajectory of AI infrastructure.
PRO
SSDT-302-1:
AI Workloads and Data Placement Techniques
Ballroom G (Santa Clara Convention Center, First Floor)
Track:
SSD Technology
Chairperson:
Roman Pletka, Senior Research Scientist, IBM Research - Zurich
Roman Pletka is a senior research scientist and master inventor for storage and AI systems at the IBM Zurich Research Laboratory where he focuses on non-volatile memory technologies and AI in storage systems. He is a frequent speaker at international conferences, has published over 20 articles and obtained more than 130 patents in managing non-volatile memories, security, scalability, and availability of distributed storage systems as well as quality-of-service in high-speed networks, active networks, and network processors. He has made presentations at many international conferences including the ACM International Conference on Systems and Storage (SYSTOR) and the Nonvolatile Memory Workshop. He earned a PhD in computer networking from ETH Zurich, Switzerland and an MS in the same subject from EPFL (Swiss Federal Institute of Technology of Lausanne) and has over 20 years experience in storage systems research.
Organizer:
Erich Haratsch, Senior Director Architecture, Marvell Semiconductor
Erich Haratsch is the Senior Director of Architecture at Marvell, where he leads the architecture definition of SSD and storage controllers. Before joining Marvell, he worked at Seagate and LSI, focusing on SSD controllers. Earlier in his career, he contributed to multiple generations of HDD controllers at LSI and Agere Systems. Erich began his career at AT&T and Lucent Bell Labs, working on Gigabit Ethernet over copper, optical communications, and the MPEG-4 video standard. He is the author of over 40 peer-reviewed journal and conference papers and holds more than 200 U.S. patents. A Senior Member of IEEE, Erich earned his MS and PhD degrees from the Technical University of Munich, Germany.
Presenters:
Presentation Session Description:
David Yeh, Product Marketing Manager, Silicon Motion
Presentation Title:
Optimizing SSD Performance for Edge AI: NVMe Dataset Management Insights
Presentation Abstract:
Edge computing enables data to be stored and processed at the network edge, reducing latency and enhancing performance for real-time AI services. However, existing technologies such as ZNS and FDP often fall short in providing flexible data storage solutions for highly standardized SSDs. The "Dataset Management Commands," as defined by the NVMe specification, offer a powerful approach to optimizing data placement strategies through SSD firmware. In this presentation, we will compare Dataset Management, ZNS, and FDP, highlighting their respective strengths and limitations. Furthermore, we will show a real implementation of our PCIe 5.0 SSD controller with Dataset Management Commands, demonstrating its performance and WAF under workloads designed to simulate AI model transactions on edge devices. This session aims to offer practical insights and actionable strategies for leveraging Dataset Management to enhance data placement, reduce WAF, and improve overall SSD performance. The goal is to meet the application and service of AI on edge devices.
Author Bio:
David Yeh has 10 years of experience in the SSD industry, with 7 years focused on firmware R&D and specializing in FTL implementation, as well as 3 years in product marketing. He has collaborated with many NAND manufacturers around the world and participated in numerous projects. Currently, he focused on Gen4/Gen5 SSD projects and dedicated to providing technologically advanced solutions.
Kiran Bhat, Product Manager, Solidigm
Presentation Title:
IO charecterization of AI workloads and models
Presentation Abstract:
Understanding of AI workloads is very critical for designing, tuning and optimizing and deploying the storage devices for AI applications. Please join to learn three of the most popular AI models and IO characteristics of the data created by AI models during training and inference when deployed in real-world applications that will enable you to choose the right storage solution for your application.
Author Bio:
Kiran is an experienced Product Manager. He has been in storage industry for the last 7 years. He started working on client SSDs and now works as a Data center SSD product manager on on the Data center. Kiran worked as Technical Maketing Engineer at Intel's PC client division for more than a decade before moving to storage. Kiran has a masters degree in Electrical Engineering.
Robert Moss, Principal Architect, Samsung
Presentation Title:
Unlocking Efficiency: SNIA's Guidelines for Flexible Data Placement
Presentation Abstract:
Flexible Data Placement (FDP) provides for the increasing performance requirements from storage to meet the needs of AI. The SNIA Data Placement TWG has published a whitepaper outlining recommendations for FDP configurations. This document provides guidance for enterprise SSD vendors, enabling them to implement standardized FDP configurations that align with industry best practices. By adopting these recommendations, vendors can reduce variation in the marketplace and provide customers with a consistent experience. Customers will benefit from knowing that their SSDs will support at least one FDP configuration that conforms to the SNIA guidelines, allowing them to focus their host software development on specific configuration ranges and simplify testing and optimization efforts.
This presentation will summarize the key recommendations and discuss the benefits of industry alignment for both vendors and customers
Author Bio:
Robert is a Principal Architect at Samsung Semiconductor, specializing in enterprise NVMe SSDs. With an extensive background in SSD storage controller design and architecture, he has expanded his contributions to NVMe standards development and architectural innovation supporting new and emerging standards. His current areas of focus have included Zoned Namespaces (ZNS) controller optimization, and Flexible Data Placement (FDP) standards and controller development, with an emphasis on optimizing data placement controller architecture.
Rajesh Neermarga, Distinguished Engineer, Sandisk
Presentation Title:
Using FDP to Optimize Video Recording Performance for External Storage
Presentation Abstract:
Mobile Phone and Drone applications allow video recording and storage, while simultaneously allowing data backup. In these use cases, the user does not explicitly purge or trim the storage medium but a guaranteed rate of recording is required. In the above use case when multiple applications are recording/storing the data, a given application's recording rate can impact the performance on another application stream because of data fragmentation. This talk wll discuss how a host can achieve guaranteed performance, improve power-to-performance ratio, and provide higher endurance (by reducing write amplification) using some of the techniques of Flexible Data Placement (FDP). This use case will be illustrated using analysis done on the High capacity (>1TB) uSD Express/External SSD storage products.
Author Bio:
Rajesh has been a System Architecthas at Sandisk for 10 years. He has developed SATA/PCIe SSDs and portable USB storage devices and solutions.
This session delves into the evolving landscape of storage solutions tailored for AI workloads, focusing on optimizing data placement and enhancing performance both at the edge and in enterprise environments. A central theme is the critical role of understanding AI model IO characteristics and the deployment of storage technologies like Dataset Management Commands and Flexible Data Placement (FDP) to meet the demands of real-time AI applications. Presentations will explore the strengths and limitations of various technologies such as ZNS and FDP, with practical demonstrations of their implementation in PCIe 5.0 SSD controllers, showcasing improved performance and reduced write amplification factor (WAF). The session will also highlight industry alignment efforts, including SNIA's guidance on FDP configurations, aiming to standardize practices and reduce market variability. Additionally, strategies to ensure guaranteed performance in dynamic application environments, such as those involving mobile devices and drones, will be examined. Attendees will gain insights into selecting appropriate storage solutions and configuring them to optimize AI applications both at the network edge and in enterprise settings.
10:00 AM to 02:30 PM
Open
GEN :
FMS Exhibition
Exhibit Hall (Santa Clara Convention Center, First Floor)
Track:
General Events
General Event Description:
Description Not Available
11:00 AM to 12:00 PM
Open
SPEC-301-1:
Special Presentation: Executive AI Panel: Memory and Storage Scaling for AI Inferencing
Mission City Ballroom (Santa Clara Convention Center, First Floor)
Track:
Special Sessions
Chairperson:
John Kim, Director of Storage Marketing , NVIDIA
John Kim is Director of Storage Marketing at NVIDIA.
Speakers:
Special Presentation Description:
Rory Bolt, Senior Fellow, KIOXIA America
Rory Bolt is a senior fellow at KIOXIA America and leads the forward-looking technology and storage pathfinding group for SSDs. He has more than twenty-five years of experience in data storage systems, data protection systems, and high-performance computing with a pedigree from marquee storage companies. Rory has been granted over 12 storage related patents and has several pending. Rory has a BS in Computer Engineering from UCSD.
Vincent (Yu-Cheng) Hsu, IBM Fellow, CTO & VP of IBM storage, IBM
Vincent (Yu-Cheng) Hsu is an IBM Fellow, CTO, and VP of IBM Storage. His responsibilities include IBM storage technical strategy, future storage technology research, storage system architecture, design, and solutions development. He is leading IBM storage’s strategic initiatives to support IBM hybrid clouds, Data and AI and cyber security. Vince has devoted his entire 30+ years of his career on storage system research and development. He is a master inventor at IBM. In 2005 he was named a Distinguished Engineer and Chief Engineer for IBM Enterprise storage. In 2009, he was named the CTO for IBM disk storage leading IBM storage technology council to oversee storage technology for all IBM disk storage products. He was named an IBM Fellow in 2015. Since 2023, Mr. Hsu represents IBM in Ceph community governance board. He is appointed as an IBM TT (Technology team) member in 2024. In 2025, Vincent led IBM storage to deliver the very first content aware storage solution to accelerate AI data processing and inferencing. Vincent is a graduate of the University of Arizona and holds a Master of Science degree in Computer Engineer and an MBA from Eller college of the University of Arizona.
John Mao, VP Global Business Development , VAST Data
A technology executive and leader with over 20-years of cross-functional experience in early and growth stage technology companies, John is currently the VP of global business development and strategic alliances at VAST Data, focused on enabling AI, data analytics, and cloud use-cases for large data organizations. Prior to joining VAST, John led product management and product strategy teams across a wide range of technology verticals including cloud infrastructure, network and application performance management, custom hardware (silicon), big data / analytics, storage and hyper-converged infrastructure. Starting his career as a database engineer provided an onramp into the world of unlocking meaningful insight from large datasets, a passion he still possesses today. John holds a B.S. in Computer Science from the University of Texas.
Sunny Kang, VP of DRAM Technology, SK hynix
With over 30 years of experience at SK hynix, Sunny Kang has successfully led numerous high-impact initiatives as a seasoned expert in DRAM Planning and New Product Enabling. His role as a JEDEC representative, contributing to memory standardization and ecosystem development, has been a cornerstone of his professional journey. Since relocating to SK Hynix America in 2022, he has been leading the DRAM Technology teams, overseeing future pathfinding and roadmap alignment with key customers like NVIDIA. His responsibilities also include New Product Enabling, and customer technical support related to mass production quality. A critical aspect of his role is ensuring our technology roadmaps are closely aligned with all our customer needs, enabling seamless integration and optimal performance.
Raw bandwidth is important for AI training workloads, but AI inference needs that and more. It also needs distributed solutions with AI optimized low latency networking, and intelligent memory and storage for optimum performance. This panel explores how ultra-high performance AI optimized storage networking, and GPU enhanced AI storage solutions can dramatically accelerate data transfers between memory and local and remote storage tiers. This enables dynamic resource allocation, significantly boosting AI inferencing request throughput. We will explore how this combination addresses the challenges of scaling inference workloads across large GPU fleets moving beyond traditional bottlenecks. We have assembled a panel of experts from inside NVIDIA and across the storage and memory industry to provide insight on how to maximize the number of AI requests served, while maintaining low latency and high accuracy.
12:00 PM to 01:00 PM
Open
BRK:
Thursday Lunch
Exhibit Hall D (Santa Clara Convention Center, First Floor)
Track:
General Events
General Event Description:
Description Not Available
12:10 PM to 01:15 PM
PRO
AIML-303-1:
Storage for AI: Solutions
Ballroom A (Santa Clara Convention Center, First Floor)
Track:
AI and ML Applications
Chairperson:
Jonathan Prout, Director, Memory Business Development, Samsung Semiconductor
Jonathan Prout is Director of Memory Business Development at Samsung Semiconductor Inc., where he leads initiatives to advance data center and enterprise storage solutions through strategic partnerships and innovative business models. With nearly a decade of experience in the semiconductor industry, Jonathan previously held roles in consulting and product planning, where he supported the development of Samsung’s CXL® technology-based product strategy. His current focus is on enabling partnerships within the software-defined storage ecosystem to unlock the next generation of storage innovation.
Organizer:
David McIntyre, Director Product Planning, Samsung Electronics
David McIntyre focuses on computational storage acceleration solutions development and strategic business enablement for cloud to edge applications including AI inference/video analytics, database processing and blockchain networks. He has held senior management positions with IBM, Samsung, Xilinx, Intel (formerly Altera) and at Silicon Valley startups. He has consulted for institutional investors including Fidelity, Goldman Sachs and UBS. David is a frequent presenter and chairperson at the Flash Memory Summit and other technical conferences including SNIA.
Presenters:
Presentation Session Description:
Reggie Reynolds, Principal Product Marketing Manager, NVIDIA
Presentation Title:
Accelerating AI and Storage with NVIDIA Spectrum-X
Presentation Abstract:
The speed of storage directly impacts the performance of AI clusters. As AI models scale, slow or congested storage networks create bottlenecks that throttle GPU utilization and prolong training times. NVIDIA Spectrum-X, a high-performance Ethernet networking platform, overcomes these challenges by delivering 50% higher storage bandwidth per GPU using RoCE Adaptive Routing. By dynamically optimizing data paths, Spectrum-X ensures AI workloads get the high-speed storage access they need without congestion bottlenecks.
In addition, Spectrum-X provides performance isolation, preventing noisy neighbors from degrading storage access in shared AI infrastructure. This results in a 1.2× speedup in AI workloads, ensuring predictable and consistent performance at scale.
This session will explore how Spectrum-X accelerates AI storage, eliminates network congestion, and enhances multi-tenant AI infrastructure. Attendees will gain insights into real-world performance gains and best practices for integrating Spectrum-X into AI clusters.
Author Bio:
Reggie Reynolds is the Product Marketing Manager at NVIDIA, where he helps lead the go-to-market strategy and execution for NVIDIA’s Networking Platforms with storage partners. He has over 35 years of experience in the data storage industry, particularly in high-performance computing (HPC). Reggie joined NVIDIA in late 2020 from DDN Storage, where he was instrumental in leading DDN's QA and worldwide support organizations.
Floyd Christofferson, VP of Product Marketing , Hammerspace
Presentation Title:
Accelerating AI with HPC-Class Performance on Standard IT Infrastructure
Presentation Abstract:
The path to deploying AI use cases is seldom straightforward. Building dedicated AI infrastructure involves performance requirements that standard data centers are not equipped for. This leaves IT teams faced with having to retool existing infrastructure, or incurring the cost of building dedicated high-performance AI repositories, both of which have a direct impact on the ROI of AI initiatives. This session will focus on how existing IT environments can adapt to the performance needs of AI use cases, but without the cost and risk of retooling their existing environments.
This presentation will focus on three key topics that address these issues:
-- How standard Linux is being used to deliver HPC-class parallel file system performance for AI workloads at extreme scales on commodity hardware.
-- How the integration of this tech into SSD drives will usher in unprecedented performance gains and power savings for AI and HPC-type use cases.
-- Innovation that activates local storage on GPU/CPU servers to dramatically accelerate checkpointing and reduce costs.
We will cover examples of how these technologies are being used today to accelerate AI use cases without exploding costs.
Author Bio:
Floyd Christofferson is VP of Product Marketing at Hammerspace.
Xiangyu Tang, Senior Member of Technical Staff, Micron
Presentation Title:
AI Inferencing SSD Traffic Profile for Client PCs
Presentation Abstract:
AI capable PC shipment is projected to reach 35% in 2025, and over 55% in 2026. AI PCs’ main purpose is inferencing operations, training is not expected to be significant. Improving the user experience of AI applications on PCs is a main focus in the industry.
Our paper profiles AI inferencing storage IO traffic, and details its difference with traditional user traffic on client PCs. The paper also introduces how AI inferencing performance is measured by benchmarks and perceived by users. We demonstrate how storage bottlenecks impact AI inferencing performance. In particular we profile SSD IO traffic for single and multiple LLM model loading, RAG data ingestion, RAG inferencing with vector database simlarity search, and AI storage benchmarks. We showcase AI storage performance on different generation of SSDs from multiple brands. We finally discuss possible innovations targeting certain aspects of AI inferencing traffic to improve user experience.
Author Bio:
Dr. Tang graduated from the University of Illinois at Urbana-Champaign. He has since worked at major SSD companies such as SK Hynix, Sandisk, and Micron.
This session will delve into the pivotal role of storage performance in AI infrastructure, offering a comprehensive exploration of how cutting-edge technologies are addressing key challenges in AI deployment. Common themes across the presentations include the critical need to overcome storage bottlenecks and enhance performance for AI workloads, whether in high-performance data centers or consumer PCs. NVIDIA Spectrum-X emerges as a transformative solution, providing high-speed storage access and performance isolation to ensure consistent AI workload efficiency. Concurrently, there is a focus on adapting existing IT environments to meet AI demands without significant retooling, leveraging innovations such as HPC-class parallel file systems on commodity hardware and enhanced SSD integration for power savings. Furthermore, the session will highlight the anticipated growth of AI-capable PCs and the unique storage demands of AI inferencing, emphasizing the importance of optimized storage IO traffic and user experience. Attendees will gain valuable insights into integrating these advancements to streamline AI operations and maximize returns on investment.
Open
CHIP-303-1:
Navigating the Chiplet Revolution: Applying EDA Insights into UCIe Standards
Ballroom D (Santa Clara Convention Center, First Floor)
Track:
Chiplets and UCIe
Organizer:
Brian Rea, UCIe Marketing Work Group Chair, UCIe Consortium
Brian Rea is a senior technologist in the industry initiative and technology enabling team at Intel and is the Marketing Working Group Co-Chair for the UCIe Consortium. Brian has held engineering, marketing, and strategic planning roles bringing products with new technologies to market including USB, Gigabit Ethernet, PCIe, and CXL. His passion is working with customers and partners to enable ecosystem innovations in silicon, hardware, and software. Brian holds an MBA from the University of Washington and a BSEE from the University of Texas at Austin.
Presenters:
Presentation Session Description:
Prashant Dixit, Architect, Siemens EDA
Presentation Title:
Mastering UCIe 2.0: Overcoming Fabric Management Hurdles for Chiplet Integration
Presentation Abstract:
UCIe 2.0 introduces system architecture and MTP. This standardizes communication between management entities within a System-in-Package (SiP) and allows the creation of complex multi-chiplet systems or topologies with greater interoperability. All components in dies must be verified from a system-level perspective which includes: MTP encapsulation over SB or MB, discovery/configuration of management elements and ports in a multi-chiplet SiP, routing between chiplets across different domains, combining MTP with other protocols in the MB, bridging across domains, configuring routing tables for MB/SB, VCs, and TCs.
Since UCIe is evolving, new protocols like security will be added soon, let us explore the strategies, such as designing APIs that simplify complexity and ensure full portability, creating portable and SiP topology-agnostic tests to make the environment reusable for future, using UVM features, like callbacks and analysis components, to adapt to protocol like PCIe, CXL, CHI, AXI, C2C etc. We will see a case study on how the above techniques, flexible architecture, exhaustive compliance test suite, and efficient debug helped UCIe customers to achieve a shorter time to market.
Author Bio:
Prashant Dixit, an architect is leading the Verification IPs team which deals with the development, testing and deployment of CXL, NVMe over PCIe and over Fabrics solutions.
Prior to his role at Siemens EDA, Prashant gained valuable experience at Samsung, where he contributed to the design and verification of IPs and SoC of networking and storage domains.
He has completed his Master of Engineering in Microelectronics from BITS Pilani in 2006 and Bachelor of Technology in Electronics and Communication from Uttar Pradesh Technical University in 2004.
Himani Kaushik, Lead Member Technical Staff, Siemens EDA
Presentation Title:
Versatile Verification framework for multi-protocol UCIe Design
Presentation Abstract:
A holistic verification of a chiplet design is achieved with system-level verification, addressing synchronization issues, timing variations, and protocol interoperability.
Multi-die systems evolve quickly and with protocols such as PCIe, CXL, AXI, CHI, and interfaces such as C2C, CXS, etc. On-package integration with protocols provide streamline data encapsulation which is coupled with the performance-enhancing characteristics of UCIe. It is important that chiplet designs are rigorously tested against system level operations to monitor performance, enhance security and achieve stability.
This presentation will introduce an architecture for a versatile adapter to integrate diverse Protocol layers and interfaces over UCIe verification solution to streamline testbench for system level verification. Multiple designs have been tested to validate the proposed architecture by reusing existing Protocol testbench with minimal updates to accommodate UCIe Verification solution.
Author Bio:
Himani Kaushik works as Lead Member Technical Staff at Siemens EDA. She has been associated with Siemens for over 4 years and currently works in the UCIe domain. She holds a past working experience in NVMe and CXL Verification IP. She graduated with a Bachelor in Engineering (B.E.) degree from Netaji Subhas University of Technology (NSUT)(2020).
Tim Wang Lee, Signal Integrity Application Scientist, Keysight
Presentation Title:
Your Chiplet Design Is Failing the UCIe Spec - Here’s Why
Presentation Abstract:
As the Universal Chiplet Interconnect Express (UCIe) emerges as a pivotal standard in the chiplet revolution, chiplet-based architectures are redefining system integration by delivering high-bandwidth, low-latency, and power-efficient interconnects. This presentation delves into the electrical specifications and signal integrity practices that form the backbone of robust die-to-die communication in multi-vendor chiplet ecosystems.
Attendees will understand UCIe’s electrical specifications in-depth and uncover the hidden challenges that cause chiplet designs to fail UCIe compliance through a design example. This session offers actionable insights for both emerging engineers and seasoned professionals looking to future-proof their designs, improve system robustness, and drive innovation in memory storage solutions.
Author Bio:
Chun-ting "Tim" Wang Lee, Ph.D., is a Signal Integrity Application Scientist at Keysight, where he uses simulation tools and measurement insights to help engineers achieve better Signal Integrity (SI) in their designs. In his current role, he has been studying the Chiplet UCIe standard and has delivered presentations on the system-level SI challenges associated with chiplet designs. Tim started in Keysight working on coding the PAM4 eye diagram algorithm. Most recently, he lead the development team to bring a new signal integrity software to market. Recognized as one of DesignCon’s 40-under-40, Tim is known for his technical knowledge and clear and engaging communication style at industry conferences. He holds a Ph.D. in Signal Integrity from the University of Colorado at Boulder, focusing on achieving better simulation and measurement correlation for printed circuit board SI analysis. Tim's mission is to empower engineers with the knowledge and tools to confidently tackle signal integrity and chiplet design challenges.
Prashant DIxit, Architect, Siemens EDA
Presentation Title:
UCIe Chiplet Ecosystem: Interoperable Testbench for Multi-Vendor IP Integration
Presentation Abstract:
The chiplet ecosystem and standards are still in their infancy. Consequently, official interoperability and compliance programs from workgroups like the UCIe Working Group are not yet available. Typically, it takes a couple of years after a specification is published for workgroups to organize interoperability or compliance events, as silicon is not available before then. This poses a risk for early adopters of the standards but also offers opportunities for companies to collaborate early in their design processes.
We will describe a simulation-based interoperability program that integrates UCIe IP from two companies into a simulation environment, focusing on LogPhy and D2D interoperability in two stages. Verification IP for UCIe is used to create interoperability test cases and drive traffic through RDI and FDI interfaces. We discuss the challenges encountered during the interoperability exercise, the test cases developed to demonstrate interoperability, and the results. Additionally, we explore how other companies can participate in similar interoperability efforts to accelerate the adoption and rollout of UCIe-based designs.
Author Bio:
Prashant Dixit, an architect is leading the Verification IPs team which deals with the development, testing and deployment of CXL, NVMe over PCIe and over Fabrics solutions.
Prior to his role at Siemens EDA, Prashant gained valuable experience at Samsung, where he contributed to the design and verification of IPs and SoC of networking and storage domains.
He has completed his Master of Engineering in Microelectronics from BITS Pilani in 2006 and Bachelor of Technology in Electronics and Communication from Uttar Pradesh Technical University in 2004.
The session on chiplet-based architectures and the emerging Universal Chiplet Interconnect Express (UCIe) standard explores how these technologies are transforming system integration by fostering high-bandwidth, low-latency, and power-efficient interconnects. Central to the discussions are the challenges and opportunities presented by the nascent chiplet ecosystem, including the intricacies of electrical specifications, signal integrity, and system-level verification. Through detailed analysis, presenters delve into the importance of robust die-to-die communication and the necessity for comprehensive verification frameworks that address synchronization, timing variations, and protocol interoperability. The session further highlights the simulation-based interoperability initiatives that serve as a proactive approach for early adopters, facilitating collaboration and accelerating the adoption of UCIe standards. Participants will gain actionable insights into future-proofing designs, improving system robustness, and driving innovation in multi-vendor environments, setting the stage for the widespread adoption of UCIe-based solutions.
PRO
CXLT-303-1:
CXL and AI
Ballroom B (Santa Clara Convention Center, First Floor)
Track:
CXL
Organizer + Chairperson:
Anil Godbole, Sr. CXL Mktg Manager, Intel
Anil Godbole is a CXL Marketing Working Group Co-Chair and Senior Marketing Manager for Intel’s Xeon Product Planning and Marketing Group. His domain is in Memory, Serdes Technologies & Associate Protocols (DDRx, CXL, PCIe, Ethernet, etc.). Previously, he held a position as Design Engineer in CPU-support ASICs, FPGAs.
Presenters:
Presentation Session Description:
Sandeep Dattaprasad, Director, Product Management, Astera Labs
Presentation Title:
Accelerating AI with Real-World CXL Platforms
Presentation Abstract:
The rapid growth of AI is driving unprecedented demand for high-bandwidth, high-capacity memory solutions. Compute Express Link (CXL) is emerging as a key enabler in 2025, unlocking new levels of memory scalability and efficiency. Join experts from Astera Labs and SMART Modular Systems as they discuss how CXL-based solutions—such as Astera Labs’ Leo CXL Smart Memory Controller and SMART’s 4-DIMM and 8-DIMM Add-In Cards—are addressing memory bottlenecks and capacity constraints in modern data centers.
Attendees will:
• Learn about real-world applications and customer platforms using CXL
• Gain insights into benchmarks for CXL performance and latency
• Understand how OEM customers are leveraging the CXL solution
Author Bio:
Sandeep Dattaprasad is a Director of Product Management and Technologist with Astera Labs. He has 15+ years of experience in semiconductor, software diagnostic tools, developing security strategies and firmware development for complex SoC product lines including Compute Express Link products, SAS RAID controllers, SAS expanders and PCIe switches. He is also a contributing member of the CXL Consortium. At Astera Labs, Sandeep’s focus is on driving product strategy for new market segments by translating data center bottlenecks into profitable and competitive hardware and software solutions using CXL technology.
Andy Mills, Vice President, Advanced Product Development, SMART Modular
Presentation Title:
Accelerating AI with Real-World CXL Platforms
Presentation Abstract:
The rapid growth of AI is driving unprecedented demand for high-bandwidth, high-capacity memory solutions. Compute Express Link (CXL) is emerging as a key enabler in 2025, unlocking new levels of memory scalability and efficiency. Join experts from Astera Labs and SMART Modular Systems as they discuss how CXL-based solutions—such as Astera Labs’ Leo CXL Smart Memory Controller and SMART’s 4-DIMM and 8-DIMM Add-In Cards—are addressing memory bottlenecks and capacity constraints in modern data centers.
Attendees will:
• Learn about real-world applications and customer platforms using CXL
• Gain insights into benchmarks for CXL performance and latency
• Understand how OEM customers are leveraging the CXL solution
Author Bio:
Andy leads the Advanced Product Development team at SMART Modular where he is responsible for CXL hardware and software, software-defined memory and memory pooling product development. Prior to joining SMART Modular, Andy was the co-founder at Enmotus, Inc where he led the architecture and development of a real-time machine intelligent SSD tiering software solution which was deployed on more than 1 million PCs and servers around the world. Prior to Enmotus, Andy served in various product development and strategic roles at DotHill, Ciprico, Netcell, TDK Semiconductor, Rockwell Semiconductor and AMD. He holds a Masters Degree in Electrical and Electronic Engineering from Bangor University in the UK
Raghu Vamsi Krishna Talanki, Associate Director, DRAM System Solutions, Samsung Electronics
Presentation Title:
Optimizing RAG inference efficiency using CXL Memory Expander
Presentation Abstract:
Retrieval-Augmented Generation (RAG) significantly improves Large Language Model (LLM) response quality by integrating relevant contextual data. This study examines three RAG configurations: Predefined, Dynamic, and Batch-wise vector databases, all employing a GPT-2 Large multi-qa-mpnet-base-dot-v1 embedding model to optimize inference within large-scale LLM deployments. Using Static profiling, we strategically allocated cold data (embeddings and LLM weights) to CXL memory and hot data (vector database) to DRAM. Results indicate a 1.65x inference efficiency improvement, highlighting CXL's effectiveness in enhancing batch processing and enabling scalable inference with improved DDR and CPU utilization. This establishes CXL as a critical component for high-performance RAG. Further performance optimization is being explored through dynamic data placement and movement using the device assisted CXL Hotness Monitoring Unit (CHMU).
Author Bio:
Raghu Vamsi Krishna Talanki is an Associate Director in DRAM System Solutions/SSIR/Samsung Electronics.
Klas Moreau, CEO, ZeroPoint Technologies
Presentation Title:
The AI Memory Bottleneck – Are We Wasting Capacity?
Presentation Abstract:
As AI workloads explode in size, memory efficiency is reaching a breaking point. Are we truly optimizing AI infrastructure, or are we stuck in outdated paradigms? Foundational models already rely on lossy compression—so why haven’t we pushed lossless compression to its full potential?
This session will challenge conventional thinking on AI memory management. We’ll present groundbreaking results showcasing real-time, lossless compression in CXL-based composable memory, tied together with an end to end Open stack extending into the Linux kernel drivers, requiring ZERO Host Application changes. Our FPGA prototype demonstrates how memory compression and tiered architectures can dramatically reduce AI memory footprint while maintaining performance.
Author Bio:
Klas is Experienced in building global companies , with 25-year background in AI, semiconductors and gaming
Raj Uppala, Sr. DIrector of Marketing , Rambus
Presentation Title:
The AI Memory Bottleneck – Are We Wasting Capacity?
Presentation Abstract:
As AI workloads explode in size, memory efficiency is reaching a breaking point. Are we truly optimizing AI infrastructure, or are we stuck in outdated paradigms? Foundational models already rely on lossy compression—so why haven’t we pushed lossless compression to its full potential?
This session will challenge conventional thinking on AI memory management. We’ll present groundbreaking results showcasing real-time, lossless compression in CXL-based composable memory, tied together with an end to end Open stack extending into the Linux kernel drivers, requiring ZERO Host Application changes. Our FPGA prototype demonstrates how memory compression and tiered architectures can dramatically reduce AI memory footprint while maintaining performance.
Author Bio:
Raj Uppala is Sr. Director of Marketing at Rambus, leading branding, positioning, demand generation, sales enablement, and ecosystem partnerships for the Silicon IP business. He previously held product and marketing roles at Western Digital, driving HDD and Smart Video solutions. With a background in memory and mixed-signal IC design, Raj brings deep semiconductor experience, and holds an MBA from Cornell and an MS in EE from Mississippi State.
Jongryool Kim , Research Director, SK hynix
Presentation Title:
Distributed LLM Serving with CXL-based Disaggregated Memory
Presentation Abstract:
Large Language Models (LLMs) are extensively used in many modern applications such as natural language processing, chatbots, etc. Typically, to serve large number of client requests, AI service providers (such as OpenAI, Google, etc.) maintain multiple instances of their LLM inference engines (e.g. ChatGPT, Gemini, etc.) and distribute input requests so as to achieve better throughput and latency. In addition, every instance of inference applications places necessary data close to the GPU memory for optimal performance. For example, inference engines/applications employ fine-tuned, low-rank additive matrices (such as LoRA adapters) to serve requests with diverse contexts over the same base LLM (e.g., Llama-2/3, GPT-3/4, etc.). Due to the heterogeneous nature of input requests, inference applications load many LoRA adapters into GPU memory or dynamically load/offload the adapters from host memory. At the service level, each instance must maintain redundant copies of a large number of adapters for faster access and therefore resulting in inefficient use of system memory. One method to address this issue is to place commonly shared data on disaggregated memory pools attached to infere
Author Bio:
Dr. Jongryool Kim is currently serving as the research director of AI System Infra team at SK hynix Inc., located in San Jose, California. He has been a part of the SK hynix since 2020, during which time he has been conducting research and development of numerous advanced projects such as custom HBM, CXL Pooled memory, computational CXL memory and storage, and object interface storage solution for AI/HPC systems. Additionally, he is a member of the Open Computing Project (OCP) Future Technology Initiative (FTI), working for the data-centric computing (DCC) workstream. Dr. Kim is also a Science Advisory Board (SAB) member of Semiconductor Research Corporation (SRC) JUMP 2.0. Prior to this role, he had served as the cloud system architect at Samsung Mobile division developing and operating a Samsung Cloud data analytics system that manages and analyzes data from all Samsung devices (smart phones, wearable devices, and home appliances) around the world. Additionally, he worked with various R&D teams at Samsung SW R&D Center. He conducted research to improve network and storage IO performance in High Performance Computing (HPC) and Cloud.
The session explores the transformative role of Compute Express Link (CXL) in addressing the pressing memory challenges posed by the rapid expansion of AI workloads and large language models (LLMs). Across multiple presentations, experts highlight CXL as a pivotal technology enabling scalable and efficient memory solutions. Key themes include the deployment of CXL-based memory controllers and add-in cards to alleviate data center bottlenecks, the integration of Retrieval-Augmented Generation (RAG) to enhance LLM inference through improved data placement, and the innovative use of real-time, lossless compression within CXL architectures to optimize memory usage without sacrificing performance. Additionally, the session addresses the strategic distribution of inference engine data to enhance throughput and latency, emphasizing the value of disaggregated memory pools for handling diverse AI service demands. Collectively, these insights underscore CXL's critical role in advancing AI infrastructure, offering a pathway to more efficient, scalable, and high-performance computing environments.
PRO
DCTR-303-1:
Data Center Memory and Storage Resilience
Ballroom F (Santa Clara Convention Center, First Floor)
Track:
Data Center Storage and Memory
Chairperson:
Scott Shadley, Director of Leadership Narrative and Evangelist, Solidigm
Scott Shadley has spent over 25 years in the semiconductor and storage space. He has time in Production, Engineering, R&D, Customer focused roles including Marketing and Strategy. His current focus is in efforts to drive adoption of new storage technology as a Director of Leadership Narrative and Evangelist at Solidigm. He has been a key figure in promoting SNIA as a Board member and leading the computational storage efforts as a co-chair of the SNIA Technical Working Group. He participates in several industry efforts like Open Compute, NVM Express and is seen as a subject matter expert in SSD technology and semiconductor design. He has and still speaks on the subject at events like the Open Compute Summit, Flash Memory Summit, SDC, and many other events, press interviews, blogs, and webinars. While at NGD Systems, Scott developed and managed the Computational Storage products and ecosystem. Scott previously managed the Product Marketing team at Micron, was the Business Line Manager for the SATA SSD portfolio, and was the Principal Technologist for the SSD and emerging memory portfolio. He launched four successful innovative SSDs for Micron and two for STEC, all of which were billion dollar programs. Scott earned a BSEE in Device Physics from Boise State University and an MBA in marketing from University of Phoenix.
Organizer:
Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft
Jonathan Hinkle is Senior Director - Azure Memory and Storage Pathfinding at Microsoft. He previously was In Micron's Storage Business Unit, where he investigated new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.
Presenters:
Presentation Session Description:
Barry Pangrle, Vice President Hardware Engineering, Abacus Semiconductor Corporation
Presentation Title:
High Performance RAID With Universal High Performance Interconnect (UHI)
Presentation Abstract:
Abstract: Even with today's increasing storage density in SSDs, large density HDDs are still roughly an order of magnitude lower in terms of purchase cost in $/TB. We propose a high-performance RAID solution using a novel approach that employs NCQ and smart caching to order and minimize the number of transactions that are sent to the HDD, thus optimizing throughput and lowering average latency. A "server on a chip" incorporating RAID controllers provides processing and connectivity to memory along with high bandwidth and low latency connectivity across Universal High Performance Interconnect (UHI) ports.
Author Bio:
Barry Pangrle brings to Abacus Semi seasoned engineering leadership that has spanned both start-ups and Fortune 500 organizations. His 30-year career in Silicon Valley has encompassed leading teams in fabless semiconductor startups and EDA companies designing new and innovative products, as well as the design tools underlying these products. For the past two decades he has specialized in power analysis, management and optimization starting with revitalizing the Synopsys Power Compiler and PrimePower R&D teams circa 2002, which led to tens of millions in annual revenue. He has twice led the design methodology and flow efforts starting from scratch at fabless semiconductor startups XStream Logic and Esperanto Technologies, where he was also a co-founder. He has authored and co-authored numerous peer-reviewed papers and book chapters and is a senior member of the IEEE and is currently the Open Source Lead for the IEEE P1801 (UPF) Working Group. Barry has a Ph.D. in Computer Science and a B.S. in Computer Engineering, both from the University of Illinois, Urbana-Champaign.
Wojciech Malikowski, Software Engineer, Solidigm
Presentation Title:
CSAL with Core Scaling for RAID5F: Revolutionizing Cloud Storage Performance and
Presentation Abstract:
This proposal introduces an innovation to the CSAL framework by integrating core scaling with RAID5F—a novel RAID implementation that eliminates the read-modify-write overhead and write hole problem inherent in traditional RAID5. By leveraging multi-core architectures to dynamically distribute CSAL’s write-shaping and data placement tasks, our approach achieves near-linear scalability across CPU cores while maintaining low-latency I/O. This new configuration, paired with high-capacity QLC drives, exceeds performance, blends cost-efficiency and provides cutting-edge capabilities. Preliminary simulations demonstrate up to 2x throughput gains and a 30% reduction in write amplification compared to previous deployments. This innovation of CSAL with RAID5F provides as a cornerstone for cloud storage, delivering unmatched efficiency and reliability for hyperscale environments.
Author Bio:
Wojciech is an experienced Software Engineer and Technical Leader. He has over fifteen years of professional practice in software development in all phases including designing, architecting, implementation, testing, publishing, and supporting. For the last ten years focused on data-storage technologies. He has experience in storage drivers for a variety of technologies like persistent memory, RAID, and VMD. He is a funder of the FTL (flash translation layer) library in SPDK (storage performance development kit) which is the backbone of CSAL (cloud storage acceleration layer) solution software. His area of expertise is focused on WAF (write amplification factor) optimization techniques and caching mechanisms. He has a master's degree in electronics and telecommunication from the Wrocław University of Technology.
Terry Grunzke, Principal Hardware Engineer, Microsoft Corporation
Presentation Title:
RAIDDR Error Correction Code for Memory
Presentation Abstract:
Server DRAM reliability demands increasing ECC overheads due to shrinking DRAM process nodes and scaling I/O speeds. Metadata requirements can further increase capacity overheads or use ECC bits at the expense of reliability. DRAM designs transfer more data per device, increasing ECC overheads due to fewer devices per cache line.
RAIDDR is a coding scheme that reduces ECC overheads and costs while maintaining server DRAM reliability. The host memory controller can more effectively use existing ECC bits or use transferred on-die ECC bits to increase the ECC budget without additional overhead, allowing the removal of a die per Rank while achieving close to Single Device Data Correction (SDDC). For example, RAIDDR enables a 9x4 DDR5 DIMM with metadata to have reliability similar to a 10x4 DIMM with current methods. RAIDDR has robust reliability and coverage of operational and inherent faults.
Author Bio:
Terry Grunzke is a Principal Hardware Engineer at Microsoft, where he provides technical leadership in the evaluation and definition of future memory technologies. His responsibilities include the technical evaluation of emerging memory candidates, the development and evaluation of industry memory ECC solutions, and driving the definition of future memory standards per Microsoft requirements. Terry also focuses on providing next-generation memory interface pathfinding. Terry has nearly 30 years of experience in memory and storage technology. He has been issued over 60 US patents. He holds a Bachelor of Computer Engineering from the University of Minnesota, Duluth.
This session delves into cutting-edge advancements in data storage and reliability, showcasing innovative approaches to optimizing RAID configurations and enhancing DRAM reliability. The common theme across the presentations is the strategic use of novel RAID solutions and advanced coding schemes to address cost, performance, and reliability challenges in data storage. The first presentation introduces a high-performance RAID solution leveraging NCQ and smart caching to boost HDD throughput and reduce latency, while a "server on a chip" enhances connectivity and processing capabilities. The second presentation builds on these ideas with RAID5F, integrated into the CSAL framework, achieving near-linear scalability and reduced write overheads using multi-core architectures and high-capacity QLC drives, positioning it as a cornerstone for cloud storage environments. Lastly, the session addresses DRAM reliability through RAIDDR, a coding scheme that minimizes ECC overheads, maintaining high reliability with reduced capacity costs. Collectively, these innovations highlight a trend towards achieving greater efficiency, cost-effectiveness, and reliability in hyperscale data environments.
Open
DRAM-303-1:
High Performance DRAM Technology
GAMR-1 & 2 (Great America Meeting Rooms, SCCC 2nd Floor)
Track:
DRAM
Organizer + Chairperson:
Ju Jin An, Senior Technical Staff Member, IBM
Ju Jin An is a Senior Technical Staff Member in IBM's Infrastructure Supply Chain Organization. Ju Jin has a background in silicon fabrication process R&D and manufacturing process integration through 20 years of career in the semiconductor industry. She is responsible for enabling memory sub-system for IBM power and z system. She holds a MS/Ph.D. degree in Chemical Engineering from MIT and a BS from Seoul National University.
Presenters:
Presentation Session Description:
Frank Ferro, Group Director Memory and Storage IP, , Cadence Design Systems
Frank Ferro is the group director of product marketing at Cadence Design Systems responsible for memory and storage interface IP products. Frank joined Cadence after spending 10 years at Rambus, Inc. working on memory and SerDes IP products. In addition to Rambus, Frank spent more than 20 years at AT&T, Lucent, and Agere Systems. Mr. Ferro holds an executive MBA from the Fuqua School of Business at Duke University, an M.S. in computer science and a B.S. in electronic engineering technology from the New Jersey Institute of Technology.
Khayam Anjam, Sr Systems Performance Engineer, Micron
Presentation Title:
Low-Power (LP) DDR memory in Datacenters
Presentation Abstract:
Low-Power (LP) DDR memory has been used for a long time in mobile and client systems because it can significantly reduce energy consumption over regular DDR memory. However with new architectures like the NVIDIA GH200 platforms where the LPDDR5X Memory is tightly integrated on the system and packaged very close to the CPU, LP can enhance both efficiency and performance for datacenter environments.
In this talk, we will delve into the technical aspects of a HPC workload, highlighting how LP memory's lower voltage operation and reduced thermal output contribute to improved computational performance. We will also discuss the architectural benefits of GH200, including its high-bandwidth memory interface and optimized power management, which together result in substantial power savings and enhanced processing efficiency.
Author Bio:
I am a Sr. Systems Performance engineer at Micron working on characterizing AI workloads in a datacenter environment.
Henrique Potter, Sr. Systems Performance Engineer, Micron Technologies
Presentation Title:
Beyond Bandwidth: MRDIMMs’ Edge in the Data Center Revolution
Presentation Abstract:
The rise of AI, real-time analytics, and high-performance computing pushes traditional memory technologies like Registered DIMMs (RDIMMs) to their limits. As CPU core counts increase, the demand for memory bandwidth has become a critical bottleneck. To address this challenge, Micron and Intel have co-developed Multiplexed Rank Dual In-line Memory Modules (MRDIMMs)—a next-generation memory solution engineered to deliver higher bandwidth, lower latency, and superior scalability for data-intensive workloads.
This presentation will highlight MRDIMMs’ significant performance gains over RDIMMs, with microbenchmarks showing a 41% bandwidth increase and a 40% reduction in latency. Real-world application testing, such as OpenFOAM simulations, demonstrates a 30% reduction in runtime, while MRDIMMs’ ability to maintain lower latency under memory-intensive conditions benefits workloads spanning databases, analytics, and virtualization. With up to 40% better-loaded latency under typical loads, MRDIMMs provide a more efficient and scalable solution for future memory demands, making them a compelling choice for next-generation data centers—despite their higher power draw.
Author Bio:
Henrique Pötter, Ph.D. is a researcher and engineer specializing in AI, power efficiency, and advanced memory technologies. He holds a Ph.D. in Computer Science from the University of Pittsburgh. At Micron Technologies, Dr. Pötter has driven significant projects evaluating DRAM technologies like DDR4, DDR5, TSV, and MRDIMM for AI and HPC applications, optimizing performance with state-of-the-art data center servers. He also excels in creating compelling demos, presentations, and benchmarks to illustrate these innovations to diverse audiences.
Nidish Kamath, Director - Product Management, Rambus
Presentation Title:
GDDR Memory for High-Performance AI Inference
Presentation Abstract:
The rapid rise in size and sophistication of AI/ML inference models requires increasingly powerful hardware deployed at the network edge and in endpoint devices. AI/ML Inference workloads for applications like edge computing and Advanced Driver Assistance Systems (ADAS) require high bandwidth memory while keeping costs low. With performance of over 20 Gbps, GDDR6 has been a good solution, providing an excellent combination of high bandwidth and cost efficiency.
As bandwidth requirements increase, the recently released GDDR7 with speeds of 36 Gbps, will provide the additional bandwidth needed moving forward for these systems. To implement high-speed memory interfaces for both the memory PHY and controller, it requires the performance and power efficiency of TSMC’s advanced process nodes. This presentation will discuss how Rambus and Cadence worked together to develop an integrated memory subsystem that is deployed widely in end-customer systems using TSMC advanced nodes. Also discussed will be the signal integrity challenges of implementing GDDR6 and GDDR7 at these high data rates.
Author Bio:
Nidish Kamath is the Director of Product Management for Memory Interface IP at Rambus. He previously held marketing and product management roles at AMD, Kioxia (formerly Toshiba Memory), Avalanche Technologies, Brocade and Qualcomm, where he worked on computational storage, SmartNICs and GPU cluster networking solutions. He has served in various standards and industry associations such as SNIA, Center for Open Source Software (CROSS), CXL Consortium, UEC and JEDEC.
Igor Sharovar, Chief Technology Officer, Truememorytechnology LLC
Presentation Title:
IO-DIMM: A Low-Latency, Power-Efficient Near-Memory I/O Interface
Presentation Abstract:
The presentation introduces IO-DIMM, a low-latency, power-efficient near-memory I/O interface designed to overcome the limitations of PCIe and CXL. While DDR interfaces offer lower latency than PCIe and CXL, they lack efficient asynchronous communication, making them unsuitable for high-performance I/O devices. Research on NVDIMM-P shows significant latency improvements for DDR-connected I/O devices, but its adoption is limited due to the absence of widespread memory subsystem implementations.
IO-DIMM offers a cost-effective alternative that replicates NVDIMM-P benefits without requiring new memory subsystems. It reuses existing DDR memory controllers, maintaining full compatibility with standard DDR protocols. By enabling direct load/store memory operations through DDR buses, IO-DIMM eliminates PCIe transaction overhead and CXL coherence delays, achieving latencies as low as 50–100 ns, compared to 250–500 ns for CXL and 1–10 µs for PCIe.
The architecture reduces power consumption by removing external PCIe interfaces and minimizing CPU utilization through interrupt-free operation. Additionally, IO-DIMM supports near-memory processing, ideal for AI and real-time data applications.
Author Bio:
Igor Sharovar is the founder of Truememorytechnology and the author of patents protecting the intellectual property (IP) behind the company's technology.
Igor’s LinkedIn profile can be found at https://www.linkedin.com/in/igor-sharovar-6151434/. He holds an M.S. in Electrical Engineering from the National Technical University of Ukraine and an M.S. in Computer Engineering from the University of Ottawa, Canada. He has extensive experience in hardware and software engineering and is the author of a published book: https://www.amazon.com/-/es/Igor-Sharovar/dp/3639230914
Throughout his career, Igor has worked with startups and large enterprises, contributing to various engineering projects.
In a rapidly evolving technological landscape, the search for efficient, high-performance memory solutions has never been more critical, as highlighted by recent advancements in memory technologies. This session explores the intersection of power efficiency and performance enhancement across various high-demand environments, from data centers to edge computing. Presentations showcase the transformative potential of Low-Power DDR memory, as exemplified by the NVIDIA GH200 platform, which integrates LPDDR5X to optimize power and performance in high-performance computing (HPC) workloads. Similarly, the emergence of Multiplexed Rank DIMMs (MRDIMMs) addresses the growing memory bandwidth demands posed by AI and real-time analytics, offering substantial improvements in latency and scalability despite their power requirements. Furthermore, the transition to GDDR7 memory, developed collaboratively by Rambus and Cadence, provides a pathway for handling the escalating bandwidth needs of AI/ML inference models at the edge. Finally, the innovative IO-DIMM architecture presents a compelling alternative to traditional PCIe and CXL interfaces, delivering low-latency, power-efficient near-memory processing suitable for AI and real-time data applications. Together, these advancements underscore a common theme: the relentless pursuit of memory technologies that not only meet the demands of modern applications but also push the boundaries of power efficiency and performance.
PRO
SSDT-303-1:
New Form Factors and Interfaces for SSDs
Ballroom G (Santa Clara Convention Center, First Floor)
Track:
SSD Technology
Chairperson:
Randy Brown, Senior Principal Engineer, Marvell
Randy Brown, a graduate of Carnegie Mellon University with a degree in Computer Science, is currently a Senior Principal Engineer in the Architecture team of Marvell’s Custom, Compute and Storage Group. Randy has over 30 years of experience in the storage industry. His experience spans filesystems, advanced storage stacks including snapshot and replication, RAID, and iSCSI. He has also managed and contributed to firmware teams that have shipped multiple SATA and NVMe based SSDs.
Organizer:
Erich Haratsch, Senior Director Architecture, Marvell Semiconductor
Erich Haratsch is the Senior Director of Architecture at Marvell, where he leads the architecture definition of SSD and storage controllers. Before joining Marvell, he worked at Seagate and LSI, focusing on SSD controllers. Earlier in his career, he contributed to multiple generations of HDD controllers at LSI and Agere Systems. Erich began his career at AT&T and Lucent Bell Labs, working on Gigabit Ethernet over copper, optical communications, and the MPEG-4 video standard. He is the author of over 40 peer-reviewed journal and conference papers and holds more than 200 U.S. patents. A Senior Member of IEEE, Erich earned his MS and PhD degrees from the Technical University of Munich, Germany.
Presenters:
Presentation Session Description:
Ramyakanth Edupuganti, Applications Engineering Manager, Microchip Technology Inc.,
Presentation Title:
Adaptive Power Optimization Techniques in NVMe® SSD
Presentation Abstract:
NVMe® SSDs have evolved from a standard passive storage device into a highly complex systems with advanced SSD controller architectures which double the performance every generation, support multiple CPUs, HW accelerators, offload engines for computational storage, advanced error correction and machine learning engines in recent times. Beyond the controller, the components used in the SSDs such as SDRAM and NAND memory are also scaling in capacity and speed, and consuming more power. This in turn drives the need for optimizing the power consumption of the SSDs.
Considering the scale and lifetime of SSDs deployed in data centers, saving even a few milliwatts of power makes a big impact to TCO (Total Cost of Ownership) and the environment. It is imperative to apply innovative power optimization techniques and achieve greater savings.
In this presentation, we will discuss various power optimization techniques that can be applied to an SSD from the design phase to the retirement phase, at the controller, component, and system levels. We will also share data on which technique provided the most cost-effective results.
Author Bio:
Ram Edupuganti is Manager, Applications Engineering for Flashtec® NVMe® SSD Controllers in the Data Center Solutions Business Unit of Microchip Technology Inc. Ram has contributed to the product development of Enterprise Storage products for the last 14 years. Ram holds an MS in Computer Science from California State University, Sacramento
Anthony Constantine, Distinguished Member of Technical Staff, Micron Technology
Presentation Title:
How EDSFF is exceeding the needs for PCIe 5.0 and 6.0
Presentation Abstract:
U.2 has been a mainstay SSD form factors for the last 15 years. Its derivation from SAS based HDDs and SSDs made it an easy choice when NVMe based SSDs were released. However, the server has changed over the past 15 years and the the requirements on the SSDs have in turn changed. This drove the creation of the EDSFF family of form factors to meet these needs.
As PCIe 5.0 based SSD become more common and with PCIe 6.0 SSDs right around the corner, the delta between EDSFF and U.2 is becoming more prevalent. The purpose of this presentation is to discuss the challenges of supporting PCIe 5.0 and 6.0 from a electomechanical perspective, the growing deltas being seen between EDSFF and U.2 SSDs, and why you should design your future systems around an EDSFF device.
Author Bio:
Anthony Constantine is a Distinguished Member of the Technical Staff at Micron Technology responsible for storage standards within the Storage Business Unit. He is involved through authoring or contributing in various industry organizations including NVMe, SNIA, JEDEC, PCI-SIG, and OCP. Anthony has over 24 years of experience in the technology industry with an expertise in memory, storage, physical interfaces, low power technologies, and form factors. He earned a BS in Electrical Engineering from UC Davis.
Paul Kaler, Storage and Security Futures Architect, HPE
Presentation Title:
How EDSFF is exceeding the needs for PCIe 5.0 and 6.0
Presentation Abstract:
U.2 has been a mainstay SSD form factors for the last 15 years. Its derivation from SAS based HDDs and SSDs made it an easy choice when NVMe based SSDs were released. However, the server has changed over the past 15 years and the the requirements on the SSDs have in turn changed. This drove the creation of the EDSFF family of form factors to meet these needs.
As PCIe 5.0 based SSD become more common and with PCIe 6.0 SSDs right around the corner, the delta between EDSFF and U.2 is becoming more prevalent. The purpose of this presentation is to discuss the challenges of supporting PCIe 5.0 and 6.0 from a electomechanical perspective, the growing deltas being seen between EDSFF and U.2 SSDs, and why you should design your future systems around an EDSFF device.
Author Bio:
Paul Kaler brings over 20 years of experience to his current role as the Storage and Security Futures Architect for the Future Server Architecture Team at Hewlett Packard Enterprise (HPE). He is responsible for researching and evaluating future storage, interconnect, and security technologies and defining the server storage strategy for ProLiant servers. He has previously led development of SSD storage arrays, been founder and co-founder of a couple of startups, and helped develop the first dual-screen smartphone. Paul is also actively involved in multiple standards and industry organizations, and has been a key driver of standards including U.3, EDSFF E3, and the OCP Datacenter NVMe and SAS-SATA SSD specs.
Kyle Zerner, Senior Engineer, Systems Design Engineering, Sandisk Flash Products Group
Presentation Title:
Adaptive Link Speed Management Benchmarking
Presentation Abstract:
As PCIe PHY technology advances to support increasing bandwidth demands, the importance of power efficiency has become paramount for SSDs operating at PCIe Gen5 speeds. The challenge no longer lies solely in NAND efficiency; SSDs must now also contend with the high power requirements necessary to sustain high PCIe link speeds, even when workloads do not fully exploit the available bandwidth. Many real-world storage scenarios exhibit dynamic bandwidth needs and low queue depths, resulting in significant, yet unused, power-saving potential. To mitigate this inefficiency, adaptive PCIe link speed management emerges as an effective solution, dynamically regulating link speed according to real-time host demands and system power policies, thereby enhancing energy efficiency with minimal compromise to performance.
This presentation will provide an in-depth exploration of the mechanisms that enable adaptive PCIe link speed management in Gen5 SSDs, detailing how real-time workload monitoring and link speed adaptation contribute to improved power consumption and enhanced power efficiency. This is aided by power policy hints to reflect host power savings policies.
Author Bio:
Kyle Zerner joined Western Digital/Sandisk in 2022 after graduating from the University of Maryland. He focuses on systems validation, prototyping, and scripting for interface characterization, optimizing system-level designs and ensuring robust validation processes to advance storage technology.
Carter Snay, Technical Manager, University of New Hampshire InterOperabliity Laboratory
Presentation Title:
From Lab to Market: The Impact of UNH-IOL's NVMe SSD Testing
Presentation Abstract:
Background: This presentation will explore the role of the University of New Hampshire InterOperability Laboratory (UNH-IOL) in advancing NVMe SSD technology through its rigorous testing and compliance programs. We will provide an overview of the NVMe Interop and Compliance Program, discussing its objectives, scope, and the importance of interoperability and compliance testing in the tech industry. Attendees will gain insights into the newest features being tested, the methodologies employed, and the challenges encountered during the testing process.
Results: We will present the tangible outcomes of our testing efforts, highlighting customer success and the positive impact of our program on their products and market readiness. Through real-world example, we will demonstrate how our testing ensures the highest standards of quality and reliability for NVMe SSDs. Additionally, we will discuss the benefits of participating in the NVMe Interop and Compliance Program and provide a glimpse into future advancements and potential developments in NVMe technology.
Author Bio:
Carter Snay is the Technical Manager at the University of New Hampshire Interoperability Laboratory (UNH-IOL), focusing on Datacenter Technologies, specifically NVMe-PCIe and NVMe over Fabrics. His work at UNH-IOL began in March 2017, initially within the iSCSI testing service before transitioning to NVMe technologies in August 2017. Snay's educational background includes studying at the University of New Hampshire, where he studied Computer Science before switching to Environmental Science and is now pursuing an MBA at the Peter T. Paul College of Business and Economics.
This session will delve into the dynamic evolution of SSD technologies, focusing on power efficiency, compliance, and form factor advancements essential for modern storage solutions. Central to the discussions is the challenge of balancing increased PCIe link speeds, as seen in Gen5 and forthcoming Gen6 SSDs, with power efficiency, highlighting innovative adaptive link speed management strategies that align with real-time workload demands and host power policies. Complementing this is an exploration of rigorous testing frameworks led by the University of New Hampshire InterOperability Laboratory, which ensure NVMe SSDs meet the highest standards of interoperability and reliability. As the industry shifts from traditional U.2 to EDSFF form factors, the session will also address the mechanical and power considerations pivotal for future system designs. Finally, a comprehensive overview of advanced power optimization techniques—from design to retirement phases—underscores the critical role of efficient SSD controller architectures and component scaling in reducing total cost of ownership and environmental impact, ultimately driving the next wave of sustainable storage innovation.
PRO
SUST-303-1:
Sustainable Data Centers
Ballroom C (Santa Clara Convention Center, First Floor)
Track:
Sustainability
Presenter + Chairperson:
Jonmichael Hands, Treasurer and Secretary, Circular Drive Initiative
Jonmichael spent ten years at Intel in the Non-Volatile Memory Solutions group working on product line management, strategic planning, and technical marketing for the Intel data center SSDs. Jonmichael is the treasurer and secretary of the Circular Drive Initiative, 501(c)(6) non-profit, promoting the secure reuse of drives and circular business models for the storage industry. Jonmichael started his storage career at Sun Microsystems designing storage arrays (JBODs) and holds an electrical engineering degree from the Colorado School of Mines.
Organizer:
Wayne Adams, SNIA Chairman Emeritus, SNIA
Wayne Adams has over 35 years of IT industry experience spanning business development, technical product/solution management, and partner ecosystems. Wayne has been involved in SNIA leadership roles since 2002. Wayne has served on the SNIA Board of Directors since 2003 including roles as Chair, Chair Emeritus, Treasurer in addition to a number of leadership roles for forums and initiatives, conferences, and strategic alliances. He has spoken at numerous industry forums and events. Over his career, Wayne M. Adams was a Senior Technologist and Director of Standards within the Office of the CTO at EMC, technical alliances partner manager, and a manager of product managers for its portfolio of SRM products. Prior to EMC, Wayne was responsible for product marketing and business development for several strategic software and hardware products at Digital Equipment Corporation. He started his high-tech career at Eastman Kodak as a system designer of real-time control systems. Wayne has been involved in many industry associations including serving on the DMTF Board of Directors, serving as Advisory Committee member of W3C, contributing to the Industrial Internet Consortium for IoT/big data test-beds, leadership of the Fibre Alliance, and participating with various committees within INCITS, OASIS, Cloud Security Alliance, and TheGreenGrid. Wayne holds a Bachelor of Science degree with a dual major in Computer Science and Mathematics from the University of Pittsburgh.
Presenters:
Presentation Session Description:
David Verburg, System Technical Staff Member, Storage Technology, IBM
Presentation Title:
SSD & HDD Sustainability Call to Action
Presentation Abstract:
Sustainability has become more important for the storage industry as we consider our responsibilities to our customers and to the world as a whole. As AI has driven an explosion in power-intensive computing systems with large storage capacity, the need to address sustainability is becoming more urgent. We will look at measures of sustainability for HDD and SSD, examine ways that we can improve in this area in 3 ways, in the energy used to create the drives, in the energy used to run the technology along with different options, and in circular economy at the end of the life of the drives. We will also examine the tradeoffs of leveraging each type of technology, along with some of the challenges we face as an industry.
Author Bio:
Dave Verburg is a Senior Technical Staff Member at IBM responsible for storage device strategy and quality. He has been with IBM since 1991, starting in disk drive manufacturing, and spending the last 15 years of his career working with HDD and SSD quality and technology. Dave has presented to IEEE, at conferences including FMS, and at the Manufacturing Leadership Council while receiving an ML100 award in 2019. Dave received a MS in Electrical Engineering from the University of Minnesota in 1996 and received a BS in both Electrical Engineering and Computer Science from the South Dakota School of Mines and Technology in 1991. Dave is an active volunteer, helping with computer systems and mentoring for the youth at his church and teaching robotics to school children. Dave also can speak both Spanish and Mongolian and uses his language skills to help Samaritan's Purse Children's heart project as they provide life changing surgery for children.
Eric Herzog, CMO, Infinidat
Presentation Title:
How Environmentally Friendly Are Your Current Storage Vendors?
Presentation Abstract:
It’s important to recognize that developing the best data center sustainable requires a holistic approach. Environmental considerations are important at all stages of the product lifecycle, from design to end-of-life, while in tandem not losing the solution performance. It’s equally important to enhance the sustainability of your data center by consolidating storage arrays. We challenge you to dive deeper into your environmental impact and push beyond the linear boundaries.
Author Bio:
Eric Herzog is the Chief Marketing Officer at Infinidat. Prior to joining Infinidat, Herzog was CMO and VP of Global Storage Channels at IBM Storage Solutions. His executive leadership experience also includes: CMO and Senior VP of Alliances for all-flash storage provider Violin Memory, and Senior Vice President of Product Management and Product Marketing for EMC’s Enterprise & Mid-range Systems Division.
In this dynamic session, we explore the intersection of sustainability and technological advancement within the storage industry, highlighting emerging practices and strategic innovations. As AI propels the growth of power-intensive systems, the need for sustainable storage solutions becomes paramount. Presentations will delve into sustainable measures for HDD and SSD, emphasizing energy-efficient production, operation, and end-of-life strategies, with a focus on the circular economy. Data centers are encouraged to adopt a holistic, lifecycle-oriented approach to enhance sustainability without compromising performance, underscoring the importance of consolidating storage arrays. The session will also spotlight the Circular Drive Initiative's upcoming Data Sanitization Best Practices Guide, which provides essential guidance on balancing security, compliance, and sustainability for enterprise drive reuse. Attendees will gain insights into the latest tools and methodologies for secure, sustainable drive reuse, ultimately reducing e-waste and fostering a more circular economy.
PRO
TEST-303-1:
Simulation and Failure Analysis
Ballroom E (Santa Clara Convention Center, First Floor)
Track:
Testing and Performance
Organizer:
Marilyn Kushnick, Track Organizer, FMS
Marilyn Kushnick is an Engineer and Track Organizer of the Testing Track at FMS.
Presenters:
Presentation Session Description:
Eyal Hamo, Technologist Reliability System Architect, Sandisk
Presentation Title:
Real-Time Monitoring and ML for Enhanced Storage Device Testing
Presentation Abstract:
This presentation introduces two key approaches to enhancing the reliability of storage devices through advanced testing methodologies. The first approach focuses on using real-time checkers to analyze device outputs and monitor parameters from device reports collected over time or by command sets. These checkers help identify potential bugs that may not be visible to the host but could lead to critical failures. The checker infrastructure integrates with broader validation and reliability packages for continuous monitoring and early issue detection.The second approach applies machine learning (ML) algorithms to detect outliers in device performance during reliability testing. By identifying anomalies early, devices can be directed to more targeted test activities, optimizing resource allocation and uncovering bugs earlier in the qualification process. Additionally, we will discuss an automatic failure analysis (FA) system designed to streamline failure investigations by automatically collecting, organizing, and highlighting critical data for the FA team.This system reduces analysis time and generates reports for product owners, suggesting similar issues when no failure is detected
Author Bio:
With over 10 years of experience in Validation and Reliability Software Engineering, I’ve progressed from Validation Engineer to Product Owner and subsequently to Validation and Reliability Architect.
I focused on embedded storage systems and real-time applications in the automotive and mobile industries.
I specialize in validation methodologies, system integration, team leadership, and developing strategies that support comprehensive product verification and performance-driven solutions.
As Validation System and Reliability Architect at Western Digital/Sandisk, I lead validation strategies and processes from kickoff to release, ensuring test traceability and defining strategies for product features.
I manage product execution, oversee failure analysis, and resolve complex technical issues.
While at WD/Sandisk, I’ve been granted six patents in storage solutions.
I also led reliability validation initiatives, optimized test flows, defined an automated failure analysis system, mentored teams, led as a product owner and worked on audits and certifications, including IATF and ASPICE.
I hold a Bachelor’s in Software Engineering and a Master’s in Computer Science.
Wade Chen, Software Engineer - Advanced, Siemens EDA
Presentation Title:
Accelerating GFD RTL Verification: A lightweight Host-to-GFD Framework
Presentation Abstract:
The CXL fabric architecture offers a novel solution for building robust and composable rack-level systems. Based on this architecture, the G-FAM Device (GFD) is a highly scalable memory device and must be attached to a PBR CXL switch, However, The CXL fabric discovery process and further configuration involve numerous steps in which CCI commands are issued to CXL switches and GFDs. These are deemed not much to be related to a GFD RTL verification.
The challenge of GFD hardware verification lies in the essential features related to PBR. If we had to construct a full testbench with multiple hosts, CXL switches, and GFDs, it would take significantly more time and effort to ramp up; also, the RTL simulation time would be much longer.
To address this challenge, Siemens CXL VIP offers a lightweight verification framework in which a Host VIP connects directly to GFD DUT without Fabric Switch in between. Host VIP provides backdoor knobs and callbacks to emulate CXL fabric, achieving direct communication with GFD to simulate PBR traffic. The approach also enables users to verify GFD by reusing the existing compliance tests to reduces the verification closure time.
Author Bio:
Wade Chen holds a master’s degree in communication engineering from National Taiwan University and specializes in PCIe/CXL IC Design Verification. As the senior verification engineer and the project leader of the Siemens Avery CXL VIP Team, he brings 5 years of experience in PCIe/CXL VIP development and support. His main responsibilities include scheduling feature roadmaps aligned with CXL Specification updates, providing high-quality support to IC Design customers, developing the CXL Compliance test suite, and managing team members.
Karthik Balan, Associate Director, Samsung Electronics
Presentation Title:
Shift Left CXL Product Readiness & Validation via OpenCXL
Presentation Abstract:
OpenCXL tools is a growing ecosystem of open-source frameworks and utilities designed to facilitate the development, testing and validation of CXL-enabled devices. This tool is instrumental in simulating and emulating CXL-based systems, enabling developers to design scalable, high-performance interconnects that meets demands of modern workloads like AI, HPC and could computing.
In this session, we would share information on usage, results of OpenCXL's in Shift-left readiness of CXL.mem protocol validation in CXL drives. Also, insight on the organization's edge to achieve parallel development & validation infra at same time. Features like - Software Compatibility, Fabric Manager ,MLD management, Debug memory pooling, Coherency mechanisms and many more can be developed and tested with the use of Open Source Software.
Additionally, will have insight on latest development for CXL in Linux Kernel that provides a robust platform for integration and testing of emulated CXL switches that is completely in open-source environments. This talk gives an understanding on how open source (like OpenCXL) helps in shift left of CXL component and test infra readiness ahead of real ASIC product.
Author Bio:
Karthik is a Associate Director at Samsung Electronics(SSIR), he has experience of 20 years in Embedded System Testing and last 12 years in Memory Solutions Tests for NVMe, SAS, CXL, etc. He is currently works on architecting the test coverage and test solutions for NVMe Enterprise SSDs. Driving towards shift-left approach and open source enablement for NVMe SSD qualifications
Bill Gervasi, Principal Memory Solutions Architect, Monolithic Power Systems
Presentation Title:
You Can’t Fix What You Can’t Measure
Presentation Abstract:
Telemetry gathering during system runtime allows systems managers to track not just the health of their systems, but allows for predicting some future failures before they happen. This trend is entering the memory domain. With health metrics combined with telemetry processing, systems can correlate seemingly disparate factors such as device temperature, access patterns, correctable and uncorrectable errors, post package repair, and use long term logging procedures to connect the dots on these factors. This talk examines trends in adding metrology to systems to enhance system health and reduce costs.
Author Bio:
Mr. Gervasi has nearly 5 decades of experience in high speed memory subsystem definition, design, and product development. He piloted the definition of Double Data Rate SDRAM since its earliest inception, authoring the first standard specification, and created the Automotive SSD standard. With MPS, Bill is driving some of the memory and storage system management mechanisms for a post-quantum world. He received the JEDEC Technical Excellence award, their highest honor, in 2020.
This session delves into innovative methodologies and technologies aimed at enhancing the reliability and performance of modern data storage and processing systems. A common theme across the presentations is the integration of advanced testing and validation frameworks, with a particular emphasis on machine learning and open-source tools, to optimize resource allocation and expedite issue detection. The utilization of real-time checkers and telemetry data for predictive maintenance exemplifies the proactive approach to system health management. Additionally, the session highlights the transformative potential of CXL (Compute Express Link) technologies, showcasing tools like OpenCXL that facilitate scalable, high-performance interconnects essential for handling demanding workloads. Siemens' CXL VIP framework further streamlines verification processes, reducing time and complexity by offering lightweight simulation environments. Collectively, these presentations underscore the importance of robust validation infrastructures and telemetry in achieving reliable, efficient, and cost-effective technology ecosystems.
01:15 PM to 01:25 PM
Open
BRK:
Thursday PM Refreshment Break
Main Lobby/Great America Lobby (SCCC, First Floor/Great America Meeting Rooms, Second Floor)
Track:
General Events
General Event Description:
Description Not Available
01:25 PM to 02:30 PM
Open
AIML-304-1:
Panel: Driving Interconnects: Memory and Storage Fabrics for New AI/ML Workloads
Ballroom A (Santa Clara Convention Center, First Floor)
Track:
AI and ML Applications
Organizer:
David McIntyre, Director Product Planning, Samsung Electronics
David McIntyre focuses on computational storage acceleration solutions development and strategic business enablement for cloud to edge applications including AI inference/video analytics, database processing and blockchain networks. He has held senior management positions with IBM, Samsung, Xilinx, Intel (formerly Altera) and at Silicon Valley startups. He has consulted for institutional investors including Fidelity, Goldman Sachs and UBS. David is a frequent presenter and chairperson at the Flash Memory Summit and other technical conferences including SNIA.
Chairperson:
Siamak Tavallaei, Sr. Principal Engineer, Samsung
Siamak Tavallaei is Sr. Principal Engineer at Samsung, Systems Architecture. He joined the CXL effort as a founding member of the CXL Consortium and co-chair of the Technical Task Force (TTF) in 2019 to develop the CXL 2.0 specification. He has served on the CXL Board of Directors and as the CXL President. In 2016, he joined Open Compute Project (OCP) as a co-lead of Server Project. He later served as the Incubation Committee Representative for the Server Project and Steering Committee where he drives open-sourced modular design concepts for integrated hardware/software solutions for massively-scaled systems. Previously, he has served as Distinguished Technologist at HP, Senior Principal Architect at Microsoft Azure, and Chief Systems Architect at Google.
Panel Members:
Panel Session Description:
Manoj Wadekar, AI Systems Technologist, Meta
Manoj Wadekar is an AI Systems Technologist at Meta and a Board Member at JEDEC.
Ardavan Sherafat, AI/ML Researcher, Cal Poly Pomona University
AArdavan Sherafat is an AI/ML researcher from Cal Poly, Pomona University.
Samir Rajadnya, Principal Architect, Microsoft Azure
Samir Rajadnya is a Principal Architect at Microsoft, Azure.
Kurt Keville, Chief Architect, semiconDx
Kurt works in Research Computing and Systems Design. His MIT thesis work was on energy-efficient supercomputing and to that end, he has investigated research enabling and accelerating technologies that can unlock new programming paradigms for grand challenge problems. Kurt currently works on a cluster model which is a notional Tactical Datacenter design with strong focus on energy efficiency, composability, and memory management.
AI/ML applications demand on memory sub-system is driving higher memory performance, lower latency, and increased capacity requirements. Memory-tiering supports the first two metrics by offering different memory technologies; however, the traditional method of addressing a larger virtual memory footprint has relied on storage-class solutions such as NVMe SSDs. Innovations in interconnect standards such as CXL and UALink as well as advancements in PCIe and Ethernet physical layers help support higher date-movement requirements, while innovations in memory buffer-caching with SSDs enable increased virtual-memory capacity without significantly impacting latency. This panel provides different perspectives on the role of storage and related memory architectures that support the growth in AI/ML application requirements.
PRO
CXLT-304-1:
CXL Verification
Ballroom B (Santa Clara Convention Center, First Floor)
Track:
CXL
Organizer:
Anil Godbole, Sr. CXL Mktg Manager, Intel
Anil Godbole is a CXL Marketing Working Group Co-Chair and Senior Marketing Manager for Intel’s Xeon Product Planning and Marketing Group. His domain is in Memory, Serdes Technologies & Associate Protocols (DDRx, CXL, PCIe, Ethernet, etc.). Previously, he held a position as Design Engineer in CPU-support ASICs, FPGAs.
Presenters:
Presentation Session Description:
Manjunaatha Harapanahalli, Silicon Firmware Development Engineer, Intel Corporation
Presentation Title:
Use Cases for CXL RAS Firmware-First Error Handling
Presentation Abstract:
Highlight the CXL RAS specific Firmware First error handling use cases that are implemented for the CXL specification which is generic in nature. When developing the support for the CXL RAS Firmware First, encountered different use cases that needs to be solved to implement the firmware and customer problems.
The use cases resolution would involve the design and implementation of the firmware to handle them. Like usage of primary and secondary Mailbox to overcome the IHV early adoption in engineering/debug effort. Common error signaling protocols usage for protocol errors. GUID and UUID usage in firmware on both CPU/host side, CXL devices and Operating system. Interaction communication failures between the CPU and CXL devices during boot time and run time that needs to be notified to users/operating system. Techniques used to improve the SMI latency. Error pollution use cases handling on both protocol, Memory error firmware notification (MEFN) and Flat2LM cases.
Author Bio:
My current position is to architect, design and develop the system firmware for Intel silicon mainly for Data Center products. Am the owner for CXL RAS firmware design and development.
I had worked mainly in embedded and firmware design and development for silicon in different domains like EV, Automotive and Data Centers.
I have graduated from San Diego State University in Computer Science.
Po Chun Wang, VIP Designer, Siemens Digital Industries Software
Presentation Title:
A Comprehensive Verification Guide for Extended Meta Data
Presentation Abstract:
Compute Express Link (CXL) is well known for its high performance and low latency connection for CPU, Accelerator and memory expander. However, as memory access speed increasing and multi-level CXL fabric being introduced to enhance resource utilization, the original 2-bit encoding scheme for Meta Data is no longer sufficient. To address the limitation, Extended Meta Data (EMD) tranfer is introduced in CXL 3.1 specification.
This paper will present comprehensive protocol checkers, corner case studies and error injection scenarios to cover the verification of Extended Meta Data and related features thoroughly. These examinations can serve as a complementary test plan on top of the one defined in CXL-3.1 chapter 14. We will also highlight some areas not well defined in 3.2 spec: for example, there is no clear definition of the RAS (Reliability, Availability, and Serviceability) error reporting for Extended Meta Data errors and the interaction with Late-Poison feature. We will address this gap by providing insights into various Extended Meta Data error scenarios, based on the discussions we had with CXL Consortium experts.
Author Bio:
Experienced VIP Designer with three years of expertise, specializing in CXL TL/DL layer and CXL Cache/Memory Protocol Interface implementation.
Heetashi Arora, Lead Member Consulting Staff, Siemens EDA
Presentation Title:
Enhancing Security in CXL: IDE and TSP Verification
Presentation Abstract:
This abstract aims to address the verification challenges associated with CXL Integrity and Data Encryption (CXL IDE) and Trusted Service Providers (TSPs), proposing methods to simplify these processes. CXL IDE protects the CXL link, ensuring the security of data in transit, while TSPs extend this security to CXL memory.Virtualization-based Trusted Execution Environments (TEEs) are used to host confidential computing workloads isolated from hosting environments.
Verification scenarios for CXL IDE and TSPs include:
1. Coherence Maintenance: Ensuring HDM-H and HDM-DB maintain coherence when TEE opcodes are used.
2. Mismatch Cases: Validating access to the Trusted Execution (TE) state with incorrect TEE intent across different opcodes and ensuring all rules of TE State Change and Access Control are followed.
3. Memory Encryption and Partial Write: Examining scenarios involving initiator-based memory encryption and partial write operations.
4. CKID Types Verification: Verifying target behavior for different CKID (CXL Key ID) types.
By addressing these challenges, this paper aims to provide valuable insights and practical solutions for developers and organizations striving to optimize
Author Bio:
Heetashi Arora is a Lead Member of Consulting Staff for CXL VIP Development at Siemens, bringing over 11+ years of experience in the EDA industry. She has extensive expertise in CXL and PCIe generations, as well as background of simulation-to-emulation VIPs. Prior to her work in VIP development, Heetashi focused on emulation solutions and its performance aspects. She holds a Bachelor's degree in Electronics and Communication
This session delves into the intricacies of Compute Express Link (CXL) technology, focusing on the critical aspects of error handling, data integrity, and security. Across multiple presentations, the common themes emerge around enhancing CXL's reliability, availability, and serviceability (RAS) through innovative firmware solutions and protocol enhancements. The discussions outline the implementation of Firmware First error handling, highlighting the use of GUID and UUID in error notification and the challenges of maintaining low SMI latency in a complex ecosystem. The session also explores the introduction of Extended Meta Data (EMD) in the CXL 3.1 specification, addressing the limitations of previous encoding schemes and proposing comprehensive verification strategies to ensure robust error reporting and interaction with features like Late-Poison. Furthermore, the session addresses the verification challenges associated with CXL Integrity and Data Encryption (CXL IDE) and Trusted Service Providers (TSPs), emphasizing the importance of coherence, access control, and encryption in maintaining secure and efficient CXL operations. Collectively, these presentations offer a nuanced perspective on optimizing CXL's performance and security, providing attendees with valuable insights and practical solutions for advancing their CXL implementations.
PRO
DCTR-304-1:
High-Performance Storage for the Data Center
Ballroom F (Santa Clara Convention Center, First Floor)
Track:
Data Center Storage and Memory
Chairperson:
Anthony Constantine, Distinguished Member of Technical Staff, Micron Technology
Anthony Constantine is a Distinguished Member of the Technical Staff at Micron Technology responsible for storage standards within the Storage Business Unit. He is involved through authoring or contributing in various industry organizations including NVMe, SNIA, JEDEC, PCI-SIG, and OCP. Anthony has over 24 years of experience in the technology industry with an expertise in memory, storage, physical interfaces, low power technologies, and form factors. He earned a BS in Electrical Engineering from UC Davis.
Organizer:
Jonathan Hinkle, Senior Director - Azure Memory and Storage Pathfinding, Microsoft
Jonathan Hinkle is Senior Director - Azure Memory and Storage Pathfinding at Microsoft. He previously was In Micron's Storage Business Unit, where he investigated new technology and products, both internally as well as with customers and partners. He was previously Executive Director and Distinguished Researcher of System Architecture at Lenovo, where he led their research of datacenter computing architecture. Jonathan is an industry leading technical expert in memory, storage devices, and data center systems architecture with over 24 years of experience. In the JEDEC standards organization, Jonathan serves on the Board of Directors as Vice-Chair of Marketing and Chairs the CXL Memory Task Group, standardizing CXL-attached memory devices. He also invented and drove the first development of the EDSFF 1U Short (E1.S) NVMe drive, the VLP DIMM, and NVDIMM Persistent Memory. He has generated more than 34 granted or pending patents, and earned BS and MS degrees in Computer Engineering from North Carolina State University.
Presenters:
Presentation Session Description:
kyoungtae Kim, eSSD QE Eng'r, SK hynix
Presentation Title:
Assessing the Stability of SSD in Immersion Cooling
Presentation Abstract:
As datacenters face increasing energy consumption and cooling costs, alternative cooling solutions such as liquid cooling and immersion cooling have gained significant attention. While these methods offer promising efficiency improvements, their impact on SSD stability and reliability remains a critical concern. This study presents an in-depth assessment of SSD behavior in immersion cooling environments, comparing single-phase and two-phase cooling liquids. By analyzing electrical performance and visual characteristics, we identify key factors influencing SSD reliability under these emerging cooling technologies.
Through extensive testing and evaluation, this research provides valuable insights into SSD performance in immersion cooling scenarios. The findings aim to support the industry in optimizing storage solutions for next-generation datacenters, ensuring long-term reliability and operational efficiency in extreme cooling conditions. This presentation will explore the experimental results, key observations, and potential considerations for implementing SSDs in liquid-based cooling infrastructures.
Author Bio:
Kyungtae Kim is a Quality Engineer at SK hynix, specializing in SSD validation and reliability assessment. With extensive experience in enterprise SSD qualification, he has been evaluating SSD stability and performance in emerging datacenter environments. Recently, he has focused on the impact of alternative cooling solutions, such as liquid cooling and immersion cooling, on SSD reliability. Through comprehensive testing and analysis, he provides key insights into optimizing SSD performance for next-generation data centers.
Johann Lombardi, Senior Distinguish Technologist, HPE/Linux Foundation
Johann Lombardi is a Senior Distinguished Engineer at Hewlett Packard Enterprise (HPE) in the HPC advanced technology group and the Technical Steering Committee (TSC) Chair of the DAOS Foundation, an open-source project under the Linux Foundation. Before joining HPE, he spent 12 years at Intel as a Senior Principal Engineer and Lead Architect for the DAOS project. Earlier in his career, Johann contributed to the advancement of the Lustre parallel file system for 8 years at Bull, Cluster File System, Sun Microsystems, Oracle and Whamcloud.
Paul McLeod, Storage Product Director, Supermicro
Presentation Title:
New Storage System Architectures for Enterprise and AI Storage
Presentation Abstract:
Software-defined storage applications have traditionally been used with x86 servers. This is still the predominant CPU architecture used today for storage applications. In this presentation, we will discuss two alternative approaches to implementing software-defined storage.
The first alternative uses a JBOF (Just-a-Bunch-of-Flash) array which is powered by a DPU (Data Processing Unit) based networking adapter. The NVIDIA BlueField-3 DPU provides both the networking functions, acceleration of networking protocols and storage workloads such as erasure coding and encryption, and it also runs the storage application on the embedded Arm processor cores. This approach provides a power efficient method of delivering high performance all-flash storage.
The second approach we will discuss uses a highly integrated CPU combining two Arm core dies and integrating the DRAM on the CPU package for lower power and latency. This system uses the NVIDIA Grace CPU which has mainly been used as a GPU co-processor. The application of this processor to the software-defined workload is new.We will discuss performance results testing using a large multi-node cluster with a parallel file system.
Author Bio:
Paul McLeod has over 20 years of experience in the storage and server industry including 12 years Supermicro where he is currently a product director. He was previously a Sr. Field Applications Engineer at Supermicro and a Product Marketing Engineer at Promise Technology. Paul was an early advocate of software defined storage using industry standards and has worked with numerous customers on designing large scale server and storage implementations.
In this session, we delve into innovative approaches and technologies shaping the future of data storage and management. A common thread throughout the presentations is the focus on optimizing performance and efficiency in increasingly demanding datacenter environments. One presentation explores the evolution of software-defined storage, highlighting alternative architectures like DPU-powered JBOF arrays and NVIDIA Grace CPU integrations that promise enhanced power efficiency and performance. Meanwhile, another presentation addresses the pressing issue of datacenter cooling, assessing the impact of immersion cooling on SSD stability and reliability. The study evaluates single-phase and two-phase liquids, offering insights into optimizing storage solutions in these alternative cooling scenarios. Together, these presentations underscore the critical balance between cutting-edge hardware advancements and innovative cooling strategies, emphasizing the importance of reliability and efficiency in next-generation datacenters.
Open
DRAM-304-1:
DRAM and NAND Technology Deep Dive
Ballroom D (Santa Clara Convention Center, First Floor)
Track:
DRAM
Presenter + Organizer:
Ju Jin An, Senior Technical Staff Member, IBM
Ju Jin An is a Senior Technical Staff Member in IBM's Infrastructure Supply Chain Organization. Ju Jin has a background in silicon fabrication process R&D and manufacturing process integration through 20 years of career in the semiconductor industry. She is responsible for enabling memory sub-system for IBM power and z system. She holds a MS/Ph.D. degree in Chemical Engineering from MIT and a BS from Seoul National University.
Presenters:
Presentation Session Description:
Jinin So, Senior Direct & System Architect, Memory Architecture Group, Samsung Memory
Presentation Title:
Heterogenous Memory Opportunity with Generative AI and Memory Centric Computing
Presentation Abstract:
With the emergence of DeepSeek, the computing power and memory bandwidth required for training and inference of LLM models on GPU systems have been relieved, but the need for memory capacity has increased even more. The adoption of a new tier of memory, such as CXL, to address this memory capacity problem is essential, but there are several challenges, including an increase in data transfer energy due to the adoption of a new tier, an increase in software complexity and etc. This presentation profiles the reasoning LLM model on the latest NVIDIA system and analyzes the memory capacity shortage problem due to long context and multi-batches. Based on this, we prove the effectiveness of second-tier memory like CXL and discuss process near memory technology to overcome the problems. Finally, we share the combination technology of CXL-based computing/memory disaggregation system for scaling and pooling and CPU/CPU system.
Author Bio:
Jinin So is a Senior Director & System Architect at Samsung, responsible for developing advanced CXL products and technologies, including CMM-DC (Computing), CMM-B (Disaggregated Memory System), and SMDK (Software Stack for CXL Products). He has played a key role as the lead architect in developing multiple groundbreaking technologies, such as the world's first CXL Process Near Memory Platform (CMM-DC), CXL Memory Expander (CMM-D), and DDR-based Near Memory Process DIMM (AXDIMM) at Samsung. Jinin has excellent knowledge of computer architecture, particularly in CPU/GPU/NPU with memory subsystems, and has in-depth expertise in Intel/AMD server system configurations and memory configurations for high-performance servers. With over 10 years of experience in memory module design, system-level SI/PI/thermal analysis, and five years in Process Near Memory System Architecture design, Jinin has contributed to defining memory module product specifications within JEDEC. He holds more than 10 U.S. patents and has authored over 10 publications
Jeongdong Choe, Senior Technical Fellow, SVP, TechInsights
Presentation Title:
Memory Technology Outlook 2025 and Beyond: DRAM & NAND
Presentation Abstract:
DRAM chips are used for many applications such as DDR5, LPDDR5 or 5X, GDDR6 or GDDR6X, HBM2E/HBM3/HBM3E, and Low Latency DRAM (LLDRAM) components. Recently, the industry introduced processing-in-memory (PIM) technology for PIM-enabled High Bandwidth Memory such as Aquabolt-XL from Samsung, and SK hynix has developed GDDR6-AiM (Accelerator in Memory) which reduces data movement between memory and the CPU or GPU. CXMT in China already released G3 DDR3L, LPDDR4X, and DDR5 DRAM chips with G4, and developing G5 generations. D1c mass products will be revealed in 2025. The last generation (D1d or D1δ nodes) of the 10nm-class DRAM devices will be followed in 2026.
The next Samsung V10 will adopt hybrid bonding technology similar to the upcoming KIOXIA 218L CBA and YMTC’s current Xtacking 3D NAND products. YMTC in China keeps a hybrid bonded structure with two wafers, up to 267L (Gen5). We'll see more than 500-layer 3D NAND products in a couple of years, with more advanced low-temp HAR process and hybrid bonding technology.
Author Bio:
Dr. Jeongdong Choe is a Senior Technical Fellow and SVP at TechInsights. He has around 30 years of hands-on experience in the semiconductor industry, R&D and reverse engineering analysis on DRAM, NAND/NOR FLASH, SRAM/Logic, and Emerging Memory devices such as MRAM/STT-MRAM, PCRAM, XPoint, ReRAM, and FeRAM. He worked for SK Hynix and Samsung Electronics for over 20 years. He has manufacturing and R&D expertise in high-technology including direct experience in the ,semiconductor process flow, process integration, unit process and tools for photo-mask, photo-lithography, plasma/wet etching, CMP, deposition, implantation, diffusion and annealing. He joined TechInsights and has been focusing on technology, device, and architecture design analysis. He regularly publishes semiconductor technology-related articles on technology trends and roadmaps. He also delivers annual memory seminars, memory technology updates, keynotes, and talks at TechInsights on-/off-line seminars and global conferences.
In the rapidly advancing landscape of artificial intelligence and high-performance computing, the demand for reliable and efficient memory systems is more critical than ever. This session delves into the intersection of cutting-edge memory technologies and AI-driven applications, highlighting common themes such as memory reliability, scalability, and innovation. Presentations will explore the challenges of DRAM and NAND failures in AI applications, emphasizing the importance of error correction and system-level optimizations to enhance memory resilience. The session will also examine the latest advancements in DRAM technologies, including processing-in-memory (PIM) and hybrid bonding, which promise to enhance performance and reduce data movement inefficiencies. Furthermore, the emergence of new memory tiers like CXL addresses increasing memory capacity demands, albeit with challenges in energy consumption and software complexity. Attendees will gain insights into the transformative potential of 3D DRAM, high-bandwidth memory (HBM), and second-tier memory solutions, which are poised to redefine the landscape of memory architectures essential for the next wave of AI and data-intensive applications.
PRO
DSEC-304-1:
Quantum Resilience: The New Storage Security Frontier
Ballroom G (Santa Clara Convention Center, First Floor)
Track:
Data Security/Ransomware Protection
Organizer:
Rohan Puri, Staff Engineer, Samsung Seminconductor
"Rohan Puri serves as a Staff Engineer at Samsung Semiconductor Inc, bringing over 14 years of expertise in systems software development with a focus on file systems, storage technologies, and distributed systems. His technical leadership spans prestigious organizations including Veritas Technologies, Oracle, and various storage technology companies, where he has optimized file system performance, enhanced storage reliability, and designed advanced distributed storage solutions. Currently serving on the Conference Advisory Board for FMS'25 and as Co-industry Chair for MSST'24, he's also an active reviewer for ACM Transactions on Storage Journal and sits on Artifact Evaluation Committees for FAST'25 and OSDI'25. Rohan holds a Master's degree in Computer Science & Engineering from Pennsylvania State University and a Bachelor's in Information Technology from the University of Pune, India.
Presenters:
Presentation Session Description:
John Myung, President, KLC Group
Presentation Title:
Securing the Future: Implementing Quantum-Safe Algorithms in Solid-State Drives
Presentation Abstract:
The rapid advancement of quantum computing poses an unprecedented threat to current cryptographic systems, particularly those safeguarding data on solid-state drives (SSDs). As SSDs become ubiquitous in personal devices, enterprise storage, and critical infrastructure, their reliance on traditional encryption methods like RSA and ECC leaves them vulnerable to quantum attacks. This presentation explores the integration of quantum-safe algorithms—cryptographic techniques resistant to quantum decryption—into SSD architectures. We will discuss the urgency of this transition, evaluate leading post-quantum cryptographic candidates, and propose practical implementation strategies to future-proof SSD security.
Author Bio:
At KLC Group, Mr. Myung, leads a team of experts in encryption and authentication technologies. KLC Group has three products listed on the National Security Agency Commercial Solutions for Classified program. With more than 25 years of sales, marketing, and software engineering, Mr. Myung has in-depth experience in network security, enterprise, and cloud technologies. Besides his work with KLC Group, John is an executive in residence at CryptKloud.
Paul Suhler, Principal Engineer, SSD Standards, KIOXIA America, Inc.
Presentation Title:
Get Ready for Post Quantum Cryptography
Presentation Abstract:
Progress in quantum computing hardware and algorithms threatens the security of data and communications protected by conventional encryption algorithms. In an effort to resist these attacks, post-quantum cryptographic algorithms have been defined and more are on the way. This talk will present the ecosystem of algorithms and standards, as well as the governmental and other requirements that are making it imperative to implement these algorithms and integrate them into products in the very near future.
Author Bio:
Paul Suhler has been active in the data storage world for thirty years, working for companies which include KIOXIA, Micron, WD/HGST, and Quantum. He is a software and firmware engineer, and has managed the development of storage devices for companies such as Quantum and Adaptec. He is the chair of the IEEE Security in Storage Working Group, and has contributed to standards developed by organizations such as NVM Express, SNIA, and the INCITS SCSI (T10) and Fibre Channel (T11) committees. He served as the Deputy Director of the USC Advanced Computer Architecture Laboratory, and commanded US Army combat engineer companies in Korea and California. He holds a PhD in computer engineering from the University of Texas at Austin. He is a Life Senior Member of IEEE and a member of ACM.
Bill Gervasi, Principal Memory Solutions Architect, Monolithic Power Systems
Presentation Title:
Memory and Storage Security in a Post Quantum World
Presentation Abstract:
With the availability of quantum computers on the horizon, traditional computing devices are being challenged to increase their sophistication in securing data. Key users of data centers and data sources have issued requirements for a more secure future where they can be assured of trusted components throughout the computing fabric.
Author Bio:
Mr. Gervasi has nearly 5 decades of experience in high speed memory subsystem definition, design, and product development. He piloted the definition of Double Data Rate SDRAM since its earliest inception, authoring the first standard specification, and created the Automotive SSD standard. With MPS, Bill is driving some of the memory and storage system management mechanisms for a post-quantum world. He received the JEDEC Technical Excellence award, their highest honor, in 2020.
Luis Freeman, Technical Project Manager, Storage Device Technologies, IBM
Presentation Title:
The path to Quantum Safe and impact on the Data Storage Industry Organizations
Presentation Abstract:
In the next few years, Quantum Computers will be able to crack current Public Key Cryptography which is the basis to ensure the confidentiality, integrity and authenticity of information. The NSA has recently released the Commercial National Security Algorithm Suite 2.0 (CNSA 2.0) recommending a new set of cryptographic algorithms to address this issue as well as guidelines for implementation. In this talk, we will examine the urgency of implementing aspects of CNSA 2.0, some of the challenges of implementing them, how it affects the data storage industry and the industry standards organizations.
Author Bio:
Luis Freeman is a Technical Project Manager in the IBM Supply Chain Engineering Organization. Luis is responsible for the Selection and Qualification of Storage Devices used across IBM Products and Services. In this role, Luis interlocks with the SSD Suppliers, IBM Brand Development teams and the Storage industry to find the right storage devices to use for each product. Luis is a member of NVM Express, Open Compute Project, SNIA and DMTF organizations.
Luis Freeman got a Master’s degree in Industrial Electronics in 1999 from ITESO in Guadalajara, Mexico. Luis has been working at IBM since 1996 in multiple roles across the Supply Chain Organization.
As the era of quantum computing approaches, the security landscape faces transformative challenges, particularly concerning the protection of sensitive data across various platforms. The convergence of these presentations underscores the urgent need to transition from conventional cryptographic systems to quantum-resistant alternatives to safeguard against potential breaches by quantum computers. Central to this discourse is the adoption of the Commercial National Security Algorithm Suite 2.0 (CNSA 2.0) and the development of post-quantum cryptographic algorithms, which are imperative for future-proofing data integrity and authenticity. The data storage industry, notably SSDs, must integrate these quantum-safe techniques to mitigate vulnerabilities. With governmental and industry mandates accelerating the transition, these sessions collectively highlight the critical need for comprehensive strategies and implementations to secure data in an increasingly quantum-capable world.
Open
NETC-304-1:
Networks and Links: Advanced Topics
Ballroom C (Santa Clara Convention Center, First Floor)
Track:
Networks and Connections
Organizer + Chairperson:
Paul Borrill, Founder and CEO, DAEDAELUS
Paul Borrill is founder and CEO of DÆDÆLUS and is a leading industry expert on the foundations of resilient network and storage infrastructures
Panel Members:
Panel Session Description:
Bijan Nowroozi, Head of Ecosystem Development , Lightmatter
Bijan Nowroozi is Head of Ecosystem Development at Lightmatter and former Chief Technical Officer of the Open Compute Project Foundation. He builds industry coalitions and standards to bring photonic compute and high-bandwidth interconnects from lab to large-scale deployment. At OCP, he led open hardware and data-center specifications spanning AI/ML, networking, security, and precision timing—helping shape next-generation, time-sensitive infrastructure.
Previously a system architect at JVCKENWOOD and founder/CTO of Aerietau and SONLTE, Bijan has 30+ years at the intersection of hardware and software across signal processing, distributed systems, and wireless. He also held senior roles at Samsung and earlier engineering posts at PageNet and Nortel. His current focus is practical pathways to scale AI systems—linking compute, memory, and fabric technologies into deployable, energy-efficient platforms.
Anjali Singhai-Jain, Network System Architect, Intel
Anjali Singhai-Jain is a Network System Architect at Intel. She has been in the
networking industry for 25+ years. She is one of the key Architects of Intel
Infrastructure Processing Unit contributing heavily towards programmable packet
processing design, host interface standardization (Infrastructure Data-plane
function: IDPF), virtualization etc. She holds several key patents and invention
disclosures in Networking. On the personal side, she is passionate about human
potential to seek higher states of being.
David Johnston, Founder, Primitive Security
David brings deep technical expertise and decades of real-world standards experience. With 21 years at Intel, where he led the development of critical security technologies, including the Intel RdRand and RdSeed instructions. He authored 'Random Number Generators: Principles and Practices", co-authored 'Designing to FIPS-140'. He helped shape the NIST SP800-90 series of standards . David has worked on security in standards 802.1, 3, 11 and 16, and from FIFO to USB with a focus on link-layer security. He founded Primitive Security Consulting, specializing in secure hardware, ESV and FIPS-140 certification.
Pankaj Mehra, Professor of Research in Computer Science and Engineering , Ohio State University
Pankaj Mehra is Professor of Research in Computer Science and Engineering department at The Ohio State University. He founded Elephance Memory, a company that builds software to optimize disaggregated data center memory for data infrastructure and applications. Pankaj has held executive positions in the Memory industry since 2013 when he took over as SVP and WW CTO of Fusion-io, later serving as VP and Senior Fellow at both acquirers SanDisk and Western Digital. Pankaj Mehra led SmartSSD (as VP of Product Planning) and other workload-optimized flash storage products (as VP of Storage Pathfinding) at Samsung, for which he and his team of 10 received Samsung's prestigious R&D Award in 2019. SmartSSD went on to win the CES R&D Innovation Award in 2021. Previously at Hewlett-Packard, Pankaj was promoted to HP Distinguished Technologist in 2004 for his pioneering work on RDMA-attached persistent memory devices and filesystems. Later he founded HP Labs Russia and served as its Chief Scientist until 2010. He is also the founder of startups IntelliFabric, Whodini and AwarenaaS. Pankaj's international experience spans academia, industry and government. His publications include 3 books and over 100 papers and patents. Pankaj holds Ph.D. in Computer Science from The University of Illinois at Urbana-Champaign.
The Link Wars Debate: Proprietary, Open and Atomic Fabrics in AI Networking}. AI-scale infrastructure is moving past traditional switches and routers. The future lies in high-speed links: NVLink, UALink, AELink, PCIe/CXL and Ultra-Ethernet -- delivering memory semantics, programmability, and deterministic messaging. Join this high-energy debate as experts square off on proprietary vs open vs atomic link fabrics, debating which model should power next-generation AI systems--and why it matters for scalability, correctness, and vendor choice.
PRO
QLCP-304-1:
Multi-Level Cells Part 2
Ballroom E (Santa Clara Convention Center, First Floor)
Track:
QLC and PLC
Organizer:
Brian Berg, President, Berg Software Design
Through his Berg Software Design consultancy, Brian provides hardware and software design and development services for storage and interface technologies in consumer electronics, including flash memory, NVMe and USB. Brian has been a developer, project lead, industry analyst, seminar leader, technical marketer and technical writer. He has participated in over 80 conferences as a speaker, session chair and conference chair. He has also worked extensively with intellectual property and patents, particularly in the storage arena. He is active as an IEEE officer and volunteer, including as past Chair of the Santa Clara Valley Section, Director and past Chair of the Consultants Network of Silicon Valley, Region 6 IEEE Milestone Coordinator, Chair of the SCV Technical History Committee, and past Liaison for the Women in Engineering Affinity Group. Brian is an IEEE awards recipient, including the 2017 Outstanding Leadership and Service to the IEEE within Region 6, the 2017 IEEE-USA Professional Leadership Award for Outstanding Service to the Consulting and Electrical Engineering profession, and the 2012 Outstanding Leadership and Professional Service Award for Region 6.
Presenters:
Presentation Session Description:
Sarika Mehta, Senior Solutions Architect, Solidigm
Presentation Title:
Best practices to minimize QLC SSD drive rebuild time and write amplification
Presentation Abstract:
High capacity QLC NVMe SSDs are getting very popular, thanks to their density and power optimization. As capacity keeps growing, drive rebuild time becomes a concern when deploying QLC drives.
In this presentation, we’ll showcase the results of tests on 9x D5-P5336 QLC 61.44TB together with our partner, Solidigm, demonstrating how it is possible to minimize drive rebuild time by implementing a proper data protection scheme. We deployed the drives in RAID level 5 using different RAID engines, emulated a drive failure and measured the drive rebuild time. We learned some best practices that we’ll share with the audience to minimize drive rebuild time.
The analysis also measured the impact of drive rebuild to the endurance of the drive, by measuring the write amplification factor (WAF), the parameter that measures the ratio of the amount of data written to the drive by the host to the amount of data effectively written to the NAND media by the drive controller. The test showed the possibility to minimize write amplification during the drive reconstruction process. This makes deploying massive capacity drives an effective solution even for mission critical applications.
Author Bio:
Sarika Mehta is a Senior Storage Solutions Architect at Solidigm, bringing over 16 years of experience from her tenure at Intel’s storage division and Solidigm. Her focus is to work closely with Solidigm customers and partners to optimize their storage solutions for cost and performance. She is responsible for tuning and optimizing Solidigm’s SSDs for various storage use cases in a variety of storage deployments that range from direct-attached storage to tiered and non-tiered disaggregated storage solutions. She has diverse storage background in validation, performance benchmarking, pathfinding, technical marketing, and solutions architecture.
Dmitry Livshits, Chief Executive Officer, Xinnor
Presentation Title:
Best practices to minimize QLC SSD drive rebuild time and write amplification
Presentation Abstract:
High capacity QLC NVMe SSDs are getting very popular, thanks to their density and power optimization. As capacity keeps growing, drive rebuild time becomes a concern when deploying QLC drives.
In this presentation, we’ll showcase the results of tests on 9x D5-P5336 QLC 61.44TB together with our partner, Solidigm, demonstrating how it is possible to minimize drive rebuild time by implementing a proper data protection scheme. We deployed the drives in RAID level 5 using different RAID engines, emulated a drive failure and measured the drive rebuild time. We learned some best practices that we’ll share with the audience to minimize drive rebuild time.
The analysis also measured the impact of drive rebuild to the endurance of the drive, by measuring the write amplification factor (WAF), the parameter that measures the ratio of the amount of data written to the drive by the host to the amount of data effectively written to the NAND media by the drive controller. The test showed the possibility to minimize write amplification during the drive reconstruction process. This makes deploying massive capacity drives an effective solution even for mission critical applications.
Author Bio:
Dmitry is the Chief Executive Officer at Xinnor. For over 20 years, Dmitry has been deeply involved in mathematical research and storage software development. He received his MS degree in Computer Science in 1998, PhD in mathematics in 2002 and graduated Harvard Business School in General Management Program in 2012.
Unsang Lee, Principal Engineer, SK hynix
Presentation Title:
Programming Efficiency Improvement Algorithm for QLC Devices
Presentation Abstract:
As generations of NAND Flash progress, the cell size decreases, and consequently, the decrease in virgin Vt characteristics leads to a reduction in programming efficiency. In particular, QLC devices require a wider program-erase window budget compared to TLC devices and demand higher reliability. Consequently, the tunnel oxide is manufactured to be thicker, making the degradation of programming efficiency a more significant issue.
In this talk, I will explore various algorithms that can improve programming efficiency, and compare each algorithm to propose a method suitable for Multi-Level Cell operation.
Author Bio:
NAND QLC Cell Characteristic, Failure Analysis, NAND QLC Operation Optimization
Kevin Hsu, Applications Engineering Senior Manager, KIOXIA
Presentation Title:
Enabling Higher Capacity Storage with QLC UFS
Presentation Abstract:
Today’s smartphones are embedded with a bevy of advanced features like video editing, high resolution cameras, high end gaming, and AI, which continues to evolve. The demand for higher capacity storage will continue to grow. Advanced technology like Quad Level Cell (QLC) NAND is already available in some Flash devices, including Universal Flash Storage (UFS).
QLC UFS capacities will continue to expand and enable higher capacity storage without sacrificing performance as a result of the WriteBooster design architecture. This concept of higher capacity and comparable performance will lead to the adoption of QLC UFS in mid to high end smartphones and other applications in the near future.
Author Bio:
Kevin is a Senior Manager in the Managed Flash Applications Engineering group at KIOXIA America Inc. He has worked in the memory industry for over 25 years and held various roles in engineering, marketing, and sales. He is the technical support lead of the Managed Flash product line for all of North America and has worked with key customers in the mobile, networking and automotive space. He holds a BSEE degree from UCLA.
This session cohesively explores the progressive advancements and applications of Quad Level Cell (QLC) NAND technology across various platforms and its implications for efficiency, reliability, and capacity. Presentations converge on the theme of optimizing QLC performance, addressing challenges such as reduced programming efficiency due to smaller cell sizes and thicker tunnel oxides, and proposing algorithms suited for Multi-Level Cell operations. The session also delves into the deployment of high-capacity QLC NVMe SSDs, with a focus on minimizing drive rebuild time and write amplification factor (WAF), ensuring endurance and reliability in mission-critical applications through robust data protection schemes. Furthermore, the adoption of QLC NAND in smartphones, particularly through Universal Flash Storage (UFS), is highlighted, emphasizing its potential to deliver higher capacity without performance trade-offs, thus meeting the expanding demands of advanced mobile applications. Collectively, these presentations underscore the transformative impact of QLC technology in enhancing storage solutions across diverse domains.
Open
SSDT-304-1:
Error Correction, Reliability, and Telemetry Techniques for SSDs
GAMR-1 & 2 (Great America Meeting Rooms, SCCC 2nd Floor)
Track:
SSD Technology
Chairperson:
Mats Öberg, Associate Vice President, Marvell
Mats Öberg is Associate Vice President of DSP Architecture at Marvell. He currently leads research and development of signal processing for storage products. He is inventor and co-inventor of over 100 patents in the areas of magnetic recording, solid state storage, optical recording, and automotive ethernet. Mats earned his PhD in Electrical Engineering from University of California, San Diego.
Organizer:
Erich Haratsch, Senior Director Architecture, Marvell Semiconductor
Erich Haratsch is the Senior Director of Architecture at Marvell, where he leads the architecture definition of SSD and storage controllers. Before joining Marvell, he worked at Seagate and LSI, focusing on SSD controllers. Earlier in his career, he contributed to multiple generations of HDD controllers at LSI and Agere Systems. Erich began his career at AT&T and Lucent Bell Labs, working on Gigabit Ethernet over copper, optical communications, and the MPEG-4 video standard. He is the author of over 40 peer-reviewed journal and conference papers and holds more than 200 U.S. patents. A Senior Member of IEEE, Erich earned his MS and PhD degrees from the Technical University of Munich, Germany.
Presenters:
Presentation Session Description:
Ilia Maller, Technology Strategist, Phison Electronics
Presentation Title:
Taking NAND Past End-of-Life: Dynamic NAND Recovery
Presentation Abstract:
This presentation shows how to extend the endurance of TLC nand flash to PE 11K and QLC nand flash to PE 3K with advanced error recovery flow, which means we can use client grade nand flash to match enterprise product requirement.
Dynamic Recovery Sequence and Online Read Level Tracking are introduced for better performance and reliability. Dynamic Recovery Sequence is run-time self-tuning recovery sequence to minimize retry trigger rate. The read performance of SSD will be more stable and the performance drop will be detected and recovered. Online Read Level Tracking is an efficient and accurate nand flash status monitoring process. Error bits of nand flash is well controlled. No matter what kinds of nand flash failure mode (Retention, Disturb, Cross-Temperature...), the drive will not suffer from data loss issue during drive power-on state.
To show the benefit of these 2 special features, real drive testing result will be demonstrated in this presentation.
Author Bio:
Ilia Maller is a storage industry veteran with deep expertise in SSD architecture, firmware, and system design. At Phison Electronics, he drives technology strategy for next-gen SSDs, including solutions for space, high-performance, and high-endurance applications. His prior roles at Micron, Intel, Samsung, and SanDisk include leading development of flagship NVMe and SAS SSDs, building global engineering teams, and shaping foundational NAND and PCIe firmware architectures.
Muhammed Ceylan Morgul, Graduate Research Assistant, University of Virginia
Presentation Title:
A Second Life for Flash With Page Isolation
Presentation Abstract:
Flash memories are widely preferred despite their relatively low endurance limitations. One of the dominant reasons for flash memory’s low reliability is cell-to-cell program interference. Programming a target cell also alters the threshold voltages of neighboring cells. These effects become more prominent as blocks age, resulting in them being abandoned after reaching their end of life due to unrecoverable errors. We propose the Page Isolation technique to reuse some pages of aged blocks that are otherwise abandoned. The key idea is to isolate some pages to enable others to continue to be used, reaching at least 6.25× more endurance than their projected lifetime. The technique suggests skipping every other page (more pages for older) in the process of declaring free page addresses after the garbage collection for the blocks that are reaching an uncorrectable error count. The simplicity of the technique allows for easy implementation in the Flash Translation Layer without increasing computational complexity. The Page isolation lowers penalty of capacity loss due to the retirement of the aged-blocks by enabling to use some pages of these blocks beyond their anticipated lifetime.
Author Bio:
Muhammed Ceylan Morgul is currently a Ph.D. candidate in Electrical Engineering at the University of Virginia. He received his BSc degree in Electronics and Communication Engineering in 2014, and MSc degree in Electronics Engineering in 2017 at Istanbul Technical University. He has been the principal investigator of one TUBITAK, and researchers of EU-H2020-RISE, SRC-JUMP, and TUBITAK projects, in Turkey, the USA, France, Portugal, and Malaysia. He is an author of more than 15 peer-reviewed research papers. His current research interests include the reliability of memory technologies, processing in memory, and emerging computing.
Mao-Ruei Li, Project Deputy Manager, Silicon Motion
Presentation Title:
An ultra-low-power LDPC decoder application in SLC mode
Presentation Abstract:
As NAND technology continues to advance, both TLC and QLC NAND have become increasingly popular. While these NAND types offer higher storage capacities, their speeds are slower compared to SLC and MLC NAND. To address this performance gap, SLC mode is supported in NAND technology, providing a high-efficiency and reliable user experience.
NAND operating in SLC mode experiences fewer errors, and in some cases, no errors at all. As a result, the controller does not require a robust error-correcting code (ECC) for error recovery, leading to potential power savings. SMI has developed a low-power LDPC algorithm and corresponding architecture to optimize performance under these conditions.
Author Bio:
Mao-Ruei Li is a Project Deputy Manager of Storage Research Department II at Silicon Motion. Prior to this role, he focused on a VLSI architecture of SERDES. He received the Ph.D. Degrees in electrical engineering from Nation Tsing Hua University. His research in high speed SERDES and error correcting codes, including encoding/decoding algorithms, VLSI architectures. Currently, he is dedicated to developing an efficient VLSI architecture for LDPC codecs tailored for NAND applications.
Devesh Rai, Senior Strategic Marketing Manager, KIOXIA America, Inc
Presentation Title:
Data Scrubbing and Rebuild in a High-capacity SSD Environment
Presentation Abstract:
Storage solutions are moving to use high-capacity drives to increase storage capacity. At the same time, storage solutions deploy various method to detect errors early and correct early as per supported fault tolerance levels. In these solutions with high-capacity SSDs, which tend to use flash with less endurance, it is imperative to deploy an efficient error detection and correction method. Offloading data scrubbing and rebuild offers an efficient mechanism, which is scalable and an optimal use of in-system resources.
Author Bio:
Devesh Rai has held senior software engineer positions over the past 20 years. Devesh’s extensive experience includes designing and developing host I/O stack, distributed file system, DRaaS, and firmware for NVMe SSDs.
This session explores innovative strategies to enhance the reliability and endurance of flash memory technologies, focusing on overcoming inherent limitations associated with cell-to-cell interference, error recovery, and endurance constraints in high-capacity NAND solutions. Presentations converge on the theme of optimizing flash memory performance through techniques such as Page Isolation, which reclaims usable pages from aged blocks, and the deployment of SLC mode to reduce error rates and power consumption. Additionally, advanced methods like Dynamic Recovery Sequence and Online Read Level Tracking are highlighted for their ability to extend the lifespan of TLC and QLC NAND flash, aligning them with enterprise standards. The session underscores the importance of efficient error detection and correction mechanisms to improve the longevity and stability of high-capacity SSDs, paving the way for sustainable, high-performance storage solutions in evolving digital environments.
02:30 PM to 03:45 PM
Open
SPEC-305-1:
"Ask Anything" Closing Session
Ballroom E (Santa Clara Convention Center, First Floor)
Track:
Special Sessions
Organizer + Chairperson:
Jean Bozman, President, Cloud Architects Advisors
Jean S. Bozman is President of Cloud Architects Advisors, a market research and consulting firm focused on hardware and software for enterprise and hybrid multi-cloud computing. She analyzes the markets for servers, storage, and software related to datacenters and cloud infrastructure. A highly-respected IT professional, she has spent many years covering the worldwide markets for operating environments, servers, and server workloads. She was a Research VP at IDC, where she focused on the worldwide markets for servers and server operating systems. She is a frequent conference participant as a speaker, chairperson, and organizer at such events as Flash Memory Summit, OpenStack, and Container World. She is often quoted in a variety of publications including BusinessWeek, Investor’s Business Daily, the Los Angeles Times, CNET, Bloomberg, and Reuters. Ms. Bozman has also been VP/Principal Analyst at Hurwitz and Associates and Sr Product Marketing Manager at Sandisk. She earned a master’s degree from Stanford.
Panel Members:
Panel Session Description:
Eric Herzog, CMO, Infinidat
Eric Herzog is the Chief Marketing Officer at Infinidat. Prior to joining Infinidat, Herzog was CMO and VP of Global Storage Channels at IBM Storage Solutions. His executive leadership experience also includes: CMO and Senior VP of Alliances for all-flash storage provider Violin Memory, and Senior Vice President of Product Management and Product Marketing for EMC’s Enterprise & Mid-range Systems Division.
Charles Sobey, Chief Scientist, ChannelScience
Chuck Sobey is the General Chair of Chiplet Summit. He leads the Organizing Committees and identifies key trends, sessions, and speakers. Chuck is also Chief Scientist of ChannelScience, where he secured ~$3M in seed funding to develop a multi-format magnetic tape reader to access rare and deteriorating data sets. These data sets will be used for domain-specific training of AI/ML models, such as for monitoring data for nuclear nonproliferation efforts globally. Chuck earned an MS in electrical and computer engineering from University of California, Santa Barbara (UCSB), a BS from Carnegie Mellon University, and holds 8+ US patents.
Brian Rea, UCIe Marketing Work Group Chair, UCIe Consortium
Brian Rea is a senior technologist in the industry initiative and technology enabling team at Intel and is the Marketing Working Group Co-Chair for the UCIe Consortium. Brian has held engineering, marketing, and strategic planning roles bringing products with new technologies to market including USB, Gigabit Ethernet, PCIe, and CXL. His passion is working with customers and partners to enable ecosystem innovations in silicon, hardware, and software. Brian holds an MBA from the University of Washington and a BSEE from the University of Texas at Austin.
Dave Eggleston, Sr Business Development Manager, Microchip Technology
Dave Eggleston is Sr. Business Development Manager at Microchip. Dave's extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at Sandisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.
Tom Coughlin, FMS General Chair, FMS: The Future of Memory and Storage
Tom Coughlin, FMS General Chair, is President, Coughlin Associates. Tom is a digital storage analyst and business/ technology consultant with over 40 years in the data storage industry with engineering and senior management positions. Coughlin Associates consults, publishes books and market and technology reports and puts on digital storage and memory-oriented events. He is a regular contributor for forbes.com and M&E organization websites. He is an IEEE Fellow, 2025 IEEE Past President, Past-President IEEE-USA, Past Director IEEE Region 6 and Past Chair Santa Clara Valley IEEE Section, and is also active with SNIA and SMPTE. For more information on Tom Coughlin go to www.tomcoughlin.com.
Kevin Yee, Sr. Director of IP and Ecosystem Marketing, Samsung Foundry, Samsung Foundry
Kevin Yee is Sr. Director of IP and Ecosystem Marketing at Samsung Foundry, responsible for driving strategic partners for IP enablement and the SoC ecosystem. With over 30 years in the semiconductor industry, he has served a variety of senior management roles in R&D engineering, product planning, sales, marketing and business development in system, semiconductor, FGPA, IP/VIP and EDA companies. Kevin's background includes system/ASIC design, FPGA architecture, IP development and he holds several patents in design architecture. Kevin is actively involved in the HPC/AI, Automotive and Chiplet space as well as with industry standards organizations such as UCIe, OCP, CXL, JEDEC, PCI-SIG, USB I/F and MIPI, driving the latest in industry standards and technologies. He holds a Bachelor of Science in Electrical Engineering from the University of California.
Willie Nelson, FMS Program Chair/Technology Enabling Architect, FMS/Intel
With over 22 years of invaluable experience at Intel, Willie Nelson has played a pivotal role in driving the early adoption of diverse storage technologies. As a Technology Enabling Architect, he has dedicated his career to facilitating seamless transitions to cutting-edge interfaces and use cases, encompassing PCIe, CXL, NVMe, SSDs, NVDIMMs, Optane, and various other Persistent Memory devices.
In recent years, Willie has been a key asset to Jim Pappas' Ecosystem Enabling team, actively collaborating with vendors to spearhead early enablement and adoption of crucial new IO technologies. His expertise extends beyond the confines of Intel, as he actively manages and directs multiple successful industry associations and cross-industry initiatives. Willie currently serves as the Treasurer for the SNIA Compute Memory and Storage Initiative (CMSI), and also holds the position of Co-Chair of the CMSI Marketing Working Group.
Willie Nelson's commitment to technological advancement and his leadership in industry associations underscore his reputation as a forward-thinking and influential figure in the ever-evolving landscape of storage technology.
Leah Schoeb, Sr. Manager, AMD
eah Schoeb is a Sr. Manager responsible for storage strategy and architecture at AMD. She was also a senior partner at Evaluator Group, where she helps systems companies with performance engineering and optimization, market positioning, and benchmarking and also architects virtualized, containerized, and big data solutions. She has over 30 years experience in the computer industry, with the last decade in solid state technology. She was previously Acting Director for Storage Solutions Reference Architecture at Intel, where she led a team of segment managers and architects managing cross functional teams for flash and NVMe based data solutions, and reference architectures in major cloud and enterprise solution design assignments. She has prior experience as a Sr Partner at the analyst firm Evaluator Group, where she focused on storage, virtualization, and cloud infrastructure. She has held management and engineering positions at VMware, Dell, and Sun Microsystems. She has over ten publications on such subjects as optimizing Oracle, automated tiering, and solid state performance specifications, and has presented at many technical conferences including SNIA’s Storage Developer Conference and Data Storage Innovation Conference. She currently serves as as a voting member of the Technical Council and tract owner and Chairperson for Flash Memory Summit. Leah has also participated and provided thought leadership for industry groups such as the Transaction Performance Council (TPC), Storage Performance Council (SPC). She is a co-founder of their Solid State Storage System Technical Work Group. She earned an BSEE at University of Maryland College Park and a MBA at the University of Phoenix. She has held management and engineering positions at VMware, Dell, and Sun Microsystems. She has ten publications on such subjects as optimizing Oracle, automated tiering, and solid state performance specifications, and has presented at many technical conferences including SNIA Developer Conference and Data Storage Innovation Conference. She is a current member of the SNIA Technical Council.
FMS: the Future of Memory and Storage, will wrap up with a dynamic and engaging Closing Session on Thursday, August 7 at 2:30 PM, offering attendees an exciting interactive opportunity to exchange ideas with leading experts who spoke at FMS and reflect on the key themes and insights from this year's record-breaking event.
Held in Ballroom E of the Santa Clara Convention Center, the 90-minute "Ask Anything" style session will feature thought leaders from across the memory and storage ecosystem. Attendees can expect to hear candid reflections, an interactive exchange of ideas, and valuable takeaways that tie together the week's technical sessions, panels, and keynotes, including Tom Coughlin, who will reflect on his worldwide travels as presented in keynote session #12: "Where in the World is Tom Coughlin."